JP2005322075A - Clock signal output device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock signal output device which can obtain the clock signal with designated duty ratio and also suppress a circuit scale smaller. <P>SOLUTION: An input clock signal 101 is inputted into a frequency divider circuit 100, and a first clock signal 102 and a second clock signal 103 both of which are different in a phase each other with 1/2 frequency for the input clock are outputted. A delay clock signal 201, in which the second clock signal 103 is delayed with designated quantity, and the first clock signal 102 are combined by an exclusive or circuit 301 and outputted as the signal with the designated duty ratio on the same frequency as the input clock signal 101. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a clock signal output device for supplying a clock signal to a semiconductor integrated circuit or the like.

  In a semiconductor integrated circuit that operates in synchronization with a clock signal, for example, in order to satisfy the setup time and hold time in a flip-flop circuit, it has a predetermined duty ratio (the elapsed time from the rising edge to the falling edge of the signal and the rising edge). A clock signal may be required (the elapsed time from the falling edge to the rising edge is a predetermined ratio).

  As a technique for obtaining a clock signal having a predetermined duty ratio, for example, a technique is known in which an input clock signal and a signal obtained by delaying the input clock signal by a delay element are synthesized by an exclusive logical ring circuit (for example, Patent Documents). 1). Furthermore, in order to prevent the duty ratio from being unstablely changed due to variations at the time of manufacturing a semiconductor integrated circuit or the like, it is known that the delay ratio of the delay element is controlled by measuring the duty ratio (for example, , See Patent Document 2).

An example of a semiconductor integrated circuit that operates in synchronization with a clock signal is a double-edge trigger flip-flop that operates in synchronization with a falling edge as well as a rising edge of the clock signal (see Non-Patent Document 1). ). Since both edge trigger flip-flops take in the input clock signal and update the output at both the rising edge and falling edge of the input clock signal, the influence of the duty ratio deterioration of the clock signal is great.
JP 2002-26264 A (Claim 2, paragraph 0006, FIG. 2) Japanese Patent Laid-Open No. 7-253825 (paragraph 0042, FIGS. 5 and 9) William J. et al. Dally / John W. By Paul Ton, edited by Tadahiro Kuroda, Digital System Engineering Application, Maruzen Co., Ltd. (Section 506, Figure 9-14)

  However, in an apparatus that synthesizes an input clock signal and its delay signal with an exclusive OR circuit as described above, the duty ratio can be adjusted by adjusting the delay amount, but the input clock signal itself If the duty ratio is not exactly 50%, a clock signal having a stable duty ratio and cycle cannot be obtained. This is the same even when measuring the duty ratio and controlling the delay amount. In addition, an analog circuit must be used to measure such a duty ratio, and the circuit scale tends to increase. In addition, it is difficult to make the clock signal output device into one chip.

  The present invention has been made paying attention to the above-mentioned problem, and even when a clock signal having a deteriorated duty ratio is input while propagating through the semiconductor integrated circuit, the clock signal having a predetermined duty ratio is input. It is an object of the present invention to provide a clock signal output device capable of obtaining the above-mentioned characteristics and capable of reducing the circuit scale.

In order to solve the above-mentioned problem, the solution taken by the invention of claim 1 is:
A first frequency dividing element that outputs a first frequency-divided clock signal whose logic value is inverted at every rising edge of the input clock signal, and a first frequency element whose logic value is inverted at every falling edge of the input clock signal. A frequency dividing circuit including a second frequency dividing element that outputs a frequency-divided clock signal of 2;
At least one of a clock signal input to the first frequency divider, an input clock signal input to the second frequency divider, a first frequency-divided clock signal, and a second frequency-divided clock signal A delay circuit for delaying one signal by a predetermined amount;
A logic circuit that generates an output clock signal that is an exclusive OR of the first divided clock signal or a delayed signal thereof and the second divided clock signal or a delayed signal;
It is provided with.

  As a result, the first and second frequency-dividing elements output the first and second frequency-divided clock signals each having a duty ratio of exactly 50% at a frequency half that of the input clock signal. Is done. Further, at least one of the clock signal and the first and second divided clock signals input to the first and second frequency dividing elements is delayed by a predetermined delay amount by the delay circuit. . Therefore, the logic circuit takes the exclusive OR of the first divided clock signal or a signal delayed from the first divided clock signal or the signal obtained by delaying the first divided clock signal or the delayed signal from the second divided clock signal. And an output clock signal in which the time difference between the falling timing and the falling timing is changed by a predetermined time corresponding to the delay amount of the delay circuit.

The invention of claim 2
The clock signal output device according to claim 1,
The delay amount from the rising timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the first frequency dividing element is
Shorter than the delay amount from the falling timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the second frequency dividing element. It is comprised so that it may become.

The invention of claim 3
The clock signal output device according to claim 1,
The delay amount from the rising timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the first frequency dividing element is
It is longer than the delay amount from the falling timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the second frequency divider. It is comprised so that it may become.

  Thus, depending on the delay amount set in the delay circuit, the time from the rise timing to the fall timing in the output clock signal, the time from the fall timing to the rise timing, that is, the length of the high level period or low level period Is controlled.

The invention of claim 4
The clock signal output device according to claim 1,
The first frequency dividing element includes a first flip-flop that outputs an inverted output or a non-inverted output as the first divided clock signal,
The second frequency dividing element includes a second flip-flop that outputs an inverted output or a non-inverted output as the second divided clock signal,
Each of the first flip-flop and the second flip-flop has a data input terminal and an inverted output terminal connected to each other,
The first frequency dividing element and the second frequency dividing element are configured to receive the same clock signal or a clock signal delayed by at least one of the first frequency dividing element and the second frequency dividing element.

The invention of claim 5
The clock signal output device according to claim 1,
The first frequency dividing element includes a first flip-flop that outputs an inverted output or a non-inverted output as the first divided clock signal,
The second frequency dividing element includes a second flip-flop that outputs an inverted output or a non-inverted output as the second divided clock signal,
The first flip-flop and the second flip-flop include a data input terminal of one flip-flop and an inverted output terminal of the other flip-flop, and a data input terminal of the other flip-flop and the one flip-flop. Are connected to the non-inverting output terminals of
The first frequency dividing element and the second frequency dividing element are configured to receive the same clock signal or a clock signal delayed by at least one of the first frequency dividing element and the second frequency dividing element.

  As a result, the first and second flip-flops output the first and second frequency-divided clock signals each having a duty ratio of exactly 50% at a frequency half that of the input clock signal. .

The invention of claim 6
6. The clock signal output device according to claim 1, wherein the logic circuit has the same frequency as the clock signal input to the first frequency divider and the second frequency divider. The at least one signal is delayed by a predetermined amount so as to output an output clock signal having a predetermined duty ratio or a difference between a high level period and a low level period being a predetermined time. It is characterized by that.

  As a result, the logic circuit outputs the output clock having the same frequency as the clock signal input to the first and second frequency-dividing elements and a predetermined duty ratio or a difference between the high level period and the low level period being a predetermined time. Output a signal.

The invention of claim 7
7. The clock signal output device according to claim 1, wherein the delay amount of the delay circuit signal is set in accordance with a predetermined control signal. Features.

  According to the invention of claim 7, by enabling the delay amount to be set by a control signal, the phase difference between the first clock signal and the second clock signal can be adjusted during operation, which is necessary. A clock signal with a corresponding duty ratio can be obtained.

The invention of claim 8
8. The clock signal output device according to claim 1, further comprising: an output terminal that outputs the first clock signal to the outside of the clock signal output device; and the first clock signal. Is further provided with at least one output terminal among output terminals for further frequency division.
According to the invention of claim 8, it is possible to output clock signals of various frequencies.

  According to the clock signal output device of the present invention, it is possible to obtain a clock signal having a predetermined duty ratio that satisfies, for example, the setup time and hold time even when the duty ratio of the input clock signal deteriorates. Therefore, the semiconductor integrated circuit can be appropriately operated.

  Further, a complicated analog circuit is not required, and the circuit scale can be easily reduced and can be incorporated into one semiconductor chip.

  Hereinafter, as an embodiment of the present invention, for example, a clock signal having a predetermined frequency and a duty ratio of 50% is transmitted through transmission paths having different delay amounts at the rising edge and the falling edge, thereby causing the duty ratio. A clock signal output device that outputs a clock signal having the original duty ratio based on the clock signal having changed will be described.

Embodiment 1
FIG. 1 is a circuit diagram showing a configuration of a clock signal output apparatus according to Embodiment 1 of the present invention. The clock signal output device includes a frequency divider circuit 100, a delay circuit 200, and a waveform synthesis circuit 300.

  The frequency dividing circuit 100 divides an input clock signal 101 transmitted from a clock signal source (not shown) through a transmission path to a frequency of ½, and a first clock signal 102 and a second clock signal having different phases from each other. The clock signal 103 is output. Specifically, the frequency dividing circuit 100 includes a first flip-flop 111 (for example, a clock edge type D flip-flop) and a second flip-flop 112 (for example, a clock edge type D flip-flop). Has been.

  The first flip-flop 111 and the second flip-flop 112 are respectively provided with reset terminals 113 and 114, and both the reset terminals 113 and 114 are connected to the reset signal 115. The reset signal 115 can be input from an external terminal of the clock signal output device.

  Here, the reset signal 115 is set to the H (High) level.

  At this time, the inverted output of the first flip-flop 111 is input to the data input terminal, and the input clock signal 101 is input to the clock input terminal. As shown in FIG. A non-inverted output whose logic value is inverted every time is output as the first clock signal 102.

  On the other hand, the inverted output of the second flip-flop 112 is input to the data input terminal, the input clock signal 101 is input to the clock input terminal, and the logic value is inverted at every falling edge of the input clock signal 101. A non-inverted output is output as the second clock signal 103.

  Conversely, when the reset signal 115 is set to L (Low) level, the first flip-flop 111 and the second flip-flop 112 are both L (or H) regardless of the input clock signal 101 and the data input terminal. ) Signal is output.

  The delay circuit 200 includes a delay element 210 and outputs a delayed clock signal 201 obtained by delaying the second clock signal 103. The delay amount of the delay element 210 is, for example, a delay time difference ΔT between the delay occurring at the rising edge and the delay occurring at the falling edge in the transmission path through which the clock signal is transmitted from the signal source to the clock signal output device (however, It is set to be the same time as the delay.) Here, the delay time difference ΔT may be measured in advance for a circuit including a clock signal transmission path actually created in advance, or may be obtained by simulation of circuit operation.

  The waveform synthesis circuit 300 includes an exclusive OR circuit 301, and synthesizes the first clock signal 102 and the delayed clock signal 201 to output an output clock signal 302.

  In the clock signal output device configured as described above, the first flip-flop 111 inverts the logical value of the first clock signal 102 in synchronization with the rising edge of the input clock signal 101. That is, the first clock signal 102 is a signal obtained by dividing the input clock signal 101 by two, and is a clock signal whose frequency is ½ of the input clock signal 101 and whose duty ratio is exactly 50%.

  The second flip-flop 112 inverts the logical value of the second clock signal 103 in synchronization with the falling edge of the input clock signal 101. That is, the second clock signal 103 is also a clock signal whose frequency is ½ of the input clock signal 101 and whose duty ratio is exactly 50%.

  Here, the time difference between the rising timings of the first clock signal 102 and the second clock signal 103 is such that the first flip-flop 111 and the second flip-flop 112 are opposite to the input clock signal 101 as described above. The time difference equal to the high pulse width (or low pulse width) of the input clock signal 101 is obtained. On the other hand, the delay amount by the delay element 210 is set equal to the delay time difference ΔT between the delay occurring at the rising edge and the delay occurring at the falling edge in the clock signal transmission path as described above. Therefore, the time difference between the rising timings of the first clock signal 102 and the delayed clock signal 201 obtained by delaying the second clock signal 103 is the rising timing and falling timing in the clock signal before the delay caused by the transmission path. Is equal to the time difference. In addition, the delayed clock signal 201 and the first clock signal 102 are divided by the frequency dividing circuit 100 so that the frequency is ½ of the input clock signal 101 and the duty ratio is accurately 50%. Therefore, by the synthesis by the exclusive OR circuit 301, a clock signal having the same frequency as that of the input clock signal 101 and the same 50% as that before the delay caused by the transmission path is obtained as the output clock signal 302. Therefore, it is possible to easily operate a semiconductor integrated circuit using the output clock signal 302 appropriately.

  As described above, the second clock signal 103 is delayed by the delay time difference ΔT between the rising edge and the falling edge generated in the transmission path of the clock signal, so that the clock can be transmitted regardless of the clock signal frequency and the duty ratio. A clock signal having the same frequency and duty ratio as that output from the signal source can be obtained. However, in order to obtain a clock signal with a duty ratio other than 50%, it is necessary to set the reset signal 115 to the L level in advance before inputting the input clock signal 101 (at the L level). At this time, the flip-flops 111 and 112 are in a state of outputting an L (or H) signal. After that, after a predetermined time has elapsed, the reset signal 115 is set to the H level again, so that the value held in the flip-flops 111 and 112 during the L level period is set as the initial value. .

  Further, by using the flip-flops 111 and 112 as described above, the range of the duty ratio allowed for the input clock signal 101, that is, the high pulse width and the low pulse width of the input clock signal 101 are operated. As long as it is possible, a clock signal having a desired duty ratio such as 50% can be obtained in many cases even when the duty ratio is remarkably deteriorated because the frequency of the input clock signal 101 is high.

  In the above example, it has been described that the rising edge delay is larger. However, when the falling edge delay is larger, if the first clock signal 102 is delayed, it is still the case. Regardless of the frequency and duty ratio of the clock signal, a clock signal having the same frequency and duty ratio as that output from the clock signal source can be obtained.

  For example, if the delay amount of the delay element is shifted by ½ of the period of the input clock signal 101 with respect to the delay time difference ΔT, either the first clock signal 102 or the second clock signal 103 is delayed. It can also be made to do. However, in this case, since the delay amount is determined according to the cycle of the clock signal, the same duty ratio as that of the clock signal source can be obtained only when the clock signal has a predetermined frequency.

  Further, the first clock signal 102 or the second clock signal 103 output from the flip-flops 111 and 112 is not limited to being delayed, but instead of or in addition to them, the flip-flop 111 or the flip-flop Even if the input clock signal 101 input to 112 is delayed, the same effect can be obtained. That is, the difference between the delay amounts of the two clock signals input to the exclusive OR circuit 301 may be the delay time difference ΔT as described above.

  In the above example, the waveform synthesis circuit 300 is configured by one exclusive OR circuit 301. However, the present invention is not limited to this, and an AND circuit, an OR circuit, a NOT circuit, or the like is combined. Even if it is used, it is only necessary to configure logic circuits that perform substantially the same function.

  Furthermore, the delay amount of the delay element is not limited to the delay time difference ΔT in the clock signal transmission path as described above, but by setting the delay amount to a predetermined delay amount, the high level period or the low level period of the clock signal is set. Since it can be changed by the predetermined delay amount, by setting the delay amount according to these frequencies and duty ratios for the input clock signal of any frequency and duty ratio, the same frequency and any A clock signal having a duty ratio can be output.

<< Embodiment 2 >>
A frequency divider circuit 400 as shown in FIG. 3 may be provided in place of the frequency divider circuit 100 as described above. In the following embodiments, components having the same functions as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The frequency dividing circuit 400 includes a first flip-flop 411 (for example, a clock edge type D flip-flop) and a second flip-flop 412 (for example, a clock edge type D flip-flop), and the input clock signal 101 is a first flip-flop. The clocks are input to the clock input terminals of the flip-flop 411 and the second flip-flop 112, respectively. Further, the non-inverted output of the first flip-flop 411 is output as the first clock signal 102 and input to the data input terminal of the second flip-flop 412. The inverted output of the second flip-flop 412 is input to the data input terminal of the first flip-flop 411, and the non-inverted output of the second flip-flop 412 is output as the second clock signal 103. It has become.

  With the configuration as described above, the first flip-flop 411 inverts the logical value of the first clock signal 102 to be output in synchronization with the rising edge of the input clock signal 101. That is, the first flip-flop 411 operates as a divide-by-2 circuit, and the first clock signal 102 is a clock signal whose frequency is ½ of the input clock signal 101 and whose duty ratio is exactly 50%.

  The second flip-flop 412 outputs a signal having the same logical value as that of the first clock signal 102 in synchronization with the falling edge of the input clock signal 101. That is, the second clock signal 103 is also a clock signal with a duty ratio of exactly 50% at a frequency half that of the input clock signal 101.

  In addition, the phase difference between the first clock signal 102 and the second clock signal 103 is such that the first flip-flop 411 and the second flip-flop 412 have opposite edges of the input clock signal 101 as described above. By operating, a phase difference equal to the high pulse width (or low pulse width) of the input clock signal 101 is obtained. That is, the frequency dividing circuit 400 outputs two clock signals 102 and 103 having the same frequency, duty ratio, and phase difference as the frequency dividing circuit 100 in the first embodiment outputs.

  Therefore, also in the present embodiment, as in the case of the first embodiment, the exclusive OR circuit 301 outputs a signal obtained by taking the exclusive OR of the first clock signal 102 and the delayed clock signal 201, so that the input clock Since a clock signal having the same frequency as the signal 101 and a duty ratio of 50% is obtained as the output clock signal 302, the semiconductor integrated circuit can be appropriately operated.

  Further, since the first and second flip-flops 411 and 412 of the frequency divider circuit 400 operate alternately at the rising edge and the falling edge of the input clock signal 101, the inversion of the second flip-flop 412 is performed as in this configuration. Even when the output is fed back to the first flip-flop 411, the timing constraint can be easily satisfied. That is, when configured as in the first embodiment (FIG. 1), in order to satisfy the hold specifications of the flip-flops 111 and 112 and avoid a phenomenon called racing, the delay time from the inverting output to the feedback input is set. Whereas it is necessary to make the time longer than a certain time, in the case of the configuration shown in FIG. 3, the first flip-flop 411 operates at the rising edge of the clock, and the second flip-flop 412. Operates at the falling edge, and since there is a time difference between the rising edge and the falling edge, the hold specification can be easily satisfied without considering the delay time of the feedback wiring.

<< Embodiment 3 >>
A delay circuit 500 as shown in FIG. 4 may be provided in place of the delay circuit 200 as described above. The delay circuit 500 further includes a delay element 211 in addition to the delay circuit 200 of the second embodiment.

  The delay element 211 delays the first clock signal 102 by a predetermined time T0 and inputs the delayed clock signal 202 to the exclusive OR circuit 301.

  Further, the delay element 210 delays the second clock signal 103 by T0 + ΔT and delays the second clock signal 103 by assuming that the delay time difference between the rising edge and the falling edge generated in the clock signal transmission path as described above is ΔT. The signal 201 is input to the exclusive OR circuit 301.

  In the clock signal output device configured as described above, the difference between the delay amounts of the delay elements 211 and 210 is ΔT. Therefore, the exclusive OR circuit 301 is the same as described in the first and second embodiments. The clock signal having the same frequency and duty ratio as that output from the clock signal source can be output. In addition, by setting the delay time T0 to a predetermined size, the phases can be made different without changing the duty ratio of the clock signal output from the exclusive OR circuit 301. Therefore, for example, the delay amount T0 is set so that the phase of the clock signal output from the exclusive OR circuit 301 and other clock signals (clock signals from the same clock signal source via other delay elements) are aligned. In addition, the clock skew can be easily adjusted.

<< Embodiment 4 >>
Instead of the delay circuit 200 in the first embodiment, a delay circuit 600 as shown in FIG. 5 may be provided.

  The delay circuit 600 includes delay elements 610, 611, and 612 having different delay amounts, and is selected by a delay element selection circuit (selector) 620 according to a delay control signal 630 having a value from 0 to 2. One of the output signals of the delay elements 610, 611, and 612 is output as the delayed clock signal 201.

  The specific delay amount of the delay elements 610 to 612 is, for example, that the delay element 610 is a delay amount such that the phase difference between the delayed clock signal 201 and the first clock signal 102 is 90 degrees, and the delay element 611 is The delay amount is such that the phase difference between the delayed clock signal 201 and the first clock signal 102 is 45 degrees. The delay element 612 has a phase difference of 135 degrees between the delayed clock signal 201 and the first clock signal 102. Such a delay amount can be set. When the phase difference is 90 degrees, a duty ratio is 50%, when the phase difference is 45 degrees, a duty ratio is 25%, and when the phase difference is 135 degrees, a clock signal having a duty ratio of 75% is obtained. be able to.

  Note that the delay control signal 630 supplied to the delay element selection circuit 620 can be input from an external terminal of the clock signal output device, a register provided in the clock signal output device, or the like.

  An example of a timing chart of each signal of the clock signal output device having the above configuration is shown in FIG. This figure shows a case where a delay element having a larger delay amount than in the case of the first embodiment (FIG. 2) is selected.

  The delayed clock signal 201 and the first clock signal 102 have a phase difference larger than 90 degrees, the frequency is ½ of the input clock signal 101, and the duty ratio is exactly 50%. Therefore, by synthesizing these signals by the exclusive OR circuit 301, a clock signal having the same frequency as the input clock signal 101 and a duty ratio larger than 50% is obtained as the output clock signal 302.

  Thus, in this embodiment, since the delay element of the delay circuit 600 can be selected, it becomes possible to obtain the output clock signal 302 having a duty ratio corresponding to the delay amount of the selected delay element.

  In this embodiment, the case of selecting three types of delay elements has been described. However, two types or four or more types of delay elements may be provided.

<< Embodiment 5 >>
As shown in FIG. 7, the output of the first clock signal 102 is directly output to the external terminal 703 as compared with the first embodiment, and the first clock signal is further divided by a half frequency. A flip-flop 701 (for example, a clock edge type D flip-flop) and an output terminal 702 for outputting the output signal of the flip-flop 701 to the outside are provided, and these are divided into a two-frequency clock signal and a four-frequency clock signal of the input clock signal 101. You may make it usable as. Further, another frequency-divided clock may be generated and output.

<< Other Embodiments >>
The components described in the above embodiments and modifications may be combined in various ways within a logically possible range. Specifically, for example, in the second, fourth, or fifth embodiment, as described in the first or third embodiment, only the first clock signal is delayed without delaying the second clock signal. Or both may be delayed, or the clock signal input to the frequency dividing circuit 100 or 400 may be delayed.

  Further, the frequency dividing circuit 100 of the first embodiment is used instead of the frequency dividing circuit 400 for the third embodiment, or the frequency dividing circuit 400 is used instead of the frequency dividing circuit 100 for the fourth or fifth embodiment. Also good.

  In the fourth embodiment or the like, the delay circuit 600 may be provided not only for the second clock signal 103 but also for the first clock signal 102.

  Since the clock signal output device according to the present invention can obtain a clock signal having a predetermined duty ratio that satisfies the setup time and hold time even when the duty ratio of the input clock signal deteriorates, The semiconductor integrated circuit can be appropriately operated, and further, since it does not require a complicated analog circuit, it can be easily incorporated into a semiconductor chip, and operates in synchronization with a clock signal. This is useful as a clock signal output device for supplying a clock signal to a semiconductor integrated circuit.

It is a circuit diagram which shows the structure of the clock signal output device of Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the clock signal output device of Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the clock signal output device of Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the clock signal output device of Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the clock signal output device of Embodiment 4 of this invention. It is a timing chart which shows operation | movement of the clock signal output device of Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the clock signal output device of Embodiment 5 of this invention.

Explanation of symbols

100 divider circuit 101 input clock signal 102 first clock signal 103 second clock signal 111 first flip-flop 112 second flip-flop 200 delay circuit 201 delay clock signal 202 delay clock signal 210 delay element 211 delay element 300 Waveform synthesis circuit 301 Exclusive OR circuit 302 Output clock signal 400 Divider circuit 411 First flip-flop 412 Second flip-flop 500 Delay circuit 600 Delay circuit 610 Delay element 611 Delay element 612 Delay element 620 Delay element selection circuit 630 Delay control signal 701 Flip-flop 702 Output terminal 703 Output terminal

Claims (8)

A first frequency dividing element that outputs a first frequency-divided clock signal whose logic value is inverted every rising edge of the input clock signal, and a first frequency element whose logic value is inverted every falling edge of the input clock signal. A frequency dividing circuit including a second frequency dividing element that outputs a frequency-divided clock signal of 2;
At least one of a clock signal input to the first frequency divider, an input clock signal input to the second frequency divider, a first frequency-divided clock signal, and a second frequency-divided clock signal A delay circuit for delaying one signal by a predetermined amount;
A logic circuit that generates an output clock signal that is an exclusive OR of the first divided clock signal or a delayed signal thereof and the second divided clock signal or a delayed signal;
A clock signal output device comprising: The clock signal output device according to claim 1,
The delay amount from the rising timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the first frequency dividing element is
Shorter than the delay amount from the falling timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the second frequency dividing element. It is comprised so that it may become. The clock signal output device characterized by the above-mentioned. The clock signal output device according to claim 1,
The delay amount from the rising timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the first frequency dividing element is
It is longer than the delay amount from the falling timing of the clock signal input to the clock signal output device to the rising or falling timing of the divided clock signal input to the logic circuit via the second frequency dividing element. It is comprised so that it may become. The clock signal output device characterized by the above-mentioned. The clock signal output device according to claim 1,
The first frequency dividing element includes a first flip-flop that outputs an inverted output or a non-inverted output as the first divided clock signal,
The second frequency dividing element includes a second flip-flop that outputs an inverted output or a non-inverted output as the second divided clock signal,
Each of the first flip-flop and the second flip-flop has a data input terminal and an inverted output terminal connected to each other,
A clock signal output device configured to receive the same clock signal or a clock signal delayed by at least one of the first frequency divider and the second frequency divider. The clock signal output device according to claim 1,
The first frequency dividing element includes a first flip-flop that outputs an inverted output or a non-inverted output as the first divided clock signal,
The second frequency dividing element includes a second flip-flop that outputs an inverted output or a non-inverted output as the second divided clock signal,
The first flip-flop and the second flip-flop include a data input terminal of one flip-flop and an inverted output terminal of the other flip-flop, and a data input terminal of the other flip-flop and the one flip-flop. Are connected to the non-inverting output terminals of
A clock signal output device configured to receive the same clock signal or a clock signal delayed by at least one of the first frequency divider and the second frequency divider.   6. The clock signal output device according to claim 1, wherein the logic circuit has the same frequency as the clock signal input to the first frequency divider and the second frequency divider. The at least one signal is delayed by a predetermined amount so as to output an output clock signal in which a predetermined duty ratio or a difference between a high level period and a low level period is a predetermined time. A clock signal output device.   7. The clock signal output device according to claim 1, wherein the delay amount of the delay circuit signal is set in accordance with a predetermined control signal. A clock signal output device.   8. The clock signal output device according to claim 1, further comprising: an output terminal that outputs the first clock signal to the outside of the clock signal output device; and the first clock signal. A clock signal output device comprising at least one of output terminals for further dividing and outputting the output terminal.

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