JPS5975165A - Timing generator - Google Patents

Abstract

PURPOSE:To reduce the number of phase generators by generating plural phase signals by a single phase generator. CONSTITUTION:A times memory 23 is stored with the number of generated phase signals 18 and when a timing selection signal 20 is inputted, the number is loaded in a times counter 24. At the same time, an AND gate 28 is opened. On the other hand, the contents of a phase memory 30 are read out by a test period signal 16 and the phase of output from a counter 31 is controlled minutely by a 1-clock delay 32 and a delay line 33. Every time one phase signal 18 is outputted, the phase counter 31 fetched information from the phase memory 30 and next signal 18 is outputted. Then, loading from the memory 30 to the phase counter 31 is not performed thereafter.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing generator used in an IC testing device, and more particularly to a timing generator having a function of generating a plurality of phase signals during one test period.

A timing generator for an IC test device is broadly divided into a rate generator that determines a test period, and a plurality of phase generators that generate a signal at an arbitrary phase with respect to the test period.

FIG. 1 shows a conventional timing generator, in which only one phase generator is shown for simplicity. Since this changes the timing in real time, when the external timing selection signal 17 is input,
The corresponding test period signal 16 and phase signal 18 are output, and the outline of its operation is as follows.

In FIG. 1, when the timing selection signal 17 is input, it is taken into the timing register 8 in synchronization with the test cycle signal 16 that had been output until then, and is input to the late memory in which the test cycle information is written. 7, the phase memory 11 in which the phase signal information is written is accessed, and the test period information and phase signal information are read out.

A rate generator 21 that generates a test cycle includes a rate counter 2 that determines a test cycle that is an integral multiple of the basic clock cycle from the oscillator 1, and a rate counter that improves the resolution of the test cycle beyond the basic clock cycle. A test period signal 16 is generated by a delay line 6 that delays the output of the second delay line 2 and a rate selector 4 that selects one of the delay lines 3. Among these, the frequency division ratio of the rate counter 2 and the selection of the selector 4 are controlled by the contents of the rate register 5, but since the resolution is increased using the delay line 3, the contents are the delay set in the previous test cycle. It is determined by a delay adder that performs an addition operation between the time (stored in the register 5) and a set value that is less than the period of the basic clock of the current test period (output of the memory 7). Furthermore, in order to supply a basic clock having the same phase as the test periodic signal 16 to the phase generator 22 that generates the phase signal 18, a delay line 9 that delays the output of the oscillator 1 and a delay line 9 that delays the output of the oscillator 1 according to the contents of the rate register 5 are provided. A phase clock 19 is generated by a phase clock selector 10 for selecting time.

On the other hand, the phase generator 22 generates a coincidence output at the time when the phase information read out from the face memory 11 and set in the phase register 12 matches the value counted by the phase clock 19 and the phase counter 16. In order to further increase the phase resolution, this -output signal is input to a delay line, and its output is selected by a phase selector 15 to output a phase signal 18.

That is, the phase generator 22 has a function of outputting an arbitrary phase pulse once during one test period.

However, as memory ICs and logic ICs, which are the test targets of IC test equipment, have become highly integrated, the number of internal elements has increased, and testing has become increasingly complex and requires timing. Therefore, multiple phase signals are required during one test period. For this reason, conventionally, a plurality of phase generators 22 must be provided and their output phase signals must be combined, which increases the hardware of the timing generator, resulting in an increase in cost and power consumption.

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art.
An object of the present invention is to provide a timing generator equipped with a phase generator capable of generating a plurality of phase signals during one test period.

The present invention provides a counter-based number control means for controlling the number of phase signals specified by a selection signal to be generated in each test period, and a number control means centered on a counter that controls the number of phase signals specified by a selection signal to be generated at equal time intervals specified by the selection signal from the test period signal. The present invention is characterized in that it is provided with phase control means comprising a counter, an arithmetic circuit, a delay circuit, etc. for controlling the generation of each phase signal.

The present invention will be explained below using examples. FIG. 2 is a schematic block diagram of the device of the present invention, in which the late generator 21 is almost the same as the conventional one in FIG. 1, and the face generator 22A, which is a feature of the present invention, is shown in FIG. has been done. With this one generator 22A,
- generating multiple phase signals 18 during the test period; Its ° 4 configuration and operation are as follows.

In FIG. 3, the control rA1 of the number of generated phase signals 18 is:
This is performed mainly using the times counter 24 and the AND gate 28. The times memory 23 stores the number of phase signals 18 generated, and when the timing selection signal 20 is input, this number (hereinafter referred to as 2) is read out from the times memory. The value 2 is loaded into the times counter 24 by the test period signal 16, and at the same time, the RS flip-flop 27 is set by the signal 16, and the AND gate 28 is opened.

On the other hand, as will be described in detail later, the contents of the phase memory 30 are read out by the test period signal 16, and the output from the counter 31 is output with a one clock delay '52. The phase is finely controlled by the delay line 36 and output as a phase signal 18. Every time this phase signal 18 is output, the output of the 1 clock delay 32 causes the AND gate 28. Phase counter 3 via or gate 29
1 takes in information from the phase memory 60 and outputs the next phase signal 18. From 1 onwards, the contents of the times counter 24 are subtracted by 1 for each output of the phase signal 18. However, the output of the circuit consisting of the inverter 25 and the gate 26 outputs 1 when the contents of the times counter 24 becomes 1 and resets the flip-flop 27.
Since the AND gate 28 is turned off, the phase counter 31 is not loaded from the memory 30 after this point. In other words, the number of phase signals written in the times memory 23 during one test period (2 in this case) is output.The number control is 0 or more, but the phase control of each phase signal is as follows. This is done as follows. FIG. 4 shows the relationship between the test period T and the period of the phase signal 18, where the time to the first phase signal a and the interval between the phase signals are equal Tp. For convenience of explanation, as shown in FIG. 5, the period Tc of the phase clock 19 is set to 10 ns + the phase signal period Tp.
is 25ns. When the test cycle signal 16 is inputted, the phase counter 61 receives two pulses from the phase memory 30.
(generally m-integer, and so on), and D flip-flop 66 is set to 5(n). Further, the D flip-flop 35 is reset, the RS flip-flop 8 is set, and the selector 37 sets the value 5 of the flip-flop 36 according to the setting condition of the flip-flop 38.
(n) is selected as its output 4, so that the delay line 33 has a delay time of 5 ns (considering n in units of ns years,
The one clock delay 32 is set to 0 ns (a time that is an integer multiple of Tc, rounding down values less than 10 ns when n is a yearly value). In other words, 1 clock delay'52
And the delay line 63 provides a delay of A=5 ns corresponding to the output l of the selector 37.

On the other hand, the phase counter 61 decrements its contents by 1 every time the phase clock 190 with a period Tc=10 ns is input, and outputs it when it becomes 0. Therefore, this is the setting value m = 2
0 output every 2TC=20 ns (m'l"c) for (Fig. 5). By outputting this phase signal a, RS
The flip-flop 68 is reset, and the selector 37 thereafter selects the output of the D flip-flop 35 as l.

Here, when the test period signal 16 is input to the delay adder 34, the flip-flop 35 has been reset by the test period signal 16, so the value 0 of the D flip-flop 35 and the value 5 (
n) is performed to obtain an output 5(n). Therefore, this calculation result 5(n) is set in the D flip-flop 35 by the output signal of the phase counter 61 that generates the first phase signal a, and the delay adder 34 sets the value 5(n) of this D flip-flop 65. , performs an addition operation on the value 5(n) of the phase memory 30, and outputs the value 1.
0 (2n) is maintained. Further, 2(m) is loaded into the phase counter 31 via the AND circuit 28. Therefore, the phase counter 31 generates an output at time 4 (2mTc) in FIG.
8 - The output value 10 (2n) of the delay adder 34 is set in the flip-flop 65. As a result, the 1 clock delay is set to 10ns, and the delay line 33
is set to OnS. Therefore phase counter 31
The output passes through a total of 10 ns delay of the set 1 clock delay 32 and delay line 33, and outputs the phase signal S shown in FIG. 5 at time 5 (2mTc+2nTc).

As in this example, the delay circuit 32. 6 and the delay adder 64 etc. that control them, it is possible to control the phase narrower than that of the phase clock 19. As is clear from the above embodiments, the present invention allows multiple This has the effect of reducing the number of phase generators in the timing generator.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional timing generator, FIG. 2 is a functional block diagram of a timing generator of the present invention, FIG. 6 is a diagram showing an embodiment of a phase generator that is a feature of the present invention, and FIG. The figure is a time chart showing the operation of the timing generator, and FIG. 5 is a time chart showing the operation of the phase generator. 16...Synchronization signal 18...Phase signal 19...
Phase clock 20... Selection signal 21... Rate generator 22A... Phase generator 23... Times memory 24... Times counter 30... Phase memory 31... Phase counter 32... 1 clock delay 66...Delay line 34...Delay adder 11° 2nd Fig. 1 Fig. 3

Claims (1)

[Claims] 1 of the clock oscillators that have a built-in periodic signal having a period specified by the input timing selection signal (a rate generator that generates from the i force, and a number of positions specified by the selection signal for each period of the periodic signal) A number control means for generating a signal under the control of a counter and a phase control means for controlling the phase signal to be outputted at equal intervals from the periodic signal at the time interval specified by the selection signal during the -period. A timing generator comprising a phase generator that generates a plurality of phase signals.