JP3633988B2 - Timing edge generation circuit for semiconductor IC test equipment - Google Patents

Timing edge generation circuit for semiconductor IC test equipment Download PDF

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Publication number
JP3633988B2
JP3633988B2 JP06170795A JP6170795A JP3633988B2 JP 3633988 B2 JP3633988 B2 JP 3633988B2 JP 06170795 A JP06170795 A JP 06170795A JP 6170795 A JP6170795 A JP 6170795A JP 3633988 B2 JP3633988 B2 JP 3633988B2
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Prior art keywords
signal
logic
circuit
resolution
delay
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JPH08146099A (en
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政利 佐藤
則之 増田
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株式会社アドバンテスト
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922Timing generation or clock distribution

Description

[0001]
[Industrial application fields]
The present invention relates to a timing edge generation and generation circuit for accurately determining rising and falling timings when generating a signal waveform to be applied to a device in a semiconductor IC test apparatus.
[0002]
[Prior art]
FIG. 4 shows a configuration diagram of an example of a timing edge generation circuit as a prior art. FIG. 4 shows a timing edge generation circuit having three systems for generating timing edges in parallel. First, the reason for having a plurality of systems will be described. There is a test cycle in the procedure for measuring the IC to be measured by the semiconductor IC test apparatus, and this test cycle is set by a user who is a user by a program. The test cycle time is not a fixed time and can be set arbitrarily. The driver output waveform generated during the test cycle is applied from the driver 90 to the IC to be measured. This relationship is shown in FIG.
[0003]
In each of the test cycles of FIG. 5, one or two driver output waveforms actually required for the IC test are generated with phase differences t1, t2, t3, etc. from the start of the test cycle. Therefore, when one driver output waveform is required, two timing edges are required for rising and falling, and when two driver output waveforms are required, four timing edges are required. Since FIG. 5 shows an example in which three driver output waveforms are generated between two cycles, cycle 1 and cycle 2, three timing edges are required in one cycle. Timing edge 1, timing edge 2 and timing edge 3 indicates that the rising and falling edges are controlled at each timing edge.
[0004]
By the way, normally, one timing generator is configured to generate one timing edge during one test cycle. Therefore, when three timing edges are required in one test cycle, as shown in FIG. 4, three circuits are configured in parallel, and are synthesized by OR circuits 40 1 and 40 2 , and RS · FF (set Reset flip-flop) 50, a driver output waveform is generated and output from the driver 51.
[0005]
One system at the top of FIG. 4 will be described. The one system consists cascaded timing generator 1 and formats the control gate 22 and the path skew adjuster 30, RS a set signal to the RS · FF50 its timing edge 1 through the OR circuit 40 1 or through an OR circuit 40 2,・ A reset signal is given to FF50. Although marked in FIG. 4 format control gate 22 1, but was meant for one system and 22 1, especially if it is not necessary to distinguish, hereinafter also referred to as 22.
[0006]
The timing generator 1 gives a timing edge having an arbitrary delay time, that is, a phase difference t1, to the format control gate 22, and includes a logic delay circuit 10, an enable gate 11, and a variable delay circuit 12. Although not shown, the logic delay circuit 10 is a high-speed circuit that drives a ck-synchronous delay circuit and a variable delay circuit 12 that drive a plurality of cascade-connected FFs (flip-flops) with a high-precision clock signal (ck). A resolution data memory M is provided, and the ck synchronous delay circuit generates an enable signal by delaying the delay of the signal received from the PG (pattern generator) 5 in units of ck periods for an arbitrary time in synchronization with ck. The enable gate 11 is opened by this enable signal, and the high-accuracy clock signal ck serving as a timing edge is passed.
[0007]
Although the frequency of ck can be changed by design, for example, if the frequency is 200 MHz, one period is 5 ns, and the accuracy can be narrowed down with an accuracy of 5 ns. However, time settings such as test cycles and timing edges are performed in high resolution units of 5 ns or less. For example, if it is performed in units of 1 ns, a resolution of at least 1 ns, which is higher than the period of ck, is required. Therefore, a highly accurate variable delay circuit 12 is provided at the subsequent stage of the enable gate 11, and the delay time is highly accurate in units of 1 ns in response to a delay time setting signal from the high resolution data memory M that stores a delay amount of 5 ns or less of the setting program. It is attached to. Moreover, this delay time can be varied in real time.
[0008]
An example of the highly accurate variable delay circuit 12 of the timing generator 1 is shown in FIG. FIG. 6 shows an example of a variable delay circuit that gives a delay time by a gate circuit composed of an IC. A pulse signal is input to the input terminal 13 and a delay time setting signal is input to the input terminal 14. The delay time setting signal is applied to AND gates 15 1 and 15 2, Izure or is selected gate opens. For example, when the gate 15 1 is selected, the pulse signal passes through the OR circuit 17 is given a delay of 2ns delay elements 16. Pulse signal when the gate 15 2 is selected in the reverse passes through the OR circuit 17 without delay. Similarly, for example, a delay is given or directly passed by a delay element 18 of 1 ns or a delay element 19 of 500 ps, and an arbitrary delay time is given. In this example, an arbitrary delay time can be given up to 4 ns in units of 500 ps.
[0009]
In FIG. 4, in the format control 20, an FC (format control main part) 21 receives a signal from the PG 5, processes the signal, and gives a gate signal to each of the format control gates 22 1 , 22 2 , and 22 3 .
In the format control gate 22 1, or to use a high-accuracy timing edge signal from the timing generator 1 to the rising of the driver output waveform, selects whether to use the falling. The selected timing edge signal delay time in a path skew adjuster 30 is sent is adjusted to an OR circuit 40 1 or 40 2.
[0010]
Here, the skew refers to a deviation from an expected value of the phase or time generated between the signals due to variations in the delay time of the transmission system when the same signal is transmitted in a plurality of timing signal transmission systems. That here refers deviation from the expected value of the delay time of six transmission system to send a pulse signal to the OR circuit 40 1 and 40 2, the variation. Therefore, the path skew adjuster 30 adjusts to this expected value. Normally, it is adjusted to the slowest delay time among the six transmission systems. The variable delay circuits 33 and 34 may have the same structure and different delay time as the variable delay circuit 12 in the timing generator 1. Since the adjustment of the path skew may be fixed once adjusted to the expected value of the path skew, a delay signal is given by a register.
[0011]
FIG. 7 shows a timing diagram related to the delay time thus far. The test cycle of FIG. 7A and the delay time of the timing edge of FIG. 7E are determined by the user. For example, the test cycle 1 is 38 ns and the delay time is 14 ns, the test cycle 2 is 33 ns and the delay time is 14 ns. Decide and write to the program. The high-precision clock signal ck in (B) has a frequency of 200 MHz and a period of 5 ns. Then, the RATE signal in (C) generates a 5 ns pulse including the end of the test cycle, and the data in the delay time from the rise of the RATE signal is sent to the PADAT in (D) to determine the period of the test cycle.
[0012]
In the test cycle 1, the delay time of the timing edge in FIG. Therefore, an enable signal (F) of 10 ns to 15 ns is transmitted from the logic delay circuit 10, and a ck signal of 10 ns to 12.5 ns is transmitted from the enable gate 11. In the variable delay circuit 12, the ck signal is delayed by 4 ns to obtain the output waveform of FIG. Since the path skew adjuster 30 gives a fixed correction time that always becomes an expected skew value for the path, for example, assuming that the rising system and the falling system are both 10 ns, the output waveform is as shown in FIG. It is given to 1 or 40 2.
[0013]
Timing edges are generated as described above. A series of high-accuracy timing systems using analog signals is an important point for determining whether the timing accuracy of the semiconductor IC test apparatus is good or bad. In the conventional circuit configuration of FIG. 4, three systems of timing edge generators are configured in parallel. That is, using six transmission systems including rising and falling systems, timing edge signals, which are analog signals, are generated by the timing generators 1, 2, and 3, and the skew is adjusted by the path skew adjuster 30 via the format control gate 22. Then, the waveform is generated by the RS / FF 50 via the OR circuit 40.
[0014]
[Problems to be solved by the invention]
Timing edge accuracy is an important factor in determining the performance of a semiconductor IC tester. In order to improve the timing accuracy, a series of high-accuracy timing systems having a long timing edge signal in the circuit configuration of FIG. 4, that is, a high-accuracy clock signal ck is sent from the timing generator to the format control gate, path skew adjuster, and OR circuit. There was a problem of wanting to make the route through as short as possible. This is because the longer the path of this series of high-accuracy timing systems is, the more easily affected by the surroundings, the more likely it is to generate jitter, and the deterioration of timing accuracy.
[0015]
There is also a problem that it is difficult to accurately predict how much timing accuracy deteriorates in this high-accuracy timing system at the circuit design stage. For example, in a system in which the delay time due to the path length is about 50 ns, jitter may occur at 60 ps depending on the production.
Further, a path skew adjuster that requires a high-accuracy delay of an analog signal has a large number of components and is expensive to manufacture.
In addition, since there is a large amount of analog hardware that requires overall accuracy, it has been difficult to simplify circuit design and adjustment.
[0016]
[Means for solving problems]
In order to solve the above problems, a series of high-accuracy timing systems of analog signals were shortened as much as possible to reduce the delay time of the system, and the corresponding part was replaced with a logic circuit.
Specifically, the analog signal high-accuracy timing system includes only an enable gate for passing a high-accuracy clock signal and a variable delay circuit for obtaining high resolution. Therefore, all the conventional path skew adjusters, format control gates, OR circuits, etc. are provided in the logic circuit section, and many of them are solved by the logic operation means. This will be described in detail below.
[0017]
The present invention is based on the concept of a conventional circuit configuration, that is, a timing edge is generated by a timing generator, the timing edge is selected from a rising edge or a falling edge by a format control gate, and six timing edges are transmitted by a path skew adjuster. System path skew is adjusted to be the same, and three set signals are put together in the OR circuit to give the set signal to the RS / FF, and the three reset signals are put together in the OR circuit and the reset signal is sent to the RS / FF. This is a completely different concept of the configuration for giving the waveform.
[0018]
As for the circuit configuration, first, the circuit configuration of the conventional timing generator is divided into two, and the logic delay circuit receives a signal from the PG as in the prior art and causes a logic delay of a high-precision clock signal ck period. On the other hand, an enable gate and a variable delay circuit are placed in front of the final stage RS / FF, and the enable gate receives a ck signal that is a highly accurate timing edge, and applies the ck signal to the variable delay circuit to provide a high resolution delay. Then, the output of the variable delay circuit is directly supplied to the RS / FF as a set signal or a reset signal to generate a waveform. In other words, the path of the conventional high-accuracy timing system is made very short, and the conventional six are combined into two.
[0019]
The logic pulse signal of the ck cycle accuracy of the logic delay circuit is divided into a set signal and a reset signal by the format control gate, and the set system collects three set signals by the OR gate and sends them to the next logic variable delay circuit. In the reset system, the three logic pulse signals are similarly collected by the OR gate and sent to the logic variable delay circuit in the next stage. A high resolution signal having a ck period accuracy or less received from the PG by the logic delay circuit is also classified into a set signal or a reset signal by the signal selector of the format control gate and sent to the respective logic delay setting circuits.
[0020]
In the logic delay setting circuit, the high resolution signal data sent from the logic delay circuit, the path skew correction value, and a delay time signal obtained by adding an offset value as necessary are transmitted to the logic variable delay circuit. For this reason, the logic delay setting circuit selects one or a plurality of high resolution signals sent from the logic delay circuit, and the small data selector selects a high resolution signal having a small data value.
[0021]
The logic variable delay circuit receives the delay time signal from the logic delay setting circuit, and delays the logic pulse signal from the logic delay circuit by the same ck synchronous delay circuit as that of the logic delay circuit for the delay time of ck cycle unit or more. This delayed logic pulse becomes an enable signal, this enable signal is applied to the enable gate, and the high precision clock signal ck is selected. A high resolution signal of ck cycle unit or less is temporarily stored in a high resolution data memory and drives a high resolution variable delay circuit. The output signal of this variable delay circuit is given to RS / FF as a set signal or a reset signal.
[Action]
[0022]
As described above, the present invention integrates the conventional timing generator, format control, path skew adjuster to OR circuit, that is, the timing edge transmission system of 6 analog signals, without changing the signal form from PG. Since the circuit is operated as logically as possible, the path of the high-accuracy timing system becomes very short, and since only two paths are required, the path skew and jitter are very small.
[0023]
【Example】
FIG. 1 shows one embodiment of the present invention, FIG. 2 shows another embodiment, and FIG. 3 shows a timing chart of the present invention. Portions corresponding to those in FIGS. 4 and 7 are denoted by the same reference numerals.
This will be described with reference to FIG. First, the circuit configuration is compared with the conventional configuration diagram, FIG. The configuration of the timing generator 1 in FIG. 4 is divided into two, and a signal from the PG (pattern generator) 5 is received by the logic delay circuit 10 in the same form as the conventional one. The enable gate 11 and the variable delay circuit 12 are placed in front of the final stage RS · FF 50. The path skew adjuster 30 of the conventional timing edge circuit is eliminated, and a logic delay setting circuit 70 and a logic variable delay circuit 80 for logically adjusting the path skew are provided. The format control function is the same for both, but the conventional format control gate 22 handles timing edges of a high-precision timing system, but the present invention handles logical signals. The circuit configuration and circuit operation will be described below.
[0024]
The signal from PG 5 is received by the three logic delay circuits 10 and the FC 61 of the format control 60 in the same form as before. Three logical delay circuit 10 in the resolution delays the delayed signal over ck units ck synchronous delay circuit, the logic variable delay circuit 80 1 and 80 2 via the format control gate 62 and the OR gate 67 1 or 67 2 To transmit. Here, the 67 1 and 80 1 rises based waveform generator, 67 2 and 80 2 are meant falling system, if there is no particular need to distinguish to that 67 and 80.
A high resolution signal having a resolution of ck cycle unit or less is immediately sent out, divided into a rising system and a falling system via a signal selector 65 of the format control gate 62, and sent to a small data selector 71 of the logic delay setting circuit 70. It is done. The signal selector 65 selects a high-resolution signal as a rising signal or a falling signal, and sends an H signal to an unselected side to make it an invalid signal. For this purpose, it is preferable to use two input 2-signal multiplexers.
[0025]
The logic delay setting circuit 70 includes a small data selector 71, a register 72, and a high-speed adder 73. Since one or a plurality of high resolution signals are sent from the three logic delay circuits 10 to the small data selector 71, a small data value, that is, the data with the earliest time is selected and extracted, and the data in the register 72 and the adder The sum is added at 73 and transmitted to the logic variable delay circuit 80. This is because only a plurality of signals having a ck cycle unit or less can be executed, and the minimum signal is a correct signal. In the register 72, a correction value for the path skew is set. Since the high-precision timing system is only two, one register 72 1 or 72 2 may be zero.
[0026]
The logic variable delay circuit 80 divides the signal from the logic delay setting circuit 70 into a resolution of ck cycle unit or more and the delay of the ck cycle unit or more is the same ck synchronous delay circuit as the logic delay circuit. Is delayed and sent to the enable gate 11 as an enable signal. Further, the delay signal of ck cycle unit or less is stored in the high resolution data memory M, and the high resolution variable delay circuit 12 is driven.
[0027]
In the enable gate 11 1 rising system opens the gate at the enable signal from the logic variable delay circuit 80 1, is passed through the high-accuracy clock signal ck to the timing edge. Ck signal passed through becomes rising timing edge given the variable delay circuit 12 1 with a delay of less high resolution ck cycle unit, gives a set signal to the RS · FF50.
Similarly, open the gate with the enable signal from the logic variable delay circuits 80 2, the enable gate 11 2 falling system, and passed through a precision clock signal ck, the variable delay circuit 12 of 2 or less ck cycle unit of the high-resolution A delay is applied to form a falling timing edge, and a reset signal is applied to the RS / FF 50 to generate a waveform.
[0028]
Another embodiment of FIG. 2 will be described. FIG. 2 is different from FIG. 1 in that a timing offset register 74 and its adder 75 are added to the logic delay setting circuit 70, respectively. This is because it may be necessary for timing adjustment of the entire semiconductor IC test apparatus, and may be necessary, for example, to synchronize with the timing on the expected value detection side. Moreover, not only a positive offset but also a negative offset within the delay time of this route can be set.
[0029]
In both the embodiments of FIGS. 1 and 2, the adders 73 and 75 in the logic delay setting circuit 70 must operate at high speed in real time. This is because it should not be delayed from the logic pulse signal from the logic delay circuit 10 on the input side. Therefore, a delay circuit may be inserted between the OR circuit 67 and the logic variable delay circuit 80 as necessary in order to obtain all synchronization, and the timings may be shifted as a whole.
[0030]
FIG. 3 shows a timing chart of the circuit according to the present invention, which will be described in comparison with FIG. The conditions are the same as in FIG. 3A is the same as FIG. 7 until (A) test cycle, (B) high-precision clock signal ck, (C) RATE signal, (D) PADAT, and (E) delay time. When generating the rising timing edge test cycle 1, the enable signal supplied from the logic variable delay circuits 80 1 to enable the gate 11 1 (F) is composed from 20ns to 10ns later than at the time of FIG. That is, the sum of 4 ns for the variable delay circuit output in FIG. 7 and 10 ns for the output of the path skew adjuster, of 14 ns, is an integer multiple of the ck period 5 ns, and is delayed by 5 ns × 2 = 10 ns. This is because delayed by ck synchronous delay circuit of the logic variable delay circuit 80 1.
[0031]
HRDAT of Figure 3 applied to the high-resolution data memory M of the logic variable delay circuit 80 1 (G) is a 4ns of the difference between the above 14ns and 10 ns. Accordingly, the enable gate output of Figure 3 that is output from the enable gate 11 1 (H), the logical product (AND), and the test cycle 1 the tip of the precision clock signal of the enable signal and (B) of (F) 20 ns later. Then the output of the variable delay circuit 12 1 becomes 24ns delay as shown in Fig. 3 (I).
[0032]
From the generation of the timing edge with the enable signal as described above to the application to the RS / FF 50, the conventional circuit of FIG. 7 gives a delay time of 14 ns with a highly accurate variable delay circuit. Then, 4 ns is sufficient. In other words, a delay within one cycle of the high-precision clock signal ck is required.
[0033]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
1. Since most of the conventional high precision timing system circuits that handle timing edges can be transferred to the logic circuit section 9 in the present invention, the high precision timing system of the present invention has become very short. High-precision timing edges can be obtained. For example, the conventional delay time of 10 ns to 50 ns due to the path length can be shortened to one cycle of the high-accuracy clock signal ck and 5 ns or less in the present invention.
2. Therefore, it becomes difficult to be influenced by the surroundings, and the jitter which is the fluctuation of the waveform is greatly reduced. In the conventional example, 60 ps can be reduced to 20 ps or less in the present invention.
3. The variable delay circuits 33 and 34 of the path skew adjuster 30 necessary for the conventional timing edge signal high-accuracy timing system are expensive and difficult to manufacture. became.
4. Since the number of logic circuits has increased, it has become possible to make customer ICs that could not be achieved in the past.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of the present invention.
FIG. 2 is a configuration diagram of another embodiment of the present invention.
3 is a timing chart of FIGS. 1 and 2. FIG.
FIG. 4 is a configuration diagram of a conventional example.
FIG. 5 is an explanatory diagram of driver output waveforms and timing edges in a test cycle.
FIG. 6 is a configuration diagram of an example of a variable delay circuit.
7 is a timing diagram of FIG. 4. FIG.
[Explanation of symbols]
1, 2, 3 Timing generator 5 PG (timing generator)
9 logic circuit section 10 logic delay circuits 11, 11 1 , 11 2 enable gates 12, 12 1 , 12 2 variable delay circuit 20 format control 21 FC (format control main section)
22, 22 1 , 22 2 , 22 3 format control gate 23, 24 AND gate 30, 30 1 , 30 2 , 30 3 path skew adjuster 31, 32 register 33, 34 variable delay circuit 40, 40 1 , 40 2 OR circuit 50 RS · FF (set reset flip flop)
51 Driver 60 Format control 61 FC (Format control main part)
62, 62 1 , 62 2 , 62 3 format control gate 63, 64 AND gate 65, 65 1 , 65 2 signal selector 67, 67 1 , 67 2 OR gate 70, 70 1 , 70 2 logic delay setting circuit 71, 71 1 , 71 2 Small data selectors 72, 72 1 , 72 2 registers 73, 73 1 , 73 2 adders 74, 74 1 , 74 2 registers 75, 75 1 , 75 2 adders 80, 80 1 , 80 2 logic Variable delay circuit M High resolution data memory

Claims (4)

  1. In a timing edge generation circuit that generates a plurality of timing edges during one test cycle,
    The enable signal delayed by the sum of a value of the high-precision clock signal ( hereinafter referred to as ck ) of the signal from PG (5) and a value of the ck cycle or less and a value of the sum of the correction value of the path skew and the ck cycle or more. And a high-resolution signal representing a value less than the ck period of the sum of the correction values of the path skew and a value less than the ck period of the signal from PG (5), each of the rising system and the falling system outputs A logic circuit section (9);
    Two enable gates (11 1 , 11 2 ) of a rising system and a falling system that allow a high-accuracy clock signal ck that becomes a timing edge to pass through an enable signal from the logic circuit section (9);
    Two variable delay circuits (12 1 , 12 2 ) of the rising system and the falling system that delay the timing edge passing through the enable gate (11 1 , 11 2 ) with high resolution and output to the RS · FF (50). When,
    A timing edge generation circuit for a semiconductor IC test apparatus.
  2. In a timing edge generation circuit that generates a plurality of timing edges during one test cycle,
    A signal necessary to generate one timing edge is received from PG (5) and processed, and a logic pulse of the ck synchronous delay circuit and a high resolution signal with a resolution of one cycle or less of the high precision clock signal ck are output. A plurality of logic delay circuits (10);
    Format control (20) that receives a signal from the PG (5) and branches an output signal of one logic pulse and a high resolution signal from the plurality of logic delay circuits (10) into a rising system and a falling system. When,
    A logical delay setting circuit (70 1 ) for receiving the high-resolution signal of the rising system, adding a path skew correction value, and outputting a delay time signal;
    A logical delay setting circuit (70 2 ) that receives the falling-side high-resolution signal, adds a path skew correction value, and outputs a delay time signal;
    In response to a logic pulse from the plurality of logic delay circuits (10) in the rising system and a delay time signal from the logic delay setting circuit (70 1 ), the logic pulse is delayed by a delay time in units of ck periods of the delay time signal. A logic variable delay circuit (80 1 ) that outputs an enable signal obtained by delaying the signal with a ck synchronous delay circuit, and temporarily stores and outputs a high resolution signal equal to or less than the ck period of the delay time signal in the high resolution data memory (M) When,
    In response to the logic pulse from the plurality of logic delay circuits (10) in the falling system and the delay time signal from the logic delay setting circuit (70 2 ), the logic is output with a delay time in units of ck periods of the delay time signal. A logic variable delay circuit (80 2 ) that outputs an enable signal obtained by delaying a pulse by a ck synchronous delay circuit and temporarily stores and outputs a high resolution signal equal to or shorter than the ck period of the delay time signal in the high resolution data memory (M). )When,
    An enable gate (11 1 ) for receiving the enable signal from the logic variable delay circuit (80 1 ) and passing the high-accuracy clock signal ck;
    An enable gate (11 2 ) that receives the enable signal from the logic variable delay circuit (80 2 ) and passes the high-accuracy clock signal ck;
    The high precision clock signal ck from the enable gate (11 1 ) is input, the high resolution signal from the logic variable delay circuit (80 1 ) is received, the input high precision clock signal ck is delayed with high resolution, and RS A variable delay circuit (12 1 ) that outputs to the FF (50);
    The high precision clock signal ck from the enable gate (11 2 ) is input, the high resolution signal from the logic variable delay circuit (80 2 ) is received, the input high precision clock signal ck is delayed with high resolution, and RS A variable delay circuit (12 2 ) that outputs to the FF (50);
    A timing edge generation circuit for a semiconductor IC test apparatus.
  3. Two logic delay setting circuits (70) of a rising system and a falling system receive a plurality of high resolution signals from the logic delay circuit (10), select a small data value from a small data value (71), A register (72) storing a path skew correction value, and an adder (73) for adding the data value from the small data selector (71) and the path skew correction value from the register (72). The timing edge generation circuit of the semiconductor IC test apparatus according to claim 2, wherein each of the timing edge generation circuits is provided.
  4. Two logic delay setting circuits (70) of a rising system and a falling system receive a plurality of high resolution signals from the logic delay circuit (10), select a small data value from a small data value (71), A register (72) storing a path skew correction value; an adder (73) for adding the data value from the small data selector (71) and the path skew correction value from the register (72); A register (74) for storing a plus / minus offset value; and an adder (75) for adding the output data of the adder (73) and the offset value of the register (74). 3. The timing edge generation circuit of the semiconductor IC test apparatus according to claim 2, wherein:
JP06170795A 1994-09-19 1995-02-24 Timing edge generation circuit for semiconductor IC test equipment Expired - Fee Related JP3633988B2 (en)

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JP24990494 1994-09-19
JP6-249904 1994-09-19
JP06170795A JP3633988B2 (en) 1994-09-19 1995-02-24 Timing edge generation circuit for semiconductor IC test equipment

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JP06170795A JP3633988B2 (en) 1994-09-19 1995-02-24 Timing edge generation circuit for semiconductor IC test equipment
DE1995134735 DE19534735C2 (en) 1994-09-19 1995-09-19 Clock edge shaping circuit and method for IC test system

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JP3633988B2 true JP3633988B2 (en) 2005-03-30

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