JPS59225367A - Timing signal generator - Google Patents

Abstract

PURPOSE:To achieve a highly accurate timing test for an IC containing an oscillator and an IC using an external clock by providing a means of converting a basic clock signal oscillated from an oscillator into a basic clock signal of a high frequency. CONSTITUTION:This is composed of an oscillator 2100 for generating a basic clock 116, a rate generator 2200 for generating a test synchronous signal 107 receiving the basic clock 116, a timing selection signal 106 and a control signal 117 as input, a phase clock generator 2300 for outputting a clock signal 110 synchronizing the test synchronous signal 107 receiving the basic clock 116 and the test synchronous signal 107 as input and a phase generator 114 for outputting a timing signal 114 receiving the clock signal or the like as input. Then, depending on whether the IC to be tested is an oscillator-built-in type or not, the test synchronous signal 107 and the timing signal 114 are outputted according to the IC being tested.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a timing generator, and particularly to an IC and LS.
This invention relates to a timing generator that is optimal for a test device that performs high-precision timing tests such as I.

[Background of the invention]

In recent years, ICs and LSIs with built-in oscillation circuits have been proposed for use in microgrossers, one-chip microcomputers, calculators, and games in order to increase the packaging density and reduce the cost of substrates. ICs and LSIs with built-in nine oscillators like this
When testing, all test patterns must be applied in synchronization with the output signal of the built-in oscillator (hereinafter referred to as device clock), and all output signals of the device (IC and LSI) must be judged. That is, it is necessary to perform IC and LSI'5 tests using the device clock as the test cycle.

On the other hand, for ICs and LSIs that do not have a built-in oscillator, it is necessary to generate a complete test cycle using a timing generator within the test equipment, apply a test pattern in synchronization with the test cycle, and judge the output of the device.

Both test equipment for devices with built-in oscillators and test equipment for external clock type devices? Providing a separate device will lead to a decrease in the operating rate of the test equipment and an increase in the number of test equipment used, which in turn will be a major factor in the rise in the prices of ICs and LSIs due to increased test costs. However, it has been difficult to adequately test devices with built-in oscillators that can operate at high speed due to the low test accuracy, especially timing accuracy when testing devices with built-in oscillators.

An example of this shared testing device will be explained with reference to FIG.

This test bag @ consists of a test pattern 101 to be applied to the IC under test 6, a pattern generator 1 that generates an expected value of output 8 of the IC under test 102, and a pattern generator 1 that generates a test pattern 101 to be applied to the IC under test 6;
The timing signal 113 that fully controls the timing of the test pattern 101 applied to the test pattern 1 and the expected value pattern 1
A timing signal generator 2 generates a timing signal 114 that instructs the timing for comparing 02 and the output signal 104 of the IC under test, and the test pattern 101 is shaped into a test signal 103 to be applied to the IC under test 6 according to the timing signal 113. a comparator 4 that compares the expected value pattern 102 with the output signal 104 of the IC under test 6;
(7) Consists of a fail memory 5 that stores the ratio M results.

Further, the timing signal generator 2 has a basic clock 1.
An oscillator 2100 that oscillates 16 and a device clock 1
05) a late generator 2200 that performs timing correction using the basic clock 116; a phase clock generator 2300 that receives the basic clock 116 and the test synchronization signal 107 as input and outputs a clock signal synchronized with the test 107; , and a phase generator 2400 which receives the clock signal 110 and outputs the timing signal 114.

When the IC 6 under test has a built-in oscillator, the test apparatus configured in this way supplies the device clock 105 of the IC 6 under test to the rate generator 2200 of the timing signal generator 2, and supplies the device clock 105 to the oscillator 21000. The timing is reset using the clock 116, and the phase clock generator 2300 creates a phase clock 110 that is synchronized with the test synchronization signal 107, which is the device clock that has not been synchronized.The phase clock 110 is supplied to the phase generator 2400 to generate the timing signals 113 and 114. This is what you get.

Therefore, in this test apparatus, by setting the basic clock 116 oscillated by the oscillator 2100 to a high frequency, it is possible to reduce the synchronization error with the device clock 105 of the IC 6 under test. However, the basic clock 11
The frequency of No. 6 is limited by the operating speed of the external clock type IC test counter of the rate generator 2200, so the conventional device cannot operate at a high frequency and therefore cannot eliminate the synchronization error. was inviting.

The reason why the frequency of the basic clock 116 is limited by the operating speed of the lateno energizer 2200 will be explained using FIG. 2. Figure 2 shows the late generator 2200
It is a diagram showing the internal configuration of this generator 2200.
is a waveform shaping circuit 2 that shapes the device clock 105.
201 , a counter 2202 that counts by inputting the basic clock 116 , a selector 2203 that selects either the output of the counter 2202 or the output of the waveform shaping circuit 2201 according to the instruction of the signal 117 , and a D flip-flop 2204 and the D clip frog 22
A variable delay circuit 2205 that delays the output of 04 and a timing selection signal 106 are held for a certain period of time. latch 220
6, a delay control circuit 2208 that controls the entire amount of delay time based on the timing information of the memory 2207, and a latch 2209 that holds the output of the circuit 22o8 for a certain period of time. In this rate generator 2200, when testing an IC with a built-in oscillator, the selector 2203 selects the device clock 105 and the signal 200 whose waveform has been shaped by the full waveform shaping circuit 2201 according to the control signal 117, and
At 204, synchronization is performed with the basic clock 116.

When performing this synchronization, the time difference between the device clock 105 and the basic clock 1]6 becomes a synchronization error. This synchronization error can be reduced by increasing the frequency of the basic clock 116;
1. The upper limit of the basic clock 116 is limited by the operating speed of the counter 2202 operated during one test. Ru.

Therefore, it was not possible to perform highly accurate timing tests.

On the other hand, when testing an external clock type IC, the generator 2200 controls the selector 220 by the control signal 117.
3 selects all the outputs of the counter 2202 and inputs them to the D flip-flop 2204, and synchronizes them all with the basic clock 116. A method for creating the test periodic signal 107 using the rate generator 2204 will be described below. Rate generator 2200, test period signal 1
Timing selection signal 106 all latches 220 by 07
Hold by 6. Retained timing selection signal 1
12, the late memory 2207 is accessed, the timing information omitted in the late memory 2207 is loaded into the read counter 2202, and the counter 220
2 counts the basic clock 116 according to the loaded value and inputs it to the D free lag flop 2204 via the selector 2203', and synchronization is performed by the basic clock 116 not via the counter 2202'. However, if this continues, the resolution of the test cycle is determined by the operating speed of the counter 2202, and high precision timing tests cannot be performed.
205 to improve the input of the test period signal 107. A delay control circuit 2208 controls a variable delay circuit 2205 for improving the resolution of the test period. However, it is difficult to control this variable delay circuit 2205 with high accuracy in real time, so it has not been possible to perform a highly accurate timing test.

As is clear from the above, when testing an IC with a built-in oscillator, compared to testing an external clock type IC,
It has the disadvantage of lower timing accuracy, and also has the disadvantage of not being able to perform high-precision timing tests because there is no variable delay circuit that can control the amount of delay with high precision in real time when testing external clock type ICi. there were.

[Purpose of the invention]

It is an object of the present invention to eliminate the drawbacks of the prior art and to provide a complete timing generator capable of performing high precision timing testing of ICs with built-in oscillators and ICs using external clocks.

[Summary of the invention]

In order to achieve the above object, a timing signal generator according to the present invention is characterized by having means for converting a basic clock signal oscillated from an oscillator into a high-frequency basic clock signal.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to all the drawings.

FIG. 3 is a block diagram showing the timing generator according to this embodiment, and FIG. 4 is a diagram showing the configuration of the rate generator in FIG. 3.

The timing generator shown in FIG.
an oscillator 2100 that generates the basic clock 116, the timing selection signal 106, and the control signal 117, and a rate generator 2200 that generates the test period signal 107'i as inputs for the basic clock 116, the timing selection signal 106, and the control signal 117; signal 107
a fave clock generator 2300 that outputs a clock signal 110 k synchronized with the clock signal 110;
It is composed of a phase generator 114 which outputs a timing signal 114 as all inputs.

This timing generator outputs the test synchronization signal 107 and the timing signal 1]4 depending on whether the IC under test has a built-in oscillator or not. A rate generator 22 that instructs the output of these signals.
00'f: This will be explained using FIG. 4. When testing an IC with a built-in oscillator, this late generator 2200
The device clock 105 is synchronized with the basic clock 116, converted into a test cycle signal 107, and external clock type I
For C, test period signal 1 is specified by timing selection signal 106 from turn generator 2100.
Create 07.

The rate generator 2200 that operates in this manner includes a waveform shaping circuit 2250 that shapes the waveform of the device clock J-05, a frequency divider 2251 that performs all divisions of the basic clock 16, and a frequency divider 2251 that counts the output of the frequency divider 2251. a variable delay circuit 2253; a selector 2254 that selects either the output of the waveform shaping circuit 2250 or the variable delay circuit 2253; A D free lag flop 2255 that outputs the test synchronization signal 107 and a latch 22 that latches the V timing selection signal 106 using the test synchronization signal 107.
56, and a late memory 2257 that is accessed from when the latch 2256 is latched and outputs timing information to the counter 2252 and the delay control circuit 2258.
and a delay control circuit 2258 that completely controls the delay of the variable delay circuit 2253 based on the timing information of the rate memory 2257.

When testing an IC with all built-in oscillation circuits, the selector 2254 selects all the outputs of the waveform shaping circuit 2250 from the control signal 117K and outputs the device clock 105 to the 7 lip-flop 2255 using the rate generator 2200.
, the flip-frog 2255 synchronizes the device clock 105 with the basic clock 116,
A test cycle signal 107 is created to cause the test equipment to fully operate.

On the other hand, when testing an external clock type ICi, the rate generator 2200 controls the selector 2 by the control signal 117.
254 selects the output of the variable delay circuit 2253, and the test synchronization signal 107 which is the output of the flip-flop 2255
The timing selection signal 106 generated by the 9-turn generator is latched by the latch 2256, and the late memory 2
257 'eAccess and read timing information,
The value is output to the total counter 2252 and the delay control circuit 2258. The counter 2252 outputs the clock frequency divided by N by the basic clock 116 full frequency divider 2251 to the late memory 2252.
257, and outputs a count-up signal to the variable delay circuit 2253.

Since the propagation delay time of the variable delay circuit 2253 is controlled by the delay control circuit 2258, the input signal is output to the selector 2254 with a delay of a total designated amount. selector 225
4 selects the output of the variable delay circuit 2253 as described above, so the output signal of the variable delay circuit 2253 is retimed by the D free lag flop 2255 and the V basic clock 116 to become the test period signal 107.

As is clear from the above, since the basic clock 116 used for resetting the timing of the device clock 105 is divided by N by the full frequency divider 2251 and supplied to the counter, the frequency N is limited by the operating speed of the counter.
The frequency of the basic clock can be doubled, and the time error that occurs when synchronizing the device clock 105' with the basic clock can be reduced to VN.

Also, when testing all external clock type ICs, the variable delay circuit 2
If the delay accuracy of the variable delay circuit 2253 is within one cycle of the basic clock 116, the output signal of the variable delay circuit 2253 is sent to the D free lag flop 2255 to re-timing with the basic clock 116, thereby achieving high precision.

Next, referring to FIG. 5, we will explain the phase clock generator 230 (l) that creates a clock obtained by dividing the basic clock 116 by N in synchronization with the test periodic signal 107. This generator 2300 is configured so that the test periodic signal 107 is connected to the reset terminal. Input D flip-flop 23o2
Then, the Q terminal output of the flip-flop 23o2 is added to a flip-flop 23o4 whose timing is completely determined by the basic clock 116. Seven like this! The generated generator 2300 receives the test cycle signal 107, and when it reaches the S H level, the output of the Nordart 23o1 becomes the L level, and the signal is input to the S terminal of the D flip-flop 23o2. The set input is “L”
Since the reset input input to the R terminal becomes the "H" level, the output of the Q terminal becomes the "H" level, and the output of the Q terminal becomes "L // Hull". After that, when the test period signal 107 becomes "L" level, the Q terminal output of the flip-flop 2302 is "L//hull", so the flip-flop 23o2 changes the "H" level to the S terminal via the node gate 2301'e. It is input and set, and the output voltage is "L" level 7', C, !l), "H"
Error, 7, which is the # mutual terminal enable force installed from the "level to 1L" level, becomes an edge signal synchronized with the basic clock 116 by the flip-flop 7" 2304. It becomes a negative edge at the Q terminal output of the flip-flop 23o4. This edge is delayed by delay gate 2306 and inverted by inverter 23051/C to become a positive edge.Since this edge is connected to the clock bin (CLK terminal) of flip-flop 2302, flip-flop 23o2 The output from the Q terminal becomes "L" level and is delayed by the delay element 2303, the /7 dart 2301 is fully activated, and the flip-flop 2302't is set. The output from this pin is the clock
]? It goes to the "H" level at the digital esso, and after the propagation delay time from the set input to the delay element 2303, the Nordart 2301, and the free lag flop 23020 to the four-terminal output has passed, it goes to the 9L" level. The negative edge of the terminal output is re-timed by the basic clock 116 by the flip-flop 2304 and output.

That is, the basic clock 11 synchronized with the test periodic signal
The clock 110 whose frequency is divided by N of 6 is the flip-flop 23.
It is obtained from the Q terminal output of 04.

The frequency division number N is determined by the following formula (1) where the period of the basic clock is T and the propagation delay time of each element is determined as follows.
).

(N −1) T(Ts + TCQI +Td1 +
Tr +Tcq2+Td2+TN+TSQ +Tw(N
T Tap River + (1) However, Ts: Set-up time of the clock from the D terminal input of the flip-flop 23o4, TcQl: Propagation delay time from the clock input of the flip-flop 23o4 to the terminal Q output, 'rd1: Delay element 23o6 propagation delay time T1: inverter 23o5 propagation delay time TCQ2: propagation delay time from the clock input of flip-flop 23o2 to terminal Q output, Td2: propagation delay time of delay element 2303, TN: noader) 2301 propagation delay time, TSQ: propagation delay time from the free lag flop 23020 set input to terminal output, Tw: propagation delay time due to wiring.

Therefore, the propagation delay time T'at IT due to the delay element
By changing dZ, N can be arbitrarily selected, and a clock 110 obtained by dividing the basic clock by N in synchronization with the test period signal can be obtained.

Next, the configuration and operation of the phase generator 2400 will be explained using FIG. 6. Generator 2400 shown in the figure
a counter 2401 that counts the N-divided clock 110 synchronized with the test cycle; a variable delay circuit 2402 that delays the count-up signal of the counter 2401;
a D-flip 70g 2403 that resets the timing using the output basic clock 116 of the variable delay circuit 2402;
Phase memo that is accessed by timing selection signal 112 and outputs timing information to counter 2401 and latch 2405! 2404, and a latch 2405 that holds setting data of the variable delay circuit.

The generator 2400 configured in this manner first selects the phase memory 2404 using the timing selection signal 112.
is accessed and the timing information is read, then
Timing information is loaded into the counter 24o1 by the test period signal 107, and held in the latch 2405K to set the variable delay circuit 2402 in accordance with the timing information. The counter 24o1 counts all of the N frequency divided clocks 110 synchronized with the test period signal 107, counts the value of the loaded timing information, and outputs a count up signal to the fully variable delay circuit 2402. The variable delay circuit 24o2 delays the input signal with a basic clock signal resolution of 1100, and outputs the delayed signal to the D-fluruff zero float 24o3. The D flip-flop 2403 re-times the delayed count-up signal using the basic clock signal 116 and outputs the timing signal 114. Therefore, the timing signal is created with an accuracy N times that of the clock signal 110 supplied to the counter 2401. be able to.

Although this embodiment has been described using a single phase generator 2400'e, normally a plurality of phase generators are used to configure a timing generator for testing an IC. The invention is not limited by the number of phase generators used.

〔Effect of the invention〕

As described above, according to the present invention, by increasing the frequency of the basic clock of the timing signal generator for testing external clock type ICs, it is possible to perform timing tests on external clock type ICs with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a general IC test device,
FIG. 2 is a block diagram of a rate generator according to the prior art. 3 is a functional block diagram of a timing signal generator according to an embodiment of the present invention, FIG. 4 is a diagram showing the rate generator of FIG. 3, and FIG. 5 is a diagram showing the phase clock generator of FIG. 3. FIG. 6 is a diagram showing the phase generator of FIG. 3. 1... Pattern generator, 2... Timing generator,
3... Waveform filter, 4... Konno or rake, 5...
...Fail memory, 6...IC under test, 2200
...Rate generator, 2300... Phase clock generator, 2400... Phase generator, 2252... Frequency divider, 2253... Variable delay circuit, 2254... Selector, 2254... D flip-flop , 2257...Late memory, 2258
...Delay control circuit. Representative Patent Attorney Tadashi Akimoto Figure 1 Figure 2

Claims (1)

[Claims] A timing signal generator that outputs a basic clock signal oscillated from an oscillator as a timing signal synchronized with a test periodic signal, characterized by comprising means for converting the basic clock signal of the oscillator into a high-frequency basic clock signal. timing signal generator.