CN202256511U - Adjustable jitter measurement circuit based on self-reference signals - Google Patents
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Abstract
The utility model discloses an adjustable jitter measurement circuit based on self-reference signals. The output end of a single-cycle sampling module is respectively in electrical connection with the input end of a first alternative data selector MUX1 and the input end of a second alternative data selector MUX2. The output end of the first alternative data selector MUX1 is in electrical connection with the input end of a first oscillation circuit. The second alternative data selector MUX2 is in electrical connection with the input end of a second oscillation circuit. The output end of the first oscillation circuit and the output end of the second oscillation circuit are respectively in electrical connection with the input end of a phase discriminator. The output end of the phase discriminator is in electrical connection with a reset signal generating module. A counter is in electrical connection with the second oscillation circuit. The adjustable jitter measurement circuit based on self-reference signals overcomes the defects of poor accuracy, difficulty in adjusting, limited measurement range, low resolution ratio, slow measurement speed and the like in the prior art, and achieves the advantages of high accuracy, convenience in adjusting, wide measurement range, high resolution ratio and high measurement speed.
Description
Technical Field
The utility model relates to an electronic circuit field specifically relates to but, calibration shake measuring circuit based on from reference signal.
Background
With the continuous progress of microelectronic technology, the performance of integrated circuits is continuously improved, the development of high-speed communication systems is faster and faster, and the requirement of high-speed communication system chips on clock frequency is higher and higher. Phase Locked Loops (PLLs) are one of the clock generators commonly used at present, clock jitter is an important parameter of the PLL, the clock jitter of the high-speed communication system must be within a range specified by a design specification, otherwise, a series of problems such as system performance degradation are caused, and the jitter measurement method is more important.
Currently, as shown in fig. 1(a) and 1(b), the vernier delay chain jitter measurement method is one of the most commonly used jitter measurement techniques. The resolution of the method depends on the difference between the delay times of two different delay units, which is much smaller than the delay of a single gate, as shown in fig. 1(a), the circuit is composed of two delay chains containing different delay units, wherein the delay unit of one delay chain is τsThe other delay unit is taurWhen the clock signal passes through the first stage delay unit of the vernier delay chain, a slight timing difference (tau) is generateds-τr). Assuming that the reference clock (ref _ clk) is ideal, the data clock (data _ clk) to be measured contains jitter, and it can be seen from fig. 1(b) that the rising edge of ref _ clk leads the rising edge time T of data _ clk, the difference between their rising edges reduces to T- Δ τ after the first stage delay unit, and the rising edge of ref _ clk starts lagging data _ clk after the N stages, and the jitter value can be calculated by the following formula (assuming that Δ τ = (τ) is ideals-τr）：
The method can realize real-time measurement. During measurement, the output of the delay stage with the changed phase precedence relationship between signals ref _ clk and data _ clk and the output of the D flip-flop after the delay stage are both changed to 1, the output of the D flip-flop before the delay stage is still kept to be 0, the value of the output end of the D flip-flop is recorded by a counter, and then a Cumulative Density Function (CDF) and a Probability Density Function (PDF) can be derived and analyzed, so that the jitter value and the state distribution thereof are obtained. However, due to the existence of process deviation, the delay time of each delay unit in fig. 1(a) cannot be controlled to be equal, thereby affecting the accuracy of measurement; the circuit comprises a plurality of groups of delay units, so that calibration is not easy to realize; when measuring signal jitter, an ideal signal is required to be input as a reference clock; and a large number of counters and phase detectors are used, so that the circuit area is large.
In addition, jitter measurement requires that the test cost of a circuit is saved while the measurement time is effectively reduced, and the periodic jitter of the output signal of the phase-locked loop can be directly measured at high frequency. Therefore, there is a need for an on-chip circuit for measuring clock jitter, which uses a self-reference signal and can measure jitter over a wide frequency range, while also meeting the practical requirements of high speed and high resolution.
In summary, in the process of implementing the present invention, the inventor finds that there are at least the following defects in the prior art:
the measurement accuracy is poor: due to the existence of process deviation, the delay time of each delay unit in fig. 1(a) cannot be controlled to be equal, thereby affecting the accuracy of measurement;
secondly, the calibration is difficult: the circuit comprises a plurality of groups of delay units, so that calibration is not easy to realize;
the measurement range is limited: when measuring signal jitter, an ideal signal is required to be input as a reference clock, so that the measuring range is influenced;
fourthly, the resolution ratio is low, and the measuring speed is slow: a large number of counters and phase detectors are used in the circuit, the circuit area is large, and the resolution and the measuring speed are influenced.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to the above-mentioned problem, provide based on from reference signal's correctable shake measuring circuit to realize that the measurement accuracy is good, the calibration is convenient, measuring range is wide, resolution ratio is high and the fast advantage of measuring speed.
In order to achieve the above object, the utility model adopts the following technical scheme:
a self-reference signal based calibrated jitter measurement circuit comprises a single-period sampling module, a first alternative data selector MUX1, a second alternative data selector MUX2, a first oscillation circuit, a second oscillation circuit, a phase discriminator, a reset signal generation module and a counter, the output of the single-period sampling module is electrically coupled to the inputs of the first and second alternative data selectors MUX1 and 2, the output of the first alternative data selector MUX1 is electrically connected to the input of the first tank, the second alternative data selector MUX2 is electrically connected to the input of the second tank, the output ends of the first oscillating circuit and the second oscillating circuit are electrically connected with the input end of the phase discriminator, the output end of the phase discriminator is electrically connected to the reset signal generation module, and the counter is electrically connected to the second oscillation circuit.
Further, the single-period sampling module is composed of three cascaded flip-flops DFF1, DFF2 and DFF 3.
Further, the Reset signal generation module is composed of a Reset signal Reset _ Cal generation submodule, a Reset signal Resetn generation submodule, and a third alternative data selector MUX 3.
Further, the Reset signal Reset _ Cal generation submodule includes a first flip-flop DFF1 Reset by a low level, a second flip-flop DFF2 Reset by a low level, a logical not gate, and a logical and gate, and the Reset signal Reset generation submodule includes a first register FF1 Reset by a high level, a second register FF2 Reset by a high level, a not gate, an and gate, and two or gates.
Further, the single-period sampling module samples the Clock signal Clock to be detected to generate an En signal, an S signal and an Sd signal, the time sequences of which lag behind one period in sequence; the S signal is input to a '0' input terminal of the MUX1, the Sd signal is input to a '0' input terminal of the MUX2, and the En signal is input to a '1' input terminal of the MUX1 and the MUX2, respectively; an externally input standard mode control signal Cal is used as a selection signal of the MUX1 and the MUX2, the circuit is set to be in a measurement mode when the Cal is at a low level, and the circuit is set to be in a calibration mode when the Cal is at a high level;
the first oscillation loop is triggered by an output signal of the alternative data selector MUX1, and the output signal is S'; a second oscillation loop triggered by the output signal of the one-out-of-two data selector MUX2, wherein the output signal is Sd'; the first oscillating loop and the second oscillating loop can adjust the corresponding oscillation period by the delay selection signal; the S 'signal and the Sd' signal are input into a phase discriminator, the phase discriminator judges the phase relationship between the S 'signal and the Sd' signal, and an output signal Out _ Dir acts on a reset signal generation module;
the counter is used for recording the oscillation times of the second oscillation loop;
the Reset signal generation module provides a Reset signal Resetn under a functional mode for the single-period sampling module and provides a Reset signal resetCounter under a calibration mode for the Counter according to a Clock signal Clock to be tested, an externally input Reset signal in _ Reset, an effective signal Out _ Dir output by the phase discriminator and an externally input standard mode control signal Cal.
Further, in the self-reference signal based calibratable jitter measuring circuit described above, the calibratable property is that in the case where the signal Cal is set to a high level to enter the calibration mode, the output signal En of the one-cycle sampling circuit simultaneously triggers the oscillation loops 1 and 2, and both oscillation loops start to oscillate simultaneously. Since the oscillation period of tank 1 is longer by Δ τ than the oscillation period of tank 2, the falling edges of the output signals of the two tanks coincide again after a long period T has elapsed. At this time, the design counter records the oscillation frequency of the oscillation circuit 2 as N, and the corresponding oscillation frequency of the circuit 1 is N-1. The oscillation period of the oscillator circuit 1 is T1The oscillation period of the loop 2 is T2The relationship between the oscillation periods of the two loops can be expressed by the following formula:
Δ τ in the above equation is the actual oscillation period difference between the two oscillation loops, thereby determining the resolution of the jitter measuring circuit.
Further, in the self-reference signal based calibratable jitter measuring circuit described above, the single-period sampling module is composed of three flip-flops DFF1, DFF2 and DFF3 in cascade, wherein:
the three flip-flops are triggered by the same external Clock signal Clock, the R input end of the DFF1 is connected with an externally input Reset signal in _ Reset, the D input end of the DFF1 is connected with a high level VDD, and the Q output end of the DFF2 is connected with the D input end of the DFF 2; the Q output end of the DFF2 is connected with the D input end of the DFF3, and the R input ends of the DFF2 and the DFF3 are both connected with a reset signal Resetn. The Q output of DFF1, signal En, whose rising edge occurs on the first rising edge of the Clock signal, the Q output of DFF2, signal S, whose rising edge occurs on the second rising edge of the Clock signal, and the Q output of DFF2, signal SdThe rising edge of which occurs at the third rising edge of the Clock signal.
The En signal is used for simultaneously triggering the first oscillating loop and the second oscillating loop in the calibration mode; the S signal and the Sd signal are used to trigger the first oscillation loop and the second oscillation loop respectively in the measurement mode.
Further, the Reset signal generating module described above is composed of a Reset signal Reset _ Cal generating submodule, a Reset signal Resetn generating submodule, and a third one-out-of-one data selector MUX3, where:
the Reset signal Reset _ Cal generation submodule is used for outputting a Reset signal Reset _ Cal according to an effective signal Out _ Dir output by the phase discriminator and an externally input Reset signal in _ Reset;
the Reset signal Resetn generation submodule is used for outputting a Reset signal Resetn according to a Clock signal Clock to be tested, an externally input Reset signal in _ Reset and an effective signal Out _ Dir output by the phase discriminator;
the Reset signal Reset _ Cal is input to the "1" input of the third alternative data selector MUX 3; a reset signal Resetn input to a "0" input of the third one-of-choice data selector MUX 3; an externally input standard mode control signal Cal as a selection signal of the third alternative data selector MUX 3; the third alternative data selector MUX3 outputs a Reset signal Reset _ Counter.
Further, in the Reset signal generation module described above, the Reset signal Reset _ Cal generation submodule includes a first flip-flop DFF1 Reset by a low level, a second flip-flop DFF2 Reset by a low level, a logical not gate, and a logical and gate, wherein:
an externally input Reset signal in _ Reset is respectively used as Reset signals of the first register DFF1 and the second register DFF2, namely, is respectively input into the R input ends of the first register DFF1 and the second register DFF 2; the valid signal Out _ Dir output by the phase detector is used as the clock signals of the first register DFF1 and the second register DFF2 respectively;
the D input end of the first register DFF1 is connected with a high level VDD, and the Q output end is connected with the D input end of the second register DFF 2; the Q output of the second register DFF2 outputs a signal in _ Reset 3;
the signal in _ Reset3 passes through the not gate, and then passes through the and gate with the Reset signal in _ Reset inputted from the outside, and outputs the Reset _ Cal signal.
Further, in the reset signal generation module described above, the reset signal Resetn generation submodule includes a first register FF1 reset by a high level, a second register FF2 reset by a high level, a not gate, an and gate, and two or gates, wherein:
after passing through the logical not gate, an externally input Reset signal in _ Reset is respectively used as Reset signals of the first register FF1 and the second register FF2 after passing through a logical or gate together with an effective signal Out _ Dir output by the phase detector, namely, the externally input Reset signal in _ Reset is respectively input into the R input ends of the first register FF1 and the second register FF 2; the Clock signal Clock to be tested is respectively used as Clock trigger signals of the first register FF1 and the second register FF 2;
the D input end of the first register FF1 is connected with a high level VDD, and the Q output end of the first register FF1 is connected with the D input end of the second register FF 2; the Q output of the second register FF2 outputs a signal in _ Reset 2;
the signal in _ Reset2 and the valid signal Out _ Dir output by the phase detector pass through the logic or gate, and then pass through the logic and gate with the Reset signal in _ Reset input from the outside to obtain the Reset signal Resetn.
The utility model provides a but based on from reference signal's calibration jitter measuring circuit, owing to include single cycle sampling module, first alternative data selector MUX1, second alternative data selector MUX2, first oscillation circuit, second oscillation circuit, phase discriminator, reset signal generation module and counter, can provide the calibration scheme (namely: through the calibration, confirm the resolution ratio of this but based on from reference signal's calibration jitter measuring circuit); different measurement resolutions can be selected according to the frequencies of different signals to be measured, and the method has the advantages of wide measurement range, high resolution and high speed; using the self-reference signal, the measurement error is correspondingly reduced; therefore, the defects of poor measurement accuracy, difficult calibration, limited measurement range, low resolution and low measurement speed in the prior art can be overcome, and the advantages of good measurement accuracy, convenient calibration, wide measurement range, high resolution and high measurement speed are realized.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and examples.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1(a) is a schematic diagram of the operation principle of a vernier delay chain jitter measurement circuit in the prior art;
FIG. 1(b) is a timing diagram of a vernier delay chain jitter measurement circuit in the prior art;
FIG. 2 is a schematic diagram of the operation principle of the self-reference signal based adjustable jitter measurement circuit of the present invention;
fig. 3 is a schematic view of the working principle of the single-period sampling module provided by the present invention;
FIG. 4 is a circuit diagram of a prior art controllable digitally controlled oscillator;
fig. 5 is a schematic diagram of the working principle of a phase detector in the prior art;
fig. 6 is a schematic view of the working principle of the reset signal generating module according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are presented herein only to illustrate and explain the present invention, and not to limit the present invention.
According to embodiments of the present invention, as shown in fig. 2-6, a calibratable jitter measurement circuit based on a self-reference signal is provided.
As shown in fig. 2, the present embodiment includes a single-period sampling module, a first alternative data selector MUX1, a second alternative data selector MUX2, a first oscillation circuit, a second oscillation circuit, a phase detector, a reset signal generation module, and a counter.
Wherein: the single-period sampling module is used for sampling the Clock signal Clock to be detected and generating an En signal, an S signal and an Sd signal of which the time sequence lags behind one period in sequence; the S signal is input to a '0' input terminal of the MUX1, the Sd signal is input to a '0' input terminal of the MUX2, and the En signal is input to a '1' input terminal of the MUX1 and the MUX2, respectively; an externally input standard mode control signal Cal is used as a selection signal of the MUX1 and the MUX2, the circuit is set to be in a measurement mode when the Cal is at a low level, and the circuit is set to be in a calibration mode when the Cal is at a high level; the first oscillating loop is triggered by an output signal of the alternative data selector MUX1, and the output signal is S'; a second oscillation loop triggered by the output signal of the one-out-of-two data selector MUX2, wherein the output signal is Sd'; the first oscillating loop and the second oscillating loop can adjust the corresponding oscillation period by the delay selection signal; the S 'signal and the Sd' signal are input into a phase discriminator, the phase discriminator judges the phase relationship between the S 'signal and the Sd' signal, and an output signal Out _ Dir acts on a reset signal generation module; the counter is used for recording the oscillation times of the second oscillation loop; and the Reset signal generation module is used for providing a Reset signal Resetn under a functional mode for the single-period sampling module and providing a Reset signal resetCounter under a calibration mode for the Counter according to the Clock signal Clock to be tested, the Reset signal in _ Reset input from the outside, the effective signal Out _ Dir output from the phase discriminator and the standard mode control signal Cal input from the outside.
Its calibratability is that the signal Cal is set highWhen the level enters a calibration mode, an output signal En of the single-period sampling circuit triggers the oscillating circuits 1 and 2 at the same time, and the two oscillating circuits start to oscillate at the same time. Since the oscillation period of tank 1 is longer by Δ τ than the oscillation period of tank 2, the falling edges of the output signals of the two tanks coincide again after a long period T has elapsed. At this time, the design counter records the oscillation frequency of the oscillation circuit 2 as N, and the corresponding oscillation frequency of the circuit 1 is N-1. Let T be the oscillation period of the oscillation circuit 11The oscillation period of the loop 2 is T2The relationship between the oscillation periods of the two loops can be expressed by the following formula:
Δ τ in the above equation is the actual oscillation period difference between the two oscillation loops, thereby determining the resolution of the jitter measuring circuit.
Wherein: the single-period sampling module consists of three cascaded triggers DFF1, DFF2 and DFF3, the three triggers are triggered by the same external Clock signal Clock, the R input end of the DFF1 is connected with an externally input Reset signal in _ Reset, the D input end is connected with a high-level VDD, and the Q output end is connected with the D input end of the DFF 2; the Q output end of the DFF2 is connected with the D input end of the DFF3, and the R input ends of the DFF2 and the DFF3 are both connected with a reset signal Resetn. The Q output of DFF1, signal En, whose rising edge occurs on the first rising edge of the Clock signal, the Q output of DFF2, signal S, whose rising edge occurs on the second rising edge of the Clock signal, and the Q output of DFF2, signal SdIts upper part risesThe edge is generated on the third rising edge of the Clock signal. An En signal for simultaneously triggering the first tank circuit and the second tank circuit in the calibration mode; the S signal and the Sd signal are used to trigger the first oscillation loop and the second oscillation loop respectively in the measurement mode.
Is composed of a Reset signal Reset _ Cal generating submodule, a Reset signal Resetn generating submodule, and a third one-out-of-data selector MUX3, wherein:
a Reset signal Reset _ Cal generation submodule, which is used for outputting a Reset signal Reset _ Cal according to an effective signal Out _ Dir output by the phase discriminator and an externally input Reset signal in _ Reset;
the Reset signal Resetn generation submodule is used for outputting a Reset signal Resetn according to a Clock signal Clock to be tested, an externally input Reset signal in _ Reset and an effective signal Out _ Dir output by the phase discriminator; a Reset signal Reset _ Cal input to the "1" input of MUX 3; a reset signal Resetn input to a "0" input of MUX 3; an externally input standard mode control signal Cal as a selection signal of the MUX 3; the MUX3 outputs a Reset signal Reset _ Counter.
The Reset signal Reset _ Cal generation submodule includes a first flip-flop DFF1 Reset by a low level, a second flip-flop DFF2 Reset by a low level, a logic not gate and a logic and gate,
wherein:
an externally input Reset signal in _ Reset is respectively used as Reset signals of the first register DFF1 and the second register DFF2, namely, is respectively input into the R input ends of the first register DFF1 and the second register DFF 2; the valid signal Out _ Dir output by the phase detector is used as the clock signals of the first register DFF1 and the second register DFF2 respectively; the D input end of the first register DFF1 is connected with a high level VDD, and the Q output end is connected with the D input end of the second register DFF 2; the Q output of the second register DFF2 outputs a signal in _ Reset 3; the signal in _ Reset3 passes through the logical not gate, and then passes through the logical and gate with the Reset signal in _ Reset inputted from the outside, and outputs the Reset _ Cal signal.
The reset signal Resetn generation submodule includes a first register FF1 reset by a high level, a second register FF2 reset by a high level, a not gate, an and gate, and two or gates,
wherein:
after passing through the logical not gate, an externally input Reset signal in _ Reset is respectively used as Reset signals of the first register FF1 and the second register FF2 after passing through a logical or gate together with an effective signal Out _ Dir output by the phase detector, namely, the externally input Reset signal in _ Reset is respectively input into the R input ends of the first register FF1 and the second register FF 2; the Clock signal Clock to be tested is respectively used as Clock trigger signals of the first register FF1 and the second register FF 2;
the D input end of the first register FF1 is connected with a high level VDD, and the Q output end is connected with the D input end of the second register FF 2; the Q output of the second register FF2 outputs a signal in _ Reset 2;
the signal in _ Reset2 and the valid signal Out _ Dir output by the phase detector pass through the logic or gate, and then pass through the logic and gate with the Reset signal in _ Reset input from the outside to obtain the Reset signal Resetn.
The single-period sampling module is configured to generate an En signal, an S signal, and a Sd signal (En leads S by one period, S leads by Sd by one period) whose time sequences sequentially lag by one period according to the Clock signal Clock to be detected; the En signal is respectively input into the 1 input ends of the MUX1 and the MUX 2; the S signal is input to the '0' input end of the MUX1, and the Sd signal is input to the '0' input end of the MUX 2; the external input standard mode control signal Cal is used as a selection signal of the MUX1 and the MUX2, when the standard mode control signal Cal is set to be a low level, the circuit enters a measurement mode, and when the standard mode control signal Cal is set to be a high level, the circuit enters a calibration mode; a first oscillation circuit for outputting a signal S' according to an output signal of the MUX 1; a second oscillation loop for outputting a signal Sd' according to an output signal of the MUX 2; delay selection signals of the first oscillation circuit and the second oscillation circuit are respectively used for adjusting oscillation periods of the first oscillation circuit and the second oscillation circuit; the phase discriminator is used for judging the precedence relationship of the phases according to the signal S 'and the signal Sd' and outputting an effective signal Out _ Dir; the Reset signal generation module is used for providing a Reset signal Resetn under a functional mode for the single-period sampling module and providing a Reset signal Reset _ Counter under a calibration mode for the Counter according to a Clock signal Clock to be detected, an externally input Reset signal in _ Reset, an effective signal Out _ Dir output by the phase discriminator and an externally input standard mode control signal Cal; and the counter is used for recording the oscillation times of the second oscillation loop.
In the above embodiment, when the difference between the oscillation periods of the first oscillation circuit and the second oscillation circuit is Δ τ (i.e. resolution) and the oscillation frequency of the second oscillation circuit recorded by the Counter when the Reset signal Reset _ Counter is valid is m, the clock period T to be measured and the jitter value J to be measured are respectively:
wherein,T ideal is the ideal period of the Clock signal Clock to be measured.
In the above embodiment, as shown in fig. 3, the single-period sampling module includes a first flip-flop DFF1, a second flip-flop DFF2 and a third flip-flop DFF 3.
In fig. 3, the Clock trigger terminals of the first flip-flop DFF1, the second flip-flop DFF2 and the third flip-flop DFF3 all receive the Clock signal Clock to be measured; the D input end of the first trigger DFF1 is connected with a high level VDD, and the R input end is connected with an externally input Reset signal in _ Reset; the R input terminals of the second flip-flop DFF2 and the third flip-flop DFF3 are both connected to the reset signal Resetn.
In fig. 3, the Q output terminal of the first flip-flop DFF1 outputs the En signal at the first rising edge of the Clock signal Clock to be tested, and is connected to the D input terminal of the second flip-flop DFF 2; the Q output end of the second trigger DFF2 outputs an S signal when the Clock signal Clock to be tested rises for the second time, and is connected with the D input end of the third trigger DFF 3; the Q output terminal of the third flip-flop DFF3 outputs the Sd signal at the third rising edge of the Clock signal Clock to be tested.
In fig. 3, the En signal is used to trigger the first tank and the second tank simultaneously in the calibration mode; the S signal and the Sd signal are used to trigger the first oscillation loop and the second oscillation loop respectively in the measurement mode.
In the above embodiments, the first and second oscillators are both digitally controlled oscillators. As shown in FIG. 4, the delay unit of the numerically controlled oscillator is composed of a buffer and a plurality of tri-state buffers connected in parallel with the buffer, the delay time of the delay unit is controlled by controlling the number of the turned-on tri-state buffers, as can be seen from the figure, the oscillator is provided with a plurality of control terminals Ci, the relation between each control terminal Ci and the oscillation period is determined through post-simulation to determine the connection relation between each control terminal Ci and the four control terminals of the oscillation loop, and therefore the oscillation frequency of the oscillator is adjusted.
In fig. 4, a nand gate is added before the delay chain formed by the buffer, and a loop is formed, the oscillation loop driving signal RUN is used as the other input of the nand gate, and when RUN =1, the loop starts oscillation; RUN =0 the loop stops oscillating.
In the above embodiment, as shown in fig. 5, in the phase detector, two signals S and Sd to be phase-detected are respectively input to two edge-triggered D flip-flops with reset terminals, each D flip-flop is formed by cross-coupling two RS latches, and the D terminals of the input terminals of the flip-flops are both connected to a high level; and performing phase comparison on the Q output signals Q1 and Q2 of the two D flip-flops, and performing phase comparison on the Q output signals Q1 and Q2, and then performing phase comparison on the Q output signals and an external Reset signal in _ Reset, or performing phase comparison on the obtained signal and a signal obtained after the obtained signal passes through a delay unit DLY to obtain a Reset signal Reset _ D of the two D flip-flops. Signals Up and Down are obtained by logically negating Q1 and Q2 with Reset _ D, respectively. Generating a new output signal Out Dir using the output signals Up and Down of the two D flip-flops, as shown in the dashed box, when Up is 1 and Down is 0, Out Dir is 1; when UP is 0 and DOWN is 1, Out Dir is 0; when UP is 0, DOWN is 0 or UP is 1, DOWN is 1, the value of Out Dir remains unchanged.
In the above embodiment, as shown in fig. 6, the Reset signal generation module includes a Reset signal Reset _ Cal generation submodule, a Reset signal Resetn generation submodule, and a third one-out-of-one data selector MUX 3; a Reset signal Reset _ Cal generation submodule, which is used for outputting a Reset signal Reset _ Cal according to an effective signal Out _ Dir output by the phase discriminator and an externally input Reset signal in _ Reset; the Reset signal Resetn generation submodule is used for outputting a Reset signal Resetn according to a Clock signal Clock to be tested, an externally input Reset signal in _ Reset and an effective signal Out _ Dir output by the phase discriminator; a Reset signal Reset _ Cal input to the "1" input of MUX 3; a reset signal Resetn input to a "0" input of MUX 3; an externally input standard mode control signal Cal as a selection signal of the MUX 3; the MUX3 outputs a Reset signal Reset _ Counter.
In fig. 6, the Reset signal Reset _ Cal generation submodule includes a first flip-flop DFF1 Reset by a low level, a second flip-flop DFF2 Reset by a low level, a logic not gate, and a logic and gate, in which: the externally input Reset signal in _ Reset is respectively used as Reset signals of the DFF1 and the DFF2, namely, the externally input Reset signal in _ Reset is respectively input into the R input ends of the DFF1 and the DFF 2; the valid signal Out _ Dir output by the phase detector is used as the clock signals of the DFF1 and the DFF2 respectively; the D input end of the DFF1 is connected with a high level VDD, and the Q output end is connected with the D input end of the DFF 2; the Q output of DFF2 outputs signal in _ Reset 3; the signal in _ Reset3 passes through the logical not gate, and then passes through the logical and gate with the Reset signal in _ Reset inputted from the outside, and outputs the Reset _ Cal signal.
In fig. 6, the reset signal Resetn generation submodule includes a first register FF1 reset by a high level, a second register FF2 reset by a high level, a not gate, an and gate, and two or gates, in which: an externally input Reset signal in _ Reset passes through a logical not gate, and then passes through a logical or gate together with an effective signal Out _ Dir output by the phase detector, and the Reset signals are respectively used as Reset signals of FF1 and FF 2; the Clock signal Clock to be tested is respectively used as Clock trigger signals of FF1 and FF 2; the D input end of the FF1 is connected with a high level VDD, and the Q output end of the FF1 is connected with the D input end of the FF 2; the Q output of FF2 outputs signal in _ Reset 2; the signal in _ Reset2 and the valid signal Out _ Dir output by the phase detector pass through a logic or gate, and then pass through a logic and gate with an externally input Reset signal in _ Reset to obtain a Reset signal Resetn.
In the above embodiment, the reset signal generating module operates as follows:
when a signal in _ Reset is in a low level, both Resetn and Reset _ Counter are kept in a low level, and the calibratable jitter measuring circuit based on the self-reference signal is in a Reset state;
secondly, when the signal in _ Reset is kept at a logic high level and the calibration mode control signal Cal is at a low level, the calibratable jitter measuring circuit based on the self-reference signal is in a measurement mode, and the signal Resetn is controlled by Out _ Dir: when Out Dir is high level, the register is in Reset state, signal in _ Reset2 keeps low level in Reset state, and the value of signal Resetn is determined by Out Dir; when the output signal Out _ Dir of the phase detector changes to low level, Resetn also jumps to low level, the output signal Reset _ Counter of the MUX3 keeps consistent with the change of Resetn, and at this time, the Counter and the one-cycle sampling module are Reset;
after Out Dir is kept valid for two clock cycles, high level VDD is transmitted to in _ Reset2, the signal changes from low level to high level, Resetn also changes from low to high, the Reset of the counter and the single-cycle sampling module is finished, and the next cycle measurement state is entered;
when the signal in _ Reset is kept at a logic high level and the calibration mode control signal Cal is at a high level, the circuit is in the calibration mode, when the rising edges of the two oscillators are coincided for the first time, the output Out _ Dir of the phase discriminator generates a rising edge, at this time, the flip-flop DFF1 propagates a high level VDD, when the rising edges of the oscillators are coincided for the second time, the high level VDD propagates to the output end of the D flip-flop DFF2, the signal Reset _ Cal becomes a low level, the output signal Reset _ Counter of the MUX3 is kept consistent with the change of the Reset _ Cal, and the Counter is Reset.
In the above embodiments, the calibratable jitter measuring circuit based on the self-reference signal, which relates to the jitter measuring circuit used on the phase-locked loop chip, is a jitter measuring circuit based on the principle of vernier oscillator, using the self-reference signal; the self-reference signal based calibratable jitter measurement circuit has the following characteristics:
the method includes the steps that self-reference signals are used, and measurement errors are correspondingly reduced;
a calibration scheme can be provided, namely: determining an actual oscillation period difference between the first oscillation circuit and the second oscillation circuit through calibration under the control of the reset signal generation module to determine the resolution of the self-reference signal based calibratable jitter measurement circuit;
the different measurement resolutions can be selected according to the frequencies of different signals to be measured, and the method is wide in measurement range, high in resolution and high in speed.
To sum up, the calibration-capable jitter measuring circuit based on the self-reference signal according to the embodiments of the present invention includes a single-period sampling module, a first alternative data selector MUX1, a second alternative data selector MUX2, a first oscillation circuit, a second oscillation circuit, a phase discriminator, a reset signal generating module, and a counter, so that a calibration scheme can be provided; different measurement resolutions can be selected according to the frequencies of different signals to be measured, and the method has the advantages of wide measurement range, high resolution and high speed; using the self-reference signal, the measurement error is correspondingly reduced; therefore, the defects of poor measurement accuracy, difficult calibration, limited measurement range, low resolution and low measurement speed in the prior art can be overcome, and the advantages of good measurement accuracy, convenience in calibration, wide measurement range, high resolution and high measurement speed are realized.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A self-reference signal based adjustable jitter measuring circuit is characterized by comprising a single-period sampling module, a first alternative data selector MUX1, a second alternative data selector MUX2, a first oscillation circuit, a second oscillation circuit, a phase discriminator, a reset signal generating module and a counter, wherein the output end of the single-period sampling module is respectively and electrically connected with the input ends of the first alternative data selector MUX1 and the second alternative data selector MUX2, the output end of the first alternative data selector MUX1 is electrically connected with the input end of the first oscillation circuit, the second alternative data selector MUX2 is electrically connected with the input end of the second oscillation circuit, the output ends of the first oscillation circuit and the second oscillation circuit are electrically connected with the input end of the phase discriminator, and the output end of the phase discriminator is electrically connected with the reset signal generating module, the counter is electrically connected to the second oscillation circuit.
2. The self-reference signal based calibratable jitter measuring circuit of claim 1 wherein the single-cycle sampling module is comprised of three cascaded flip-flops DFF1, DFF2 and DFF 3.
3. The self-reference signal based calibratable jitter measuring circuit of claim 1 wherein the Reset signal generation module is comprised of a Reset signal Reset _ Cal generation submodule, a Reset signal Reset generation submodule, and a third alternative data selector MUX 3.
4. The self-reference signal based calibratable jitter measuring circuit of claim 3, wherein the Reset signal Reset _ Cal generation submodule comprises a first flip-flop DFF1 Reset by a low level, a second flip-flop DFF2 Reset by a low level, a logical NOT gate and a logical AND gate, and the Reset signal Resetn generation submodule comprises a first register FF1 Reset by a high level, a second register FF2 Reset by a high level, a NOT gate, an AND gate and two OR gates.
5. The self-reference signal based calibratable jitter measuring circuit of claim 1, wherein the single-period sampling module samples the Clock signal Clock to be measured to generate an En signal, an S signal and an Sd signal whose timing sequence lags behind one period in turn; the S signal is input to a '0' input terminal of the MUX1, the Sd signal is input to a '0' input terminal of the MUX2, and the En signal is input to a '1' input terminal of the MUX1 and the MUX2, respectively; an externally input standard mode control signal Cal is used as a selection signal of the MUX1 and the MUX2, the circuit is set to be in a measurement mode when the Cal is at a low level, and the circuit is set to be in a calibration mode when the Cal is at a high level;
the first oscillation loop is triggered by an output signal of the alternative data selector MUX1, and the output signal is S'; a second oscillation loop triggered by the output signal of the one-out-of-two data selector MUX2, wherein the output signal is Sd'; the first oscillating loop and the second oscillating loop can adjust the corresponding oscillation period by the delay selection signal; the S 'signal and the Sd' signal are input into a phase discriminator, the phase discriminator judges the phase relationship between the S 'signal and the Sd' signal, and an output signal Out _ Dir acts on a reset signal generation module;
the counter is used for recording the oscillation times of the second oscillation loop;
the Reset signal generation module provides a Reset signal Resetn under a functional mode for the single-period sampling module and provides a Reset signal resetCounter under a calibration mode for the Counter according to a Clock signal Clock to be tested, an externally input Reset signal in _ Reset, an effective signal Out _ Dir output by the phase discriminator and an externally input standard mode control signal Cal.
6. A self-reference signal based calibratable jitter measuring circuit of claim 5 wherein calibratable is such that signal Cal is set high to enter calibration mode, the output signal En of the one-cycle sampling circuit triggers tank 1 and 2 simultaneously, both tanks starting to oscillate simultaneously; since the oscillation period of the oscillation circuit 1 is longer than the oscillation period of the circuit 2 by Δ τ, after a long period T, the falling edges of the output signals of the two oscillation circuits coincide again; at the moment, the design counter records that the oscillation frequency of the oscillation circuit 2 is N, and the corresponding oscillation frequency of the circuit 1 is N-1; let T be the oscillation period of the oscillation circuit 11The oscillation period of the loop 2 is T2The relationship between the oscillation periods of the two loops can be expressed by the following formula:
；
Δ τ in the above equation is the actual oscillation period difference between the two oscillation loops, thereby determining the resolution of the jitter measuring circuit.
7. The self-reference signal based calibratable jitter measuring circuit of claim 5 or 6 wherein the single-cycle sampling module is comprised of three cascaded flip-flops DFF1, DFF2 and DFF3, wherein:
the three flip-flops are triggered by the same external Clock signal Clock, the R input end of the DFF1 is connected with an externally input Reset signal in _ Reset, the D input end of the DFF1 is connected with a high level VDD, and the Q output end of the DFF2 is connected with the D input end of the DFF 2; the Q output end of the DFF2 is connected with the D input end of the DFF3, and the R input ends of the DFF2 and the DFF3 are both connected with a reset signal Resetn; the Q output of DFF1, signal En, whose rising edge occurs on the first rising edge of the Clock signal, the Q output of DFF2, signal S, whose rising edge occurs on the second rising edge of the Clock signal, and the Q output of DFF2, signal SdThe rising edge of which is generated at the third rising edge of the Clock signal;
the En signal is used for simultaneously triggering the first oscillating loop and the second oscillating loop in the calibration mode; the S signal and the Sd signal are used to trigger the first oscillation loop and the second oscillation loop respectively in the measurement mode.
8. The self-reference signal based calibratable jitter measuring circuit of claim 2 or 5, wherein the Reset signal generation module is comprised of a Reset signal Reset _ Cal generation submodule, a Reset signal Resetn generation submodule, and a third alternative data selector MUX3, wherein:
the Reset signal Reset _ Cal generation submodule is used for outputting a Reset signal Reset _ Cal according to an effective signal Out _ Dir output by the phase discriminator and an externally input Reset signal in _ Reset;
the Reset signal Resetn generation submodule is used for outputting a Reset signal Resetn according to a Clock signal Clock to be tested, an externally input Reset signal in _ Reset and an effective signal Out _ Dir output by the phase discriminator;
the Reset signal Reset _ Cal is input to the "1" input of MUX 3; a reset signal Resetn input to a "0" input of MUX 3; an externally input standard mode control signal Cal as a selection signal of the MUX 3; the MUX3 outputs a Reset signal Reset _ Counter.
9. The self-reference signal based calibratable jitter measuring circuit of claim 8 wherein the Reset signal Reset _ Cal generation submodule comprises a first flip-flop DFF1 Reset by low level, a second flip-flop DFF2 Reset by low level, a logical not gate and a logical and gate, wherein:
an externally input Reset signal in _ Reset is respectively used as Reset signals of the first register DFF1 and the second register DFF2, namely, is respectively input into the R input ends of the first register DFF1 and the second register DFF 2; the valid signal Out _ Dir output by the phase detector is used as the clock signals of the first register DFF1 and the second register DFF2 respectively;
the D input end of the first register DFF1 is connected with a high level VDD, and the Q output end is connected with the D input end of the second register DFF 2; the Q output of the second register DFF2 outputs a signal in _ Reset 3;
the signal in _ Reset3 passes through the not gate, and then passes through the and gate with the Reset signal in _ Reset inputted from the outside, and outputs the Reset _ Cal signal.
10. The self-reference signal based calibratable jitter measuring circuit of claim 8 wherein the reset signal Resetn generation submodule comprises a first register FF1 reset by high, a second register FF2 reset by high, a not gate, an and gate and two or gates, wherein:
after passing through the logical not gate, an externally input Reset signal in _ Reset is respectively used as Reset signals of the first register FF1 and the second register FF2 after passing through a logical or gate together with an effective signal Out _ Dir output by the phase detector, namely, the externally input Reset signal in _ Reset is respectively input into the R input ends of the first register FF1 and the second register FF 2; the Clock signal Clock to be tested is respectively used as Clock trigger signals of the first register FF1 and the second register FF 2;
the D input end of the first register FF1 is connected with a high level VDD, and the Q output end of the first register FF1 is connected with the D input end of the second register FF 2; the Q output of the second register FF2 outputs a signal in _ Reset 2;
the signal in _ Reset2 and the valid signal Out _ Dir output by the phase detector pass through the logic or gate, and then pass through the logic and gate with the Reset signal in _ Reset input from the outside to obtain the Reset signal Resetn.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102435865A (en) * | 2011-10-17 | 2012-05-02 | 无锡东集电子有限责任公司 | Adjustable jitter measurement circuit based on self-reference signal |
| CN103076554A (en) * | 2012-12-29 | 2013-05-01 | 江苏东大集成电路系统工程技术有限公司 | Phase-locked loop on-chip jitter measurement circuit |
| CN108362990A (en) * | 2016-12-28 | 2018-08-03 | 电子科技大学 | High speed signal jitter test circuit and method in piece |
| CN115268247A (en) * | 2022-08-11 | 2022-11-01 | 上海华力微电子有限公司 | Digital-analog mixed high-precision establishment holding time measuring circuit and implementation method thereof |
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2011
- 2011-10-17 CN CN2011203961055U patent/CN202256511U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102435865A (en) * | 2011-10-17 | 2012-05-02 | 无锡东集电子有限责任公司 | Adjustable jitter measurement circuit based on self-reference signal |
| CN103076554A (en) * | 2012-12-29 | 2013-05-01 | 江苏东大集成电路系统工程技术有限公司 | Phase-locked loop on-chip jitter measurement circuit |
| CN108362990A (en) * | 2016-12-28 | 2018-08-03 | 电子科技大学 | High speed signal jitter test circuit and method in piece |
| CN115268247A (en) * | 2022-08-11 | 2022-11-01 | 上海华力微电子有限公司 | Digital-analog mixed high-precision establishment holding time measuring circuit and implementation method thereof |
| CN115268247B (en) * | 2022-08-11 | 2023-11-24 | 上海华力微电子有限公司 | High-precision establishment holding time measuring circuit for digital-analog mixing and implementation method thereof |
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