CN106872772A - Dithering measuring circuit on a kind of phaselocked loop piece - Google Patents
Dithering measuring circuit on a kind of phaselocked loop piece Download PDFInfo
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- CN106872772A CN106872772A CN201510915831.6A CN201510915831A CN106872772A CN 106872772 A CN106872772 A CN 106872772A CN 201510915831 A CN201510915831 A CN 201510915831A CN 106872772 A CN106872772 A CN 106872772A
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- circuit
- measuring circuit
- phaselocked loop
- loop piece
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
Abstract
The invention discloses dithering measuring circuit on a kind of phaselocked loop piece, measuring circuit is mainly made up of monocycle sample circuit, oscillation circuit, phase discriminator, reset signal generation module.The principle that measuring circuit is based on vernier oscillator improves dithering measuring circuit on a kind of phaselocked loop piece, the measuring circuit can select different Measurement Resolutions according to different incoming frequencies, compromised between time of measuring and Measurement Resolution, certainty of measurement is ensure that while effectively reducing time of measuring, saving the testing cost of circuit.Circuit structure is simple, reduces measurement cost, improves circuit operating efficiency, and preferable reference signal is provided without outside, not only reduces dependence of the measuring circuit to outside measuring instrument, also accelerates the operating rate of measuring circuit.
Description
Technical field
The present invention relates to dithering measuring circuit on a kind of phaselocked loop piece, it is adaptable to microelectronic.
Background technology
With the continuous progress of microelectronic technique, the continuous improvement of performance of integrated circuits, the development of high-speed communication system is more and more faster, requirement of the System on Chip/SoC to clock frequency also more and more higher.Phaselocked loop (Phase Locked Loops PLL) is one of clock generator more conventional at present, it can frequency doubling clock, correction clock duty cycle and eliminate clock distribution postpone, these characteristics enable designer with cheap low frequency crystal oscillator as its piece external clock clock, frequency multiplication on piece then is carried out to low frequency signal, so as to generate the internal high frequency clock signal for needing, therefore usually using phaselocked loop as clock input circuit in communication system and microprocessor chip.
As other electronic components, phaselocked loop easily by temperature change, supply voltage be unstable and chip in other signals disturbed, make the skew in its output signal generation time, so as to produce clock jitter, clock signal jitter is excessive will to cause two serious problems.First, it will reduce signal and propagate the available clock cycle and consume the timing budget of clock signal:In addition, shake is likely to result in the decay of transmission signal, logic will be caused to propagate mistake when signal attenuation is too big.Therefore, clock jitter is an important parameter of phaselocked loop, and the size of system clock shake must be within the scope of design specification regulation, a series of problems, such as can otherwise cause systematic function to reduce, therefore jitter measurement method is also more aobvious important.
Traditional jitter measurement method is mainly pll output signal is analyzed using external testing instrument, but with the continuous improvement of working frequency of chip, common tester can not meet measurement request, and the tester of higher level can be significantly increased testing cost.Further, since signal input exports the limitation of (Input/Output) I/0 pin performances, low frequency signal can only be measured using external tester, therefore the testing time is long.Except testing cost is high, in addition to testing time the two shortcomings long, traditional method of testing also has following two problems.The output probe of tester can bring extra load to circuit under test, measured signal be distorted, so as to influence the accuracy of jitter measurement；In addition, it is necessary to increase extra dedicated pin when chip is designed be used to tester.Therefore, how reducing testing cost, reducing the testing time and improving certainty of measurement becomes the primary concern of dithering measuring circuit design, and increasing researcher starts to explore and solve these problems.The problem that test equipment causes, the program causes the ardent repercussion of numerous experts and scholars in the world.When measuring phaselocked loop shake using built-in self-test circuit, it is integrated in chip internal together with phaselocked loop to be measured, the measurement of shake is completed in piece, then measurement result is exported to external testing instrument by the I/O pins of chip, so only needing to some inexpensive test equipments just can easily analyze measured result, greatly reduce testing time and testing cost.
The content of the invention
The present invention provides dithering measuring circuit on a kind of phaselocked loop piece, and circuit structure is simple, reduces measurement cost, improve circuit operating efficiency, preferable reference signal is provided without outside, dependence of the measuring circuit to outside measuring instrument is not only reduced, the operating rate of measuring circuit is also accelerated.
The technical solution adopted in the present invention is：
Dithering measuring circuit is mainly made up of monocycle sample circuit, oscillation circuit, phase discriminator, reset signal generation module on phaselocked loop piece.The principle that measuring circuit is based on vernier oscillator improves dithering measuring circuit on a kind of phaselocked loop piece, the measuring circuit can select different Measurement Resolutions according to different incoming frequencies, compromised between time of measuring and Measurement Resolution, certainty of measurement is ensure that while effectively reducing time of measuring, saving the testing cost of circuit.
The monocycle sample circuit can two rising edges continuous to measured signal sample, the circuit is made up of three triggers.Reset signals are the external reset signals of whole circuit, and it is used for resetting DFF1, and signal Reset1 is used for the DFF2 and DFF3 that resets, and it is obtained after output logical AND by external reset signal and phase discriminator, and all triggers are all resetted by low level.Clock signals as all triggers clock signal, the data terminal of first trigger is connected to VDD, after circuit reset, as Reset signals and Reset!When signal is high, the rising edge of signal En occurs in first rising edge of Clock signals, and the rising edge of signal S occurs in second rising edge of Clock signals, and the rising edge of signal Sd will be produced in the 3rd of Clock signals the rising edge.
The controllable oscillatory loop circuit selects digital controlled oscillator, the delay cell of digital controlled oscillator is from three state buffer structure in parallel, delay cell is made up of a buffer and several three state buffers in parallel with it, the time delay of the delay cell is controlled by controlling the number of conducting three state buffer, so as to adjust the frequency of oscillation of oscillator.Simply using buffer can only constitute a time delay chain, and be unable to reach the purpose of vibration, therefore a NAND gate was added before the time delay chain being made up of buffer.
The phase discriminator modification turns into the precedence relationship of detection trailing edge phase, and this is that the rising edge got due to monocycle sample circuit will once be negated into oscillation circuit by NAND gate, is changed into trailing edge.A new output signal " Out Dir " is produced using original output signal " Up " and " Down ", when " UP=1,
During DOWN=0 ", " Out Dir=1 "；When " UP=0,
During DOWN=1 ", " Outes Dir=0 "；When " UP=0,
When DOWN=0 " or " UP=1, DOWN=1 ", the value of " Out Dir " keeps constant.
The generative circuit of the reset signal Resetn is made up of two registers resetted by high level and four gates, signal in Reset are external reset signal, Clock is external timing signal (clock signal i.e. to be measured), and Out Dir are the output signal of phase discriminator.When signal in Reset are low level, Resetn keeps low level, and circuit is in reset state.When measuring circuit is in running order, signal in Reset remain logic high, and signal in Reset are controlled by Out Dir.Work as Out
When Dir is high level, register is in reset state, and signal in Reset2 keep low level, the value of signal Resetn to be determined by Out Dir under reset state；When phase detector output signal Out Dir are changed into low level, saltus step is also low level by Resetn, and this hour counter and monocycle sample circuit will be reset.After Out Dir are kept for effective two clock cycle, high level VDD is transferred into Reset2, and the signal is changed into high level from low level, and Resetn is also uprised by low, and counter and sample circuit reset and terminate, into next period measurement state.
The beneficial effects of the invention are as follows：Circuit structure is simple, reduces measurement cost, improves circuit operating efficiency, and preferable reference signal is provided without outside, not only reduces dependence of the measuring circuit to outside measuring instrument, also accelerates the operating rate of measuring circuit.
Brief description of the drawings
The present invention is further described with reference to the accompanying drawings and examples.
Fig. 1 is monocycle sample circuit of the invention.
Fig. 2 is controllable oscillatory loop circuit of the invention.
Fig. 3 is phase detector circuit of the invention.
Fig. 4 is reset signal generation module of the invention.
Specific embodiment
The invention will be further described with reference to the accompanying drawings and examples.
Such as Fig. 1, monocycle sample circuit can two rising edges continuous to measured signal sample, the circuit is made up of three triggers.Reset signals are the external reset signals of whole circuit, and it is used for resetting DFF1, and signal Reset1 is used for the DFF2 and DFF3 that resets, and it is obtained after output logical AND by external reset signal and phase discriminator, and all triggers are all resetted by low level.Clock signals as all triggers clock signal, the data terminal of first trigger is connected to VDD, after circuit reset, as Reset signals and Reset!When signal is high, the rising edge of signal En occurs in first rising edge of Clock signals, and the rising edge of signal S occurs in second rising edge of Clock signals, and the rising edge of signal Sd will be produced in the 3rd of Clock signals the rising edge.
Such as Fig. 2, controllable oscillatory loop circuit selects digital controlled oscillator, the delay cell of digital controlled oscillator is from three state buffer structure in parallel, delay cell is made up of a buffer and several three state buffers in parallel with it, the time delay of the delay cell is controlled by controlling the number of conducting three state buffer, so as to adjust the frequency of oscillation of oscillator.Simply using buffer can only constitute a time delay chain, and be unable to reach the purpose of vibration, therefore a NAND gate was added before the time delay chain being made up of buffer.
As Fig. 3, phase discriminator modification turn into the precedence relationship of detection trailing edge phase, this is that the rising edge got due to monocycle sample circuit will once be negated into oscillation circuit by NAND gate, is changed into trailing edge.A new output signal " Out Dir " is produced using original output signal " Up " and " Down ", when " UP=1,
During DOWN=0 ", " Out Dir=1 "；When " UP=0,
During DOWN=1 ", " Outes Dir=0 "；When " UP=0,
When DOWN=0 " or " UP=1, DOWN=1 ", the value of " Out Dir " keeps constant.
Such as Fig. 4, the generative circuit of reset signal Resetn is made up of two registers resetted by high level and four gates, signal in Reset are external reset signal, and Clock is external timing signal (clock signal i.e. to be measured), and Out Dir are the output signal of phase discriminator.When signal in Reset are low level, Resetn keeps low level, and circuit is in reset state.When measuring circuit is in running order, signal in Reset remain logic high, signal in
Reset is controlled by Out Dir.When Out Dir are high level, register is in reset state, and signal in Reset2 keep low level, the value of signal Resetn to be determined by Out Dir under reset state；As phase detector output signal Out
When Dir is changed into low level, saltus step is also low level by Resetn, and this hour counter and monocycle sample circuit will be reset.After Out Dir are kept for effective two clock cycle, high level VDD is transferred into Reset2, and the signal is changed into high level from low level, and Resetn is also uprised by low, and counter and sample circuit reset and terminate, into next period measurement state.
Claims (9)
1. dithering measuring circuit on a kind of phaselocked loop piece, it is characterized in that：Described measuring circuit is mainly made up of monocycle sample circuit, oscillation circuit, phase discriminator, reset signal generation module.
2. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：The principle that the measuring circuit is based on vernier oscillator improves dithering measuring circuit on phaselocked loop piece.
3. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：Described monocycle sample circuit can two rising edges continuous to measured signal sample, the circuit is made up of three triggers.
4. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：Each sample-adding module of described manipulator is substantially similar in structure in addition to mounting position of motor difference because x is to the influence of motor installing space.
5. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：In the monocycle sample circuit, signal Reset1 is used for resetting DFF2 and DFF3, and it is obtained after output logical AND by external reset signal and phase discriminator, and all triggers are all resetted by low level.
6. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：The controllable oscillatory loop circuit selects digital controlled oscillator, and the delay cell of digital controlled oscillator is from three state buffer structure in parallel.
7. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：In the controllable oscillatory loop circuit, delay cell is made up of a buffer and several three state buffers in parallel with it, the time delay of the delay cell is controlled by controlling the number of conducting three state buffer, so as to adjust the frequency of oscillation of oscillator.
8. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：The phase discriminator modification turns into the precedence relationship of detection trailing edge phase, and a new output signal " Out Dir " is produced using original output signal " Up " and " Down ".
9. dithering measuring circuit on a kind of phaselocked loop piece according to claim 1, it is characterized in that：The generative circuit of the reset signal Resetn is made up of two registers resetted by high level and four gates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510915831.6A CN106872772A (en) | 2015-12-13 | 2015-12-13 | Dithering measuring circuit on a kind of phaselocked loop piece |
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| CN201510915831.6A CN106872772A (en) | 2015-12-13 | 2015-12-13 | Dithering measuring circuit on a kind of phaselocked loop piece |
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| CN106872772A true CN106872772A (en) | 2017-06-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109032023A (en) * | 2018-08-08 | 2018-12-18 | 上海精密计量测试研究所 | A kind of built-in self-test method of FPGA internal DC M, PLL |
| CN109379076A (en) * | 2018-10-24 | 2019-02-22 | 佛山市秀声电子科技有限公司 | A kind of low-frequency phase-locking ring that modulus combines |
-
2015
- 2015-12-13 CN CN201510915831.6A patent/CN106872772A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109032023A (en) * | 2018-08-08 | 2018-12-18 | 上海精密计量测试研究所 | A kind of built-in self-test method of FPGA internal DC M, PLL |
| CN109379076A (en) * | 2018-10-24 | 2019-02-22 | 佛山市秀声电子科技有限公司 | A kind of low-frequency phase-locking ring that modulus combines |
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Application publication date: 20170620 |