JP2561644B2 - Timing signal generator - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a functional test apparatus for IC, LSI, etc., and more particularly to IC, L
The present invention relates to a timing signal generator suitable for a test device that performs a high precision timing test such as SI.

[Background of the Invention]

The timing signal generator for IC testing is roughly divided into a late generator that determines the test period and a plurality of phase generators that generate signals at arbitrary phases with respect to the test period. To be done. First,
A conventional example will be described with reference to the drawings.

FIG. 1 shows a block diagram of an example of a conventional timing signal generator. For the sake of simplicity, the rate generator RG and phase generator PG are both one. This is to output the test period signal 102 and the phase signal 103 correspondingly when the timing selection signal 101 is input from the outside in order to change the timing in real time. The outline of the operation is as follows. Is.

In FIG. 1, when the timing selection signal 101 is input, it is the test cycle signal 102 that has been output until now.
It is taken in by the latch 7 in synchronization with. The latch 7 accesses the late memory 6 in which the test cycle information is written and the phase memory 9 in which the phase signal information is written to read the test cycle information and the phase signal information.

A late generator RG that generates the test period signal 102.
Then, the rate counter 2 that determines the test cycle from the oscillator 1 that is an integral multiple of the basic clock cycle, and the variable delay circuit 3 that delays the output of the rate counter 2 in order to improve the resolution of the test cycle beyond the cycle of the basic clock. By the, the test period signal 102 is generated.

Of these, the frequency division ratio of the rate counter 2 and the delay time of the variable delay circuit 3 are controlled by the contents of the latch 4. Since the resolution is increased by using the variable delay circuit 3, the contents of the delay time (data stored in the latch 4) set in the previous test cycle and the basic clock cycle of the current test cycle (output of the late memory 6) It is determined by the adder 5 that performs addition operation with the set value less than.

Furthermore, the phase generator 103 for generating the phase signal 103
Since the basic clock having the same phase as the test cycle signal 102 is supplied to G, the variable clock circuit 8 that delays the output of the oscillator 1 generates the phase clock 100.

On the other hand, the phase generator PG outputs a coincidence output at the time when the phase information read from the phase memory 9 and set in the latch 10 coincides with the value counted by the phase counter 11 for the phase clock 100. In order to generate and further increase the phase resolution, this coincidence output is input to the variable delay circuit 12 and the phase signal 103 is output.

Here, the time error ε of the test period signal and the phase signal
_{Since RATE} and ε _PHASE are the sum of the time error factors in the path where each signal is created from the oscillator 1 that generates the basic clock, ε _RATE = {T _RATE / T _C } _int · ε _CLOCK + ε _COUNT + ε _DELAY (1) ε _PHASE = {T _D / T _C } _int · ε _CLOCK + ε _COUNT + 2ε _DELAY (2) However, _int represents a quotient in {}.

T _RATE is the period of the test period signal, T _D is the delay time from the start point of the test period signal, T _C is the basic clock period, ε
_CLOCK is the period error of the basic clock, ε _COUNT is the error depending on the set value of the counter, and ε _DELAY is the error of the analog variable delay circuit. Of these, the basic clock cycle error is about 10 ^-8 in a normal test device, and the error depending on the set value of the counter can be suppressed to 5 ps or less in the case of ECL logic elements generally used. Therefore, the time error ε _RATE is especially
Since ε _PHASE and ε _PHASE can ignore the error of the basic clock, it can be rewritten as ε _RATE ≈ ε _DELAY (3) ε _PHASE ≈ 2 ε _DELAY (4). The time error ε _PHASE of the system that creates the phase signal includes two analog delay circuits, and the time accuracy deteriorates compared to the test period signal.

As is apparent from the above description, the test period signal 102
The accuracy of is mainly determined by the variable delay circuit 3. However, the accuracy of the phase signal 103 to be the timing signal for comparing and judging the timing of the waveform applied to the device under test and the output from the device under test is determined by the above-mentioned variable delay circuits 8 and 12.
Therefore, the timing accuracy is lower than that of the test cycle signal 102, and it is difficult to perform a highly accurate timing test.

[Object of the Invention]

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art,
It is an object of the present invention to provide a timing signal generator that improves the accuracy of a phase signal that should be a timing signal for comparing and determining the timing of a waveform applied to a device under test and the output from the device under test.

[Outline of Invention]

The timing signal generator according to the present invention counts the basic clock signals and sends out a desired test cycle signal, generates a phase-locked signal synchronized with this, and generates and sends out a desired phase signal based on this. In the timing signal generator configured as described above, means for dividing the basic clock signal to generate a phase clock signal,
And a means for performing a correction calculation regarding the set time for the phase signal.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the timing signal generator according to the present invention, and FIG. 3 is its time chart.

Here, 21 is an oscillator constituting the late generator RG, 22 is also a late counter, 23 is also a variable delay circuit, 24 is also a latch, 25 is an adder, 26 is also a late memory, 27 is also a latch, and 28 is a latch. Similarly, a synchronous oscillator, 29 is a phase memory that constitutes the phase generator PG, 30 is also a latch, 31 is a phase counter, 32 is also a variable delay circuit, 33 is an adder, 34 is also a D flip-flop, and 35 is It is also a variable delay circuit.

The timing signal generator shown in FIG. 2 receives a timing selection signal 101 as an input and a test period signal 102 and a phase-locked signal 106 which is substantially synchronized with the test period signal 102.
And a phase generator 103 for inputting the phase-clock signal 106 and the like and outputting a phase signal 103.

Example of creating test period signal 102 etc. and generator RG
And the operation of the phase generator PG is as follows, and the operation of each of the components 21 to 32 in FIG. 2 is the same as the operation normally performed in each of the corresponding components 1 to 12 in FIG. is there.

In FIG. 2 and FIG. 3, when the timing selection signal 101 is input, it is synchronized with the nth signal of the test period signal 102 that has been output so far, and the test period information (Trate) output to the (n + 2) th The address of the late memory 26 in which () is written is taken into the latch 27. The latch 27 accesses the rate memory 26 in which the test cycle information Trate is written, and the read test cycle information Trate (n + 2) is output by the latch memory 26.
2) together with the setting value of the rate counter 22 and the setting value of the test cycle set in the variable delay circuit 23 in order to generate the test cycle (Trate (n + 1)) written in the latch 24 and output N + 1th Basic clock signal at 104
The set value (T _{RD in} FIG. 3) of less than 1 cycle is added and calculated by the adder 25 and stored in the latch 24. Of the values obtained by the addition operation, an integer multiple of the basic clock signal 104 is input to the rate counter 22, and the remaining values are input to the variable delay circuit 23.

The late counter 22 counts the basic clock signal 104, which is the output of the oscillator 21, according to this input value, and outputs a coincidence signal 105 when it coincides with the set value.

This match signal is further input to the variable delay circuit 23,
A test period signal having a time resolution finer than the time of one period of the basic clock 104 is generated by delaying T _RD time. The coincidence signal 105 is also input to the synchronous oscillator 28, where the phase clock signal 106, which is synchronized with the coincidence signal 105 and is obtained by dividing the basic clock by N, is created and output to the face generator PG. In FIG. 3, the frequency division number N = 5.

The face generator PG that creates the phase signal 103 is
From the output of the latch 27 holding the timing selection signal 101, the phase melody 29 in which the timing information, that is, the delay time from the start point of the n + 2th test cycle information Trate (n + 2) is written, is accessed, and
The timing information T _D (n + 2) indicating the delay time from the start point of the + 2nd test cycle is read. When the read timing information T _D (n + 2) and the N + 1th test period signal ((Trate (n + 1)) are generated, the set value T set in the variable delay circuit 23 of the rate generator RG is generated.
_RD (n + 1) is added to the latch 33 by the adder 33.
Stored in. The stored value is the phase signal 10 generated by the phase generator PG from the rising edge of the match signal 105 obtained by counting the basic clock 104 with the late counter 22.
The delay time is up to 3.

Depending on the values stored in the latch 30, the phase counter 31 has an integer multiple of the period of the basic clock 104, the variable delay circuit 32 has an integer multiple of the period of the basic clock 104, and the variable delay circuit has a variable delay circuit 32. Since a value obtained by subtracting the parts set in the phase counter 31 and the variable delay circuit 32 is set in 35, the phase counter 31 counts the phase clock signal 106 obtained by dividing the basic clock 104 by N. The coincidence output signal is delayed by the variable delay circuit 32 having a resolution equal to the period of the basic clock signal 104, and then the basic clock signal is delayed by the D flip-flop 34.
The phase signal 103 is generated by being synchronized with 104 and further delayed by the variable delay circuit 35.

As is clear from the above description, in the timing signal generator according to the present embodiment, the precision of the phase signal can be determined by the single variable delay circuit 35, and thus the highly accurate phase signal 103 can be created.

Further, since the phase clock signal 106 obtained by frequency division in the synchronous oscillator 28 is supplied to the phase counter 31, the basic clock signal 104 of high rate is equivalently obtained without using a counter capable of high speed operation. The effect is that it can be counted.

In the present embodiment, the single phase generator PG has been described, but a plurality of phase generators are usually used to form a timing signal generator for testing an IC.
As is apparent from the above description, the present invention is not limited by the number of use of phase generators.

〔The invention's effect〕

As described above in detail, according to the present invention, it is possible to improve the accuracy of the phase signal to be the timing signal for comparing and determining the timing of the waveform applied to the device under test and the output from the device under test. Therefore, a remarkable effect can be obtained in improving the accuracy and efficiency of the timing test of IC and LSI.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a conventional timing signal generator, FIG. 2 is a block diagram of an example of a timing signal generator according to the present invention, and FIG. 3 is its time chart. 21 ... Oscillator, 22 ... Late counter, 23 ... Variable delay circuit, 24 ... Latch, 25 ... Adder, 26 ... Late memory, 27 ... Latch, 28 ... Synchronous oscillator, 29 ... Phases Memory, 30 ... Latch, 31 ... Phase counter, 32 ...
… Variable delay circuit, 33 …… Adder, 34 …… D flip-flop, 35 …… Variable delay circuit.

Claims (2)

(57) [Claims] 1. A means for generating a basic clock signal having a constant period (T), and an arbitrary multiple (p + i) of the period (T) of the basic clock signal.
(P is an integer, i is a decimal number of 0 ≦ i <1), and a period (p) that is an integer (p) times the period of the basic clock signal.
Means for generating a test cycle signal having a test cycle signal having T) or a cycle ((p + 1) T) that is an integer (p + 1) times the cycle of the basic clock signal, and a small number of the set arbitrary multiples (p + i). And a first adder means for determining whether or not a cumulative addition value of the portion (hereinafter referred to as a first addition value) exceeds 1, and the means for generating the test period signal is the first adder means. When the added value is less than 1, a test period signal having a period (pT) that is an integer (p) times the period of the basic clock signal is generated,
When the added value of is greater than or equal to 1, a period ((p + 1) T) that is an integer (p + 1) times the period of the basic clock signal.
And a means including the first adder means for generating a test period signal having the following: and an arbitrary multiple (q + j) of the period (T) of the basic clock signal (q is an integer, j is a decimal number of 0 ≦ j <1). ), And the addition value of the data of the fractional part of the first addition value and the fractional part of the arbitrary multiple (q + j) of the period (T) of the basic clock signal (hereinafter referred to as the second addition value). ) Is greater than 1, and if the second addition value is less than 1, the test cycle signal generated by the test cycle signal generation means is the cycle of the basic clock signal. Generate a phase signal delayed by an integer multiple (qT) of
When the second added value is 1 or more, the test cycle signal is an integral multiple of the cycle of the basic clock signal ((q +
1) T) a phase signal generating means including the second adder means for generating a delayed phase signal, and means for further delaying the phase signal according to the value of the minority part of the second addition value. A characteristic timing signal generator. 2. The phase signal generating means performs a phase division of the basic clock by N (N is an integer of 1 or more) in synchronism with a test period signal which is an integer (p or p + 1) times as large as the basic clock signal, and is phased. Means for generating a clock signal, means for counting the phase clock signal according to the second addition value, means for further delaying the counting result with the resolution of the basic clock period, and a signal for delaying the delayed clock and the basic clock. 2. The timing signal generator according to claim 1, further comprising a synchronizing means.