JPS58184624A - Timing generator - Google Patents

Abstract

PURPOSE:To generate a high-precision, high-stability timing signal which has resolution more than a period determined by the operation speed of a counter, by performing phase control over a clock to be supplied to the counter. CONSTITUTION:Output signals 34a, 34b, and 34c of latches contain information on a phase difference between the clock to be supplied to the counter and a clock for generating the timing signal. The output 19 of a frequency divider is supplied to the counter and when the outputs 34a, 34b, and 34c have a phase difference ''3'' or ''4'', an OR gate 46 outputs ''1'' to select a delay line 40. Therefore, a control signal 35 is ''0'' during a period determined by the delay line 40, ''1'' during a period determined by a delay line 45, and ''0'' thereafter. Consequently, an output 22 or 23 having the phase difference ''3'' or ''4'' from the output 19 is passed through an AND gate 18 to obtain a timing generation signal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing generator, and more particularly to a circuit that uses multiphase clocks to be supplied to a counter and can control timing generation with high precision in real time by controlling the phases. It is.

As shown in FIG. 1, the conventional timing generator is a basic II four-wavenumber oscillator 1. Counter 2, memory 4 for storing output cycle information. It is comprised of a coincidence circuit 3 that compares the output of the counter 2 and the contents of the memory 4, and a variable delay circuit 5. In order to obtain a resolution higher than the oscillation period of the fundamental frequency oscillator 1, the output of the coincidence circuit 3 is delayed by a variable delay circuit 5. However, due to the variation of the delay time due to the temperature and voltage dependence of the variable delay circuit 5, and the difficulty in checking the delay time, there is a drawback that the timing generator cannot be made highly accurate and highly stable.

The purpose of the present invention is to achieve high precision, high stability, and real-time @
The purpose of the present invention is to provide a circuit that generates efficient timing.

The present invention eliminates variable delay circuits that are dependent on temperature and power supply voltage and whose logic is complicated, and by controlling the phase of the clock supplied to the counter, it is possible to obtain a resolution exceeding the cycle determined by the operating speed of the counter. It is characterized by a high precision and high stability timing.

The present invention will be explained in detail below with reference to embodiments shown in the drawings. FIG. 2 is a block diagram of an embodiment of the present invention, which has the following configuration: a basic oscillator 6°, a five-phase divider 7 that divides the output 24 of the basic oscillator 6 into 115 channels, and the output of the divider 7. 19 to 25"L switching circuits 9, 10.-) Latch 8, 11. Gate control circuit 13 that sub-controls the Lv of the AND gate 18 for timing output to the output of the coincidence circuit 15 and the value of the latch 11, A memory 17 for storing period information of the counter 21, and a latch 16.55 for holding period information read from the memory 7 for one timing period.
A match circuit 15 compares the contents of the counter 12 and the latch 16, and a quinary adder 14 adds the contents of the latch 11 and the memory 7. 1. ,,i.

The divider 7 is a D flip-flop (hereinafter abbreviated as D-FF') 48, 49, 50, 51 as shown in FIG.
Q from t52, the Q output of D-FF48 is transferred to D-FF49
to 0 human power, D-FF49's Q output QD-FF50's 0
The output 24 of the basic oscillator 6 is divided by 115 to obtain a 5-phase Glock by connecting the output 24 of the basic oscillator 6 to a frequency divider of 1. Output 1 of 7? , 20, 21, 22.25.

Next, one embodiment of the present invention will be described using FIGS. 2 and 5. A timing signal 25 is generated at the time of "0" in FIG.

1 bit is set in the counter 12. At this time, latch 3S
The value of the output signal 34 is 12°% The output signal 2 of the latch 8
7 is 10#, and the value of the output signal 28 of latch 11 is “2”.
The case where the value of the output signal 29 of the latch 16 is 3'' will be explained. 19, that is, No. 519(a). On the other hand, the matching circuit 15□ monitors the value "31" of the output signal 29 of the two-touch 16 and the value "[" of the output signal 30 of the counter 12, and determines that they are equal. At time, that is, at time '10'' in FIG. , the value of the output 29 of the latch 16 holding the memory 170 cycle information -3' 191 less @2'' is counted, by sending a match signal to the gate control circuit 13, the operation of the gate control circuit 13 is controlled. It has the effect of compensating the delay time.When the output signal 28 of the latches 8 and 11 is @02, the output 1 of the divider 7
Similarly, if it is “1”, the output is 20, “2”
”, the output is 21. -3”, the output is 22. "4"
In this case, it corresponds to output 23.

On the other hand, the output signal 36 of the switching circuit 10 is changed from the value "2#" of the output signal 28 of the latch 11 to the output 21 of the frequency divider 7 (FIG. 5), and the gate control circuit 1S is The pulse of (0) in the same figure at time 17# of (1) is AN
DN-Gate 18 is controlled to pass.

The timing signal 25 is output at time "17#" in FIG. 1'' is set, the output 21 of the divider 7 is counted, and new cycle information is read out from the memory 17.
Holds the value read from. The latch 8 is
) is read out from the memory 17 at time 0'' and the ratio value held by the latch 8 according to the timing signal at time 0, and is held in the latch 11Y.

The timing signal period is given by ((value of output signal 29 of latch 16) x 5+(value of output signal 34 of latch 33)) times the period of basic excavator 6.

In this case, it becomes @17'. Therefore, by dividing the establishment period X by the number of divisions 5 in the branch unit 70 and writing it into the memory 17 separately for Tomo Commercial A and the remainder 9 B, the effect of eliminating the need for the division function inside the timing generator is achieved. There is. This information is generated at time "0" in FIG. 5(1) and read out from the memory 17 one clock period before the nine timing signals.

The operating principle of adder 14 and latch 8.11 will now be explained. The clock 27 supplied to the counter 12 is switched by a periodic signal 31 read from the memory 17 each time in response to a timing generation signal. First latch 8 output signal 2
The value of 7 is 101, that is, the counter 12 operates with the clock of tar in FIG.
2m1 If the value of the memory 170 periodic signal 31 is °4'', the counter 12 will be set to the fifth value in the next timing generation period.
Count figure (0). During that period, the adder 14 adds the value ``4'' of the periodic signal 310 of the memory 170 and the value @2'' of the output signal 28 of the latch 11 in quinary, and outputs the value ``V'' with the digit ignored in vl. In the next timing generation cycle, the output value 'bi' of the adder 14 is held in the latch 11, and the previous value '2'' v2 of the latch 11 is held, so that the signal supplied to the counter 12 is transferred to the switching circuit. 9 and a switching circuit 1 for timing generation.
0'1 to select the timing generation mode. By controlling the counter 12% timing generation clock in real time, a timing generation cycle is generated in 60 basic oscillator cycles with 175 clocks having a basic oscillator frequency of 60.

Next, the operation of the gate control circuit 13 will be explained using FIGS. 6 and 7. Output signal 54m, 5 of latch 33 in FIG.
4b and 34o store information on the phase difference between the clock that supplies the counter and the clock that generates the timing signal. Figure (Ml, (phase difference between 61 is °2'', Figure 111 (Ml, te1 is "0")
Thus, the output signal port T of the branching device 7, 20.21.
22.25 phase! ! @01 ~ 14m number is a friend. FIG.
When m, 54b, and 34c are @3" or "41," the OR gate 46 becomes 11, and the L delay in 4 makes the AND gate 42Y conductive and the AND gate 43 non-conductive.
Select 0. Matching circuit 150 Matching signal 26% Figure 7 (
1tte to fl, DF-156(1')rlffl
@1"To'l 9 Delay Line 40. Or Game) 3
8'lk: Set DF-FLg via, q is "O"
, Q is reversed to "1", and q of DF/F56 is 1
When transferring from 02 to 11#, DF'・F44 has Q of "0"
Inverted from "to" 1°, via delay line 45,
DF'-F44 is set and %ζ is inverted from "1" to "0". That is, as shown in FIG. 7, the gate control signal 35 of the gate control circuit 15 is determined by the delay line 40 for a period of ``0'', and the delay line 45 causes the gate control signal 35 to be 1 m for a T00 period, and thereafter.
0". As a result, the output of FIG. 7 (dl or (el) with a phase difference of 3 or 4 from FIG.
Or ku- is obtained. 34m, 34b.

When the value of 34o is "0", "bi, '2", the delay line 39 is selected, and the gate control signal 55 has a waveform as shown in the figure (F) determined by the delay line 39. 28m, 28b, and 28o are selected and become either hl, (il, or jl).

By using the gate control circuit 13 according to the present invention, it is possible to select the pulse at time "17" of (at) in FIG. be.

As is clear from the above explanation, if the present invention is implemented, the timing generation signal can be generated from the output of the 5-phase 115 frequency divider without limiting the resolution of the timing generation cycle depending on the operating speed of the counter. This has the effect of obtaining a highly accurate and highly stable timing generation signal.

By using the divider 7) IN phase 1/N frequency divider in Figure 2, the timing pulse is output with an accuracy of 1/'N of the period determined by the maximum operating speed of the counter, and then the counter Highly accurate and inexpensive timing pulses can be generated without being limited by operating speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional timing generator, FIG. 2 is a block diagram showing an embodiment of a timing generator according to the invention, and FIG. 3 is a block diagram of an embodiment of a branching unit used in FIG. The block diagram shown in Fig. 4 is a time chart for explaining the branch operation in Fig. 3, Fig. 5 is the ninth time chart for explaining the operation in Fig. 2, and Fig. 6 is in Fig. 2! FIG. 7 is a block diagram showing one embodiment of a gate control circuit used in the present invention, and is the tth time chart for explaining the operation of FIG. 6: Basic oscillator. 7: Frequency divider, 8.11, 16, 55: Latch, 9, To: Switching circuit, 122 counter, 13: Gate control circuit. 14: Quintal adder, 15 double coincidence circuit, 17: Memory, 18: AND gate. ..., (sai / [21 years old 3 years old 3 years old 2 years old 4 years old 4'fS captive t illustrations (a) 11-1-1 bite 11 low 11 bite Cf) February - 1111 one! (Ribun - 111 Low - □□□□ - Lower To □ 2 ■■ Knee (== □□□□□ - 1 ``Similar - Ri 111 November 1''=''-

Claims (1)

[Claims] 1. A fundamental frequency oscillation means, a frequency division means for dividing the output of the fundamental frequency oscillation means into N-phase 1/H, and a predetermined second output of a predetermined phase of the division means at a timing. A timing generator comprising at least selection means for extracting a period. Z The selection means includes a first selection device that selects a phase corresponding to the quotient obtained by dividing the timing period by the number of phases of the frequency division device, and a phase selected by the first selection device. Select the phase with the rank corresponding to the remainder of the above division from 1!2
4. The timing generator according to claim 1, wherein the timing generator is configured such that the output of the second selection device is extracted as a timing period.