CN100547407C - The signal generating circuit of electric capacitance measurement - Google Patents
The signal generating circuit of electric capacitance measurement Download PDFInfo
- Publication number
- CN100547407C CN100547407C CNB2006101084071A CN200610108407A CN100547407C CN 100547407 C CN100547407 C CN 100547407C CN B2006101084071 A CNB2006101084071 A CN B2006101084071A CN 200610108407 A CN200610108407 A CN 200610108407A CN 100547407 C CN100547407 C CN 100547407C
- Authority
- CN
- China
- Prior art keywords
- signal
- test signal
- clock
- coupled
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005259 measurement Methods 0.000 title claims abstract description 48
- 238000012360 testing method Methods 0.000 claims abstract description 94
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 2
- 102100034501 Cyclin-dependent kinases regulatory subunit 1 Human genes 0.000 description 1
- 101000710200 Homo sapiens Cyclin-dependent kinases regulatory subunit 1 Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005352 clarification Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000003534 oscillatory effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
A kind of signal generating circuit of electric capacitance measurement, in order to produce an electric capacitance measurement signal, the electric capacitance measurement signal has first test signal and second test signal, and above-mentioned signal generating circuit comprises clock generating unit, frequency divider and arithmetic logic unit.Clock generating unit is in order to producing a clock signal, and frequency divider is coupled to clock generating unit, in order to clock signal being carried out frequency division, and the output frequency division signal.Arithmetic logic unit then is coupled to clock generating unit and frequency divider, in order to clock signal and fractional frequency signal are carried out logical operation, and exports first test signal and second test signal.
Description
Technical field
The present invention relates to a kind of signal generating circuit, particularly relate to a kind of signal generator that is used to measure electric capacity.
Background technology
When utilizing the electric capacity charging principle to carry out capacitance value measuring, need two groups of cycles identical usually, but the different signal of polarity, be used for time of control capacitance charge and discharge, its signal period is shorter, and just frequency is higher, the capacitance that institute's energy measurement arrives is littler, and measurement result also more accurately.
Yet, in traditional measuring technique, need produce instrument by signal usually, the signal generator as Agilent (Agilent) 81110A produces needed measurement signal.But it is not high that general signal produces the signal frequency that instrument can produce, when the capacitance of electric capacity than hour, promptly can't accurately measure.The high signal generator and frequency heals, its price is also higher, and during the electric capacity (as MIM electric capacity) on using the high-frequency signal measuring chip, usually need high frequency transmission line, high-frequency joint, even need the measurement probe of high frequency and measure platform etc., this has just caused inconvenience that measures and the rising that measures cost.
Summary of the invention
One of them is in that a kind of signal generating circuit is provided for a purpose of the present invention, in conjunction with oscillatory circuit and logical operation circuit, replaces instrument with circuit, produces and measures the required measurement signal of electric capacity, increases to measure convenience.
One of them is that a kind of signal generating circuit is being provided for a purpose of the present invention, can directly signal generating circuit and testing capacitance be incorporated on the same chip, uses producing the more measurement signal of high frequency, so that measure littler capacitance.And make measurement more accurate.
One of them is that a kind of electric capacitance measurement circuit is being provided for a purpose of the present invention, do not need the outer signal generator directly to produce and measure required measurement signal, and this electric capacitance measurement circuit directly can be integrated on the same chip with testing capacitance, reduce measuring cost and increasing the measurement convenience.
For realizing above-mentioned and other purpose, the present invention proposes a kind of signal generating circuit, and in order to produce an electric capacitance measurement signal, this electric capacitance measurement signal has first test signal and second test signal.Above-mentioned signal generating circuit comprises clock generating unit, frequency divider and arithmetic logic unit.Wherein, clock generating unit, in order to clocking, and frequency divider is coupled to clock generating unit, in order to clock signal is carried out frequency division, and the output frequency division signal.Arithmetic logic unit then is coupled to clock generating unit and frequency divider, in order to clock signal and fractional frequency signal are carried out logical operation, and exports the first above-mentioned test signal and second test signal.
For realizing above-mentioned and other purpose, the present invention proposes a kind of signal generating circuit, comprises clock generating unit, frequency divider and rejection gate.Clock generating unit is in order to clocking, and frequency divider is coupled to clock generating unit, in order to clock signal is carried out frequency division, and exports a fractional frequency signal.Rejection gate then is coupled to clock generating unit and frequency divider, in order to clock signal and fractional frequency signal being carried out anti-or logical operation, and exports one first test signal.
For realizing above-mentioned and other purpose, the present invention proposes a kind of signal generating circuit, comprises clock generating unit, frequency divider, phase inverter and rejection gate (NOR gate).Wherein, clock generating unit is in order to produce a clock signal.Frequency divider is coupled to clock generating unit, in order to clock signal is carried out frequency division, and the output frequency division signal.Phase inverter is coupled to frequency divider, in order to anti-phase above-mentioned fractional frequency signal, and exports anti-phase fractional frequency signal.Rejection gate is coupled to phase inverter and clock generating unit, in order to anti-phase fractional frequency signal and clock signal being carried out anti-or logical operation, and exports second test signal via the output phase inverter.
For realizing above-mentioned and other purpose, the present invention proposes a kind of electric capacitance measurement circuit, is applicable to the capacitance that measures an electric capacity, and above-mentioned electric capacitance measurement circuit comprises signal generating circuit and charge/discharge unit.Above-mentioned signal generating circuit is in order to export first test signal and second test signal.And discharge cell is coupled to signal generating circuit, according to second test signal, produces a charging current, in order to this electric capacity is charged, and the operation of electric capacity being discharged according to first test signal.Wherein, first test signal has the identical clock period with second test signal, and above-mentioned electric capacitance measurement circuit calculates the capacitance of this electric capacity according to charging current and above-mentioned clock period.
In an embodiment of the present invention, above-mentioned signal generating circuit comprises clock generating unit, frequency divider and arithmetic logic unit.Wherein, clock generating unit is in order to clocking, and frequency divider is coupled to clock generating unit, in order to clock signal is carried out frequency division, and the output frequency division signal.Arithmetic logic unit is coupled to clock generating unit and frequency divider, in order to clock signal and fractional frequency signal are carried out logical operation, and exports first test signal and second test signal.
Above-mentioned in an embodiment of the present invention arithmetic logic unit comprises rejection gate, is coupled to clock generating unit and frequency divider, in order to above-mentioned clock signal and fractional frequency signal being carried out anti-or logical operation, and exports the first above-mentioned test signal.
Above-mentioned in an embodiment of the present invention arithmetic logic unit comprises phase inverter and rejection gate.Wherein, above-mentioned phase inverter is coupled to frequency divider, in order to anti-phase above-mentioned fractional frequency signal, and exports an anti-phase fractional frequency signal.Above-mentioned rejection gate is coupled to the output terminal and the clock generating unit of phase inverter, in order to above-mentioned anti-phase fractional frequency signal and clock signal being carried out anti-or logical operation, and exports second test signal via an output phase inverter.
The present invention, produces and measures the required measurement signal of electric capacity, therefore with circuit mode because of directly, can be directly and testing capacitance be integrated on the same chip, do not need outer signal to produce instrument and just can carry out electric capacitance measurement, not only reduce the electric capacitance measurement cost, more increased the measurement convenience.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is the calcspar of electric capacitance measurement circuit according to an embodiment of the invention.
Fig. 2 is the circuit diagram according to the signal generating circuit of present embodiment.
Fig. 3 is the signal waveforms according to present embodiment.
Fig. 4 is the circuit diagram according to the clock generating unit of present embodiment
Fig. 5 is the circuit diagram according to the frequency divider of present embodiment.
Fig. 6 is the circuit diagram according to the charge/discharge unit of present embodiment.
The reference numeral explanation
DD: operating voltage
VSS: earth terminal
CKS: clock signal
DKS: fractional frequency signal
IDKS: anti-phase fractional frequency signal
TN+, TP+: positive half period
TP-, TP-: negative half-cycle
T1, T2: time
SN, SP: test signal
EN: enable signal
ICKS: inversion clock signal
P1, P2:P transistor npn npn
N1, N2:N transistor npn npn
I1: reference current
I2: charging current
110: the electric capacitance measurement circuit
120: signal produces single circuit
130: charge/discharge unit
140: electric capacity
210: clock generating unit
220: frequency divider
232,236: rejection gate
234: phase inverter
238: the output phase inverter
401～40N: rp unit
520～550: phase inverter
525～555: switch module
Embodiment
Fig. 1 is the calcspar of electric capacitance measurement circuit according to an embodiment of the invention.As shown in Figure 1, electric capacitance measurement circuit 110 comprises signal generating circuit 120 and charge/discharge unit 130.Signal generating circuit 120 output first test signal SN (hereinafter to be referred as test signal SN) and the second test signal SP (hereinafter to be referred as test signal SP) are to charge/discharge unit 130, charge/discharge unit 130 then is coupled to electric capacity 140, produce a charging current according to test signal SP, in order to electric capacity 140 is charged, and the operation of electric capacity being discharged according to test signal SN.And then utilize cycle of its electric current that discharges and recharges and test signal SN, SP, calculate the capacitance of electric capacity 140.
Next, further specify the circuit framework of the thin portion of present embodiment, Fig. 2 is the circuit diagram according to the signal generating circuit of present embodiment.Signal generating circuit 120 comprises clock generating unit 210, frequency divider 220 and arithmetic logic unit 230.Clock generating unit 210 is coupled to the input end of frequency divider 220, and exports a clock signal CKS to frequency divider 220, and via after the divide operation, frequency divider 220 produces a fractional frequency signal DKS.In the present embodiment, frequency divider 220 divided by 2, and then produces clock signal C KS frequency half fractional frequency signal DKS of clock signal CKS1 is only arranged.
230 of arithmetic logic unit are coupled to clock generating unit 210 and frequency divider 220, in order to clock signal C KS and fractional frequency signal DKS are carried out logical operation, and export test signal SN and test signal SP.Arithmetic logic unit 230 comprises rejection gate 232,236 and phase inverter 234, exports phase inverter 238.Wherein, rejection gate 232 is coupled to clock generating unit 210 and frequency divider 220, in order to clock signal C KS and fractional frequency signal DKS are carried out anti-or logical operation, and exports test signal SN.Phase inverter 234 is coupled to frequency divider 220, in order to anti-phase fractional frequency signal DKS, and exports an anti-phase fractional frequency signal IDKS.236 of rejection gates are coupled to phase inverter 234 and clock generating unit 210, in order to anti-phase fractional frequency signal IDKS and clock signal C KS are carried out anti-or logical operation, and export test signal SP via an output phase inverter 238.
Next, in conjunction with the signal waveform of oscillogram explanation present embodiment, Fig. 3 is the signal waveforms according to present embodiment.Below explanation please be simultaneously with reference to Fig. 2, the clock signal C KS that clock generating unit 210 is produced then is illustrated in figure 3 as a clock, after carrying out frequency division via frequency divider 220 (present embodiment for divided by 2), then produce fractional frequency signal DKS, its frequency only is half of clock signal C KS.
Because test signal SN is the result who carries out anti-or logical operation via rejection gate 232, therefore, only have when clock signal CKS and fractional frequency signal DKS all are in logic low potential, test signal SN just produces the signal (shown in time T 1) of logic high potential, and its oscillogram is then shown in the test signal SN of Fig. 3.Anti-phase fractional frequency signal IDKS then is fractional frequency signal DKS via anti-phase and get.Since test signal SP be via anti-phase fractional frequency signal IDKS and clock signal C KS carry out instead or logical operation after, again that it is anti-phase and produce.Therefore, only have when anti-phase fractional frequency signal IDKS and clock signal C KS are all logic low potential, test signal SP just can produce the signal (shown in time T 2) of logic low potential.
Therefore, can learn obviously that in the present embodiment, the negative half-cycle TN-of test signal SN is greater than positive half period TN+, and the positive half period TP+ of test signal SP is greater than positive half period TP-via Fig. 3.And test signal SN has the identical clock period with test signal SP.
Fig. 4 is the circuit diagram according to the clock generating unit of present embodiment, in the present embodiment, utilizes the circuit framework of a ring oscillator, clocking CKS.Certainly, the producing method of clock signal C KS of the present invention is not limited to the framework of ring oscillator, as long as the circuit that stable clock signal can be provided all can, those skilled in the art should know the circuit framework of all the other clockings by inference easily via disclosure of the present invention, does not add tired stating at this.
Mainly comprise odd number rp unit 401～40N in the clock generating unit 210.Wherein, rp unit 401 in the present embodiment can be Sheffer stroke gate (NAND gate), can be by an activation signal EN, and the vibration of controlling clock generating unit 210 is whether.When enable signal EN was logic high potential, the effect of rp unit 401 was similar to phase inverter, thereby made clock generating unit 210 starting oscillations, and clock signal CKS, when being logic low potential as if enable signal EN, then stopped clock signal CKS.
Fig. 5 is the circuit diagram according to the frequency divider of present embodiment.Frequency divider 220 comprises phase inverter 510～550 and switch module 525～555.Wherein, each switch module 525～555 all has a positive receiving end and a negative receiving end.In the present embodiment, when positive receiving end is a logic high potential, and negative receiving end is when being logic low potential, actuating switch then, on the contrary then switch module 525～555 presents closed condition.Certainly, in another embodiment of the present invention, also can be according to design requirement, be set at when positive receiving end be logic low potential, and negative receiving end is when being logic high potential, then actuating switch is anti-, then switch module 525～555 presents closed condition.
As shown in Figure 5, clock signal C KS exports an inversion clock signal ICKS via phase inverter 510, and its signal polarity is opposite with clock signal C KS.The positive receiving end of switch module 525,555 couples inversion clock signal ICKS, and its negative receiving end is coupled to clock signal C KS.The positive receiving end of switch module 535,545 is coupled to clock signal C KS, and its negative receiving end is coupled to inversion clock signal ICKS.Therefore, when clock signal CKS is logic high potential, switch module 545,535 conductings, and then cause the logic current potential of fractional frequency signal DKS to change (as becoming logic low potential, or becoming logic high potential) by logic low potential by logic high potential.
When clock signal CKS is logic low potential, then switch module 525,555 conductings, the input end of phase inverter 520 is coupled to the output terminal of phase inverter 555, therefore, the phase inverter 520 outputs logical signal identical with fractional frequency signal DKS.And when clock signal CKS was logic high potential once more, then the logic current potential of fractional frequency signal DKS changed.Therefore, the cycle of fractional frequency signal DKS is the twice of clock signal C KS, and promptly frequency is 1/2 times.
Fig. 5 only is the circuit diagram of the frequency divider of one embodiment of the invention, and the present invention also can use the frequency divider of other circuit structure not as limit, as D flip-flop (D flip flop) etc.Those skilled in the art should know circuit framework and implementation detail that all the other are suitable for by inference easily via disclosure of the present invention, does not add tired stating at this.
Via above-mentioned Fig. 2,3,4,5 explanation, offered some clarification on circuit framework and the signal waveform of test signal SN, SP in the present embodiment.Next, further specify the charge/discharge unit 130 of present embodiment, below explanation please be simultaneously with reference to Fig. 1.Fig. 6 is the circuit diagram according to the charge/discharge unit of present embodiment.Charge/discharge unit 130 comprises a P transistor npn npn P1 (hereinafter to be referred as P transistor npn npn P1), the 2nd P transistor npn npn P2 (hereinafter to be referred as P transistor npn npn P2), a N transistor npn npn N1 (hereinafter to be referred as N transistor npn npn N1), the 2nd N transistor npn npn N2 (hereinafter to be referred as N transistor npn npn N2).Wherein P transistor npn npn P1 and N transistor npn npn coupled in series are between operating voltage VDD and earth terminal VSS, and wherein the grid of P transistor npn npn P1 is coupled to test signal SP, and produce a reference current I
1, and the grid of N transistor npn npn N1 is coupled to test signal SN.
P transistor npn npn P2 and N transistor npn npn N2 coupled in series are between operating voltage VDD and earth terminal VSS.And electric capacity 140 (in the present embodiment with an electric capacity that refers to the difference formula be example as an illustration) be coupled between the shared node and earth terminal VSS of P transistor npn npn P2 and N transistor npn npn N2.Wherein, the grid of P transistor npn npn P2 is coupled to test signal SP, and according to test signal SP, produces charging current I
2And the grid of N transistor npn npn N2 is coupled to test signal SN, and according to test signal SN, to the operation that electric capacity 140 discharges, electric capacitance measurement circuit 110 is according to charging current I
2, reference current I
1With above-mentioned test signal SN, the clock period of SP, calculate the capacitance of electric capacity 140.Its computing formula is as follows:
C: capacitance
I
1: reference current
I
2: charging current
VDD: operating voltage
Fre: the frequency of test signal
Because the stored quantity of electric charge of electric capacity is directly proportional with the voltage difference at its two ends, the stored quantity of electric charge then is directly proportional with the electric current of unit interval inflow electric capacity.The electric current of unit interval inflow electric capacity then can charging current I
2With reference current I
1Poor, and represent divided by the frequency of test signal.The voltage that capacitance multiply by the electric capacity two ends then equals the stored quantity of electric charge in the electric capacity.Therefore, can try to achieve the capacitance of testing capacitance by the following formula formula.
Comprehensively above-mentioned, the present invention produces circuit because of direct modelled signal, and therefore required measurement signal when measuring electric capacity in order to produce, only directly with measurement circuit or testing capacitance is integrated on the same chip, does not increase the measurement convenience.Also can under undesired signal produces the situation of instrument, measure electric capacity, and higher measurement signal frequency can be provided, to obtain capacitance value measuring data more accurately.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (16)
1. signal generating circuit, in order to produce an electric capacitance measurement signal, this electric capacitance measurement signal has one first test signal and one second test signal, and this signal generating circuit comprises:
One clock generation unit is in order to produce a clock signal;
One frequency divider is coupled to this clock generating unit, in order to this clock signal is carried out frequency division, and exports a fractional frequency signal; And
One arithmetic logic unit is coupled to this clock generating unit and this frequency divider, in order to this clock signal and this fractional frequency signal are carried out logical operation, and exports this first test signal and this second test signal.
2. signal generating circuit as claimed in claim 1, wherein this clock generating unit comprises a ring oscillator.
3. signal generating circuit as claimed in claim 1, wherein this arithmetic logic unit comprises:
One rejection gate is coupled to this clock generating unit and this frequency divider, in order to this clock signal and this fractional frequency signal being carried out anti-or logical operation, and exports this first test signal.
4. signal generating circuit as claimed in claim 1, wherein this arithmetic logic unit comprises:
One phase inverter is coupled to this frequency divider, in order to anti-phase this fractional frequency signal, and exports an anti-phase fractional frequency signal;
One rejection gate is coupled to this phase inverter and this clock generating unit, in order to this anti-phase fractional frequency signal and this clock signal being carried out anti-or logical operation, and exports this second test signal via an output phase inverter.
5. signal generating circuit as claimed in claim 1, wherein the negative half-cycle of this first test signal is greater than the positive half period of this first test signal.
6. signal generating circuit as claimed in claim 1, wherein the positive half period of this second test signal is greater than the negative half-cycle of this second test signal.
7. signal generating circuit as claimed in claim 1, wherein this first test signal is identical with the cycle of this second test signal, and the positive half period of this first test signal is less than the negative half-cycle of this second test signal.
8. an electric capacitance measurement circuit is applicable to the capacitance that measures an electric capacity, and this electric capacitance measurement circuit comprises:
One signal generating circuit is in order to export one first test signal and one second test signal; And
One charge/discharge unit is coupled to this signal generating circuit, according to this second test signal, produces a charging current, in order to this electric capacity is charged, and according to this first test signal, and the operation that this electric capacity is discharged;
Wherein, this first test signal has the identical clock period with this second test signal, and this electric capacitance measurement circuit calculates the capacitance of this electric capacity according to this charging current and above-mentioned clock period,
Wherein this signal generating circuit comprises:
One clock generation unit is in order to produce a clock signal;
One frequency divider is coupled to this clock generating unit, in order to this clock signal is carried out frequency division, and exports a fractional frequency signal; And
One arithmetic logic unit is coupled to this clock generating unit and this frequency divider, in order to this clock signal and this fractional frequency signal are carried out logical operation, and exports this first test signal and this second test signal.
9. electric capacitance measurement circuit as claimed in claim 8, wherein this clock generating unit comprises a ring oscillator.
10. electric capacitance measurement circuit as claimed in claim 8, wherein this arithmetic logic unit comprises:
One rejection gate is coupled to this clock generating unit and this frequency divider, in order to this clock signal and this fractional frequency signal being carried out anti-or logical operation, and exports this first test signal.
11. electric capacitance measurement circuit as claimed in claim 8, wherein this arithmetic logic unit comprises:
One phase inverter is coupled to this frequency divider, in order to anti-phase this fractional frequency signal, and exports an anti-phase fractional frequency signal;
One rejection gate is coupled to this phase inverter and this clock generating unit, in order to this anti-phase fractional frequency signal and this clock signal being carried out anti-or logical operation, and exports this second test signal via an output phase inverter.
12. electric capacitance measurement circuit as claimed in claim 8, wherein the negative half-cycle of this first test signal is greater than the positive half period of this first test signal.
13. electric capacitance measurement circuit as claimed in claim 8, wherein the positive half period of this second test signal is greater than the negative half-cycle of this second test signal.
14. electric capacitance measurement circuit as claimed in claim 8, wherein this first test signal is identical with the cycle of this second test signal, and the positive half period of this first test signal is less than the negative half-cycle of this second test signal.
15. electric capacitance measurement circuit as claimed in claim 8, wherein this charge/discharge unit comprises:
One the one P transistor npn npn, and one the one N transistor npn npn coupled in series is between an operating voltage and an earth terminal;
Wherein, the grid of a P transistor npn npn is coupled to this second test signal, and produces a reference current, and the grid of a N transistor npn npn is coupled to this first test signal.
16. electric capacitance measurement circuit as claimed in claim 15, wherein this charge/discharge unit comprises:
One the 2nd P transistor npn npn, and one the 2nd N transistor npn npn coupled in series is between this operating voltage and this earth terminal, and this electric capacity is coupled between the shared node and this earth terminal of the 2nd P transistor npn npn and the 2nd N transistor npn npn;
Wherein, the grid of the 2nd P transistor npn npn is coupled to this second test signal, and according to this second test signal, produce this charging current, the grid of the 2nd N transistor npn npn is coupled to this first test signal, and the operation of this electric capacity being discharged according to this first test signal, this electric capacitance measurement circuit calculates the capacitance of this electric capacity according to this charging current, reference current and above-mentioned clock period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101084071A CN100547407C (en) | 2006-08-02 | 2006-08-02 | The signal generating circuit of electric capacitance measurement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101084071A CN100547407C (en) | 2006-08-02 | 2006-08-02 | The signal generating circuit of electric capacitance measurement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101118252A CN101118252A (en) | 2008-02-06 |
| CN100547407C true CN100547407C (en) | 2009-10-07 |
Family
ID=39054447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101084071A Expired - Fee Related CN100547407C (en) | 2006-08-02 | 2006-08-02 | The signal generating circuit of electric capacitance measurement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100547407C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103760392B (en) * | 2014-01-22 | 2016-05-25 | 西安电子科技大学 | Adjusting corrected signal for DC-DC converter produces circuit |
-
2006
- 2006-08-02 CN CNB2006101084071A patent/CN100547407C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101118252A (en) | 2008-02-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105656456B (en) | Circuit and pulse generating method occur for a kind of high-speed, high precision digit pulse | |
| CN107819456B (en) | High-precision delay generator based on FPGA carry chain | |
| CN102035472B (en) | Programmable digital frequency multiplier | |
| CN101464658B (en) | Method and apparatus for time-differential comparison of an analog signal | |
| CN111624469A (en) | Propagation delay test circuit of digital isolator | |
| CN103499743A (en) | System and circuit for high-precision measuring of resistor and capacitor | |
| CN202166844U (en) | High precision time measurement circuit | |
| CN110518896A (en) | It is a kind of that the clock generating circuit and chip of optional frequency and duty ratio are provided | |
| CN208999990U (en) | Real random number generator | |
| CN112583355B (en) | High-precision relaxation oscillator | |
| US10833654B2 (en) | Oscillator circuit with comparator delay cancelation | |
| CN100547407C (en) | The signal generating circuit of electric capacitance measurement | |
| CN103634010B (en) | A kind of High-precision large-range time-to-digital converter based on difference charging | |
| CN114201435A (en) | Clock generator, detection system and signal output method | |
| CN102361445B (en) | High-accuracy protocol pulse generator based on digital frequency synthesizer | |
| TWI302202B (en) | Signal generation circuit for measuring capacitor | |
| El-Hadbi et al. | Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35 μ m CMOS Proof-of-Concept Prototype | |
| JP3345209B2 (en) | Multiplier circuit | |
| CN103187952A (en) | High-frequency clock duty-ratio test circuit | |
| CN104569582B (en) | A kind of method and FPGA circuitry for being used to realize that frequency measures | |
| JPH0464431B2 (en) | ||
| CN203324453U (en) | CMOS coulombmeter remaining electricity quantity display circuit of mobile power supply | |
| CN201393210Y (en) | Restoring circuit and impulse generation circuit thereof | |
| CN202014257U (en) | Time sequence generating circuit for digital IC testing system | |
| KR20120101836A (en) | Apparatus for generating random number |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091007 Termination date: 20100802 |