1302202 pt.ap699 19791 twf.doc/g 九、發明說明： '【發明所屬之技術領域】 本發明是關於-種信號產生電路，且特別是關於一種 用於量測電容之信號產生器。 【先前技術】 • 利用電容充電原理進行電容值量測時，通常需要兩組 週期相同，但極性不同的信號，用來控制電容充電與放電 • ㈣間，其信號週期愈短，也就是頻率愈高，所能測量到 的電容值愈小，測量結果也愈準確。 然而，在傳統的測量技術中，通常需要藉由信號產生 儀器，如安捷倫（Agilent) 81110A的信號產生器，來產生 所需要的量測信號。但一般的信號產生儀器所能產生的信 號頻率不高，當電容的電容值較小時，即無法準確量測: 而頻率愈高的信號產生器，其價格也愈高，且在使用高頻 信號量測晶片上的電容（如MIM電容）時，通常需=高' 頻傳輸線、高頻接頭，甚或需要高頻的量測探針與量測平 台等，皆造成量測上的不便與量測成本的上升。 【發明内容】 本發明的目的其中之一是在提供一種信號產生帝 路，結合振盪電路與邏輯運算電路，以電路取代儀哭， 生里測電容所需的量測信號，增加量測方便性。 本發明的目的其中之-是在提供一贿號產生帝 路，可直接將信號產生電路與待測電容整合在同一晶^ 上，藉以產生更高頻的量測信號，以便量測更小的電容曰^ 5 1302202 pt.ap699 19791twf.doc/g 並使量測結果更準確。 本發明的目的其中之一是在提供一 路’不需外接錢產生！I即可直接產生#廷容量測電 號，並可將此電容量測電路直接與待測的量_ 片上、，降低量測成本與增加量測方便性。&於同-晶 路，用為===:本:=-種信號產生電 測試信號與第二測試信號。上述之信= 產生單元、除，以及邏輯運算單元。其中，時 兀，用U產生時脈信號，而除頻器耦接於 早 號進行除頻，並輸出除頻信號。以單 至時脈產生單元與除頻器’用以對時脈信號: 行邏輯運算，並輸出上述之第—測試信號與第二 ，達成上述與其他目的，本發明提出—種信號產生電 —田匕括時脈產生單元、除以及反_。時脈產生單 兀=產生時脈信號，而除頻器耦接於時脈產生單元，用 脈信號進行除頻，並輸出—除頻信號。反或間則耗 日守脈產生單元與除頻H，用以對時脈信號與除頻作號 進仃反或邏輯運算，並輸出一第一測試信號。 為達f上述與其他目的，本發明提出一種信號產生電 ，包括時脈產生單元、除頻器、反相器以及反或閘（N0R 。其中，時脈產生單元用以產生一時脈信號。除頻 禺接於日守脈產生單元，用以對時脈信號進行除頻，並輸 1302202 pt.ap699 19791 twf.doc/g 以于、頻㈣。反㈣、耦接至除頻器，用以反相上述之 並輸出反相除齡號。反或㈣接至反相器與時= ^早π ’用以，反相除頻信號與時脈信號進行反或 運异，並經由輸出反相器輪出第二測試信號。 輯 ，達成上述與其他目的，本發明提^種電 =於量測一電容之，值，上述之電容量測電= 以生電路與充放電早70。上述之信號產生電路，用 測試信號與第二測試信號。而放電單 =產^路，根據第二測試信號，產生—充 ^ 電之動作。其中，第一測試信號與 丁放 之時脈週期，上狀電容量測電路根具有相同 時脈週期，計算該f容之電容值。 上述之 在本發明一實施例中，上述 產生單元、除頻器以及邏輯運駿ί生電路包括時脈 ^用以產生時脈信號，除頻器耦接於;' :’日:脈產生單 對時脈信號進行除頻，並輸出除頻信^ ^早用以 接至時脈產生單元與除，用運算單元輕 仃，運异’並輸出第一測試信號 ：，虎 ^執接至時脈產生單元與除_，用^早二包括士反或 除頻信號進行反或邏輯運算 ρ Μ之Η邊信 信號。 輪出上述之第一測試 在本發明—實施例中上述之邏輯運算單元包括反相1302202 pt.ap699 19791 twf.doc/g IX. Description of the invention: '[Technical field to which the invention pertains] The present invention relates to a signal generating circuit, and more particularly to a signal generator for measuring capacitance. [Prior Art] • When measuring the capacitance value using the principle of capacitance charging, it is usually necessary to use two sets of signals with the same period but different polarities to control the charging and discharging of the capacitor. (4) The shorter the signal period, that is, the higher the frequency. High, the smaller the capacitance value that can be measured, the more accurate the measurement results. However, in conventional measurement techniques, it is often necessary to generate a desired measurement signal by means of a signal generating instrument, such as the Agilent 81110A signal generator. However, the frequency of the signal generated by the general signal generating instrument is not high. When the capacitance value of the capacitor is small, the accurate measurement cannot be performed: The higher the frequency, the higher the price of the signal generator, and the higher frequency is used. When measuring the capacitance on the chip (such as MIM capacitor), it usually needs to be = high frequency transmission line, high frequency connector, or even high frequency measurement probe and measurement platform, etc., which cause inconvenience and quantity in measurement. Measuring the rise in costs. SUMMARY OF THE INVENTION One of the objects of the present invention is to provide a signal generating circuit, combined with an oscillating circuit and a logic operation circuit, replacing the instrument with a circuit, and measuring the signal required for measuring the capacitance, thereby increasing the convenience of measurement. . The purpose of the present invention is to provide a bribe to generate a road, and directly integrate the signal generating circuit and the capacitor to be tested on the same crystal, thereby generating a higher frequency measurement signal, so as to measure less. Capacitance 曰^ 5 1302202 pt.ap699 19791twf.doc/g and make the measurement results more accurate. One of the objects of the present invention is to provide a way of 'no need for external money to be generated! I can directly generate the #Ten capacity measurement number, and can directly measure the capacitance measurement circuit with the amount to be measured, reduce the measurement cost and increase the measurement convenience. & in the same - crystal circuit, used as ===: this: =- type of signal to generate electrical test signal and second test signal. The above letter = generation unit, division, and logic operation unit. Wherein, the clock signal is generated by U, and the frequency divider is coupled to the early signal to perform frequency division, and outputs the frequency division signal. The single-to-clock generation unit and the frequency divider 'for the clock signal: row logic operation, and output the above-mentioned first test signal and the second, to achieve the above and other purposes, the present invention proposes a signal to generate electricity - Tian Wei includes the clock generation unit, divide and reverse _. The clock generation unit 兀= generates a clock signal, and the frequency divider is coupled to the clock generation unit, performs frequency division by the pulse signal, and outputs a frequency-divided signal. The inverse or the circumstance consumes the day-to-day pulse generating unit and the frequency-dividing frequency H to perform a reverse or logical operation on the clock signal and the frequency-dividing signal, and outputs a first test signal. For the above and other purposes, the present invention provides a signal generating circuit including a clock generating unit, a frequency divider, an inverter, and an inverse OR gate (N0R, wherein the clock generating unit is configured to generate a clock signal. The frequency is connected to the day-defining pulse generating unit for frequency-dividing the clock signal, and input 1302202 pt.ap699 19791 twf.doc/g for the frequency (four). The inverse (four) is coupled to the frequency divider for Invert the above and output the inverse phase number. The inverse or (4) is connected to the inverter and the time = ^ early π ', the inverted frequency-divided signal is inversely or different from the clock signal, and inverted via the output. The second test signal is rotated by the device. In order to achieve the above and other purposes, the present invention provides a method for measuring the value of a capacitor, and the capacitance of the above-mentioned capacitance is measured by the circuit and charging and discharging 70. The signal generating circuit uses the test signal and the second test signal, and the discharge single = the production circuit, according to the second test signal, generates the action of charging and charging, wherein the first test signal and the clock cycle of the Ding The capacitance measuring circuit root has the same clock cycle, and the electric power of the f capacity is calculated. In one embodiment of the present invention, the generating unit, the frequency divider, and the logic circuit comprise a clock to generate a clock signal, and the frequency divider is coupled to the ':' day: pulse Generate a single pair of clock signals for frequency division, and output the frequency-removed signal ^ ^ used to connect to the clock generation unit and divide, use the operation unit to flick, transport the same 'and output the first test signal:, tiger ^ To the clock generation unit and the _, the second or the second signal including the inverse or the frequency division signal is used for the inverse or logical operation ρ Μ the edge signal. The first test is taken out in the present invention - the above logic in the embodiment Arithmetic unit includes inversion
1302202 pt.ap699 19791 twf.d〇c/g 器以及反或閘。其中，上述之反㈣ 反相上述之_錢，並輸出—反相除頻信’用以 或閘麵接至反相器之輸出端與時脈產生單/用以 之反相除頻錢與時脈信號進行反或軸運*、，、以 輸出反相器輸出第二測試信號。 #，亚經由一 本發明因直接以電路方式，產生量測 曰、 信號’因此，可直接與待測電容整合於同—:的里^ 1卜ί信號產生儀，便可進行電容量測，不僅“電容3 成本，更增加了量測方便性。 、 為讓本發明之上述和其他目的、特徵和優點能更明顯 易丨重，下文特舉本發明之較佳實施例，並配合 作詳細說明如下。 _圖式’ 【實施方式】 圖1為根據本發明一實施例之電容量測電路之方塊 圖。如圖1所示，電容量測電路110包括信號產生電路12〇 與充放電單元130。信號產生電路120輸出第一測試信號 SN (以下簡稱測試信號Sn)與第二測試信號sP (以^ 稱測試信號sp)至充放電單元no，而充放電單元13〇則 耗接於電容140，根據測試信號SP產生一充電電流，用以 對電容140進行充電，並根據測試信號sn對電容進行放 電之動作。進而利用其充放電的電流與測試信號SN、SP 的週期，計算電容140之電容值。 接下來，進一步說明本實施例細部之電路架構，圖2 為根據本實施例之信號產生電路之電路圖。信號產生電路 8 1302202 pt.ap699 19791 twf.doc/g 120包括時脈產生單元210、除頻器22〇與邏輯運算單元 230。時脈產生單元210耦接於除頻器22〇的輸入端，並輸 出一時脈信號CKS至除頻器22〇,而經由除頻動作後，除 頻态220產生一除頻信號DKS。在本實施例中，除頻器220 將時脈信號CKS除以2,進而產生頻率僅有時脈信號CKS1 一半的除頻信號DKS。 邏輯運算單元230則耦接至時脈產生單元21〇與除頻 ，220，用以對時脈信號CKS與除頻信號MS進行邏輯運 异’並輸出測试k號SN與測試信號sp。邏輯運算單元230 包括反或閘232、236以及反相！| 234、輸出反相器娜。 其中’反或閘232耦接至時脈產生單元21〇與除頻哭22〇， 用以對時脈信號CKS與除頻信號DKS進行反或邏輯°運算， 亚輸出測試信號SN。反相器234輕接至除頻器22〇，用以 反相除頻錢DKS，並輸出-反相除頻錢聰。反 236則耦接至反相器234與時脈產生單元21〇，用以對反相 除頻信號IDKS與時脈信號CKS進行反或邏輯運算 一輸出反相器238輸出測試信號SP。 ^ ω 接下來，配合波形圖說明本實施例之信號波形 為根據本實_之信號波形圖。以下說崎 2’時脈產生單元2Η)所產生的時脈信號CKS則如圖^圖 為-時脈，經由除頻器22〇進行除頻後（本:= 2半)。，則產生除頻信號DKS，其頻率僅為時脈信號 由於測試信號SN是經由反或閘咖進行反或邏輯運 1302202 ptap699 19791twf.doc/g 异之結果，因此，僅有當時脈信號CKS與除頻信號DKS皆 處於邏輯低電位時，測試信號SN才產生邏輯高電位之信號 一(如時間T1所示），其波形圖則如圖3之測試信號邠所 =°而反相除頻信號IDKS則是除頻信號DKS經由反相而 知。由於測試信號sp是經由反相除頻信號IDKS與時脈信 號CKS進行反或邏輯運算後，再將其反相而產生。因此， ，有當反相除頻信號IDKS與時脈信號CKS皆為邏輯低電位 犄，測试信號sp才會產生邏輯低電位之信號（如時間T2 所示）。 因此，經由圖3可明顯得知，在本實施例中，測試信 號SN^之負半週期ΤΝ-大於正半週期ΤΝ+，而測試信號sp 之正半週期TP+大於正半週期Tp—。且測試信號SN與測試 信號SP具有相同之時脈週期。 圖4為根據本實施例之時脈產生單元之電路圖，在本 實施例^，利用一環形振盪器之電路架構，產生時脈信號 CKf。當然，本發明之時脈信號cKS之產生方式並不限定 於％形振盈之架構，只要能提供穩定時脈信號之電路皆 可’在本技術領域具有通常知識者，經由本發明之揭露應 可輕易+推知其餘產生時脈信號之電路架構，在此不加累述。 日守脈產生單元210中主要包括奇數個反相單元401〜 401S[。甘 τφ?，1 /、τ 在本貫施例中之反相單元401可為反及閘 jNANDgate) ’可藉由一致能信號εν，來控制時脈產生 單兀^1〇的振盪與否。當致能信號EN為邏輯高電位時， 反相單兀401的功效與反相器相似，因而使時脈產生單元 10 1302202 pt.ap699 19791twf.doc/g 210開始振盪，並輸出時脈 ^ 邏輯低電位時，則停止於cks，右致能信號EN為 圖5為根據本實號⑽。 包括反相器510〜550 Wp*如之電路圖。除頻器220 一開關元件525〜555皆j關元件525〜555。其中，每 本實施例中，當it接收端—正接收端與—負接收端。在 輯低電位時，則導通c電位，而負接收端為邏 呈現關閉狀態。當缺，在之，則開關元件525〜555 設計需求，設定為1正2另—實施例中，亦可依照 為邏輯高電位時，則導通門：為邏輯低電位，而負接收端 奶呈現關閉狀態通開關，反之，則開關元件仍〜 =圖5所示’時脈信號CKs = = 其信號極性與時脈邮^ 而丄:接跄山、555的正接收端耦接反相時脈信號順， fCKs ° ^ 535' 相時脈時脈信號CKS，而其負接麵接至反 a* , 。因此’ #魏錢CKS為邏輯高電位 二=1 545'535?’進而造成除頻信號DKS的 ^短供1改交（如由邏輯1位變為邏輯低電位，或是由 邏輯低電位變為邏輯高電位）。 ，時脈錢CKS為邏輯低電位時，則開關元件525、 山V通’反相s 52〇的輸入端輕接至反相器、555之輸出 =因此’反相态520輸出與除頻信號DKS相同之邏輯信 〜而昌時脈信號CKS再次為邏輯高電位日夺，則除頻信號 1302202 pt.ap699 19791 twf.doc/g UKS的邏輯位準改變 脈信號CKS的兩倍，即頻率為1/2倍 的週期為時 圖5僅為本發明一貫施例之除頻器之電路圖，本發 並不以此為限，亦可使用其他電路結構之除頻器，如^ 正反器（D flip flop)等。在本技術領域具有通常知識 經由本發明之揭露，應可以輕易推知其餘適用之電 與貫施細節，在此不加累述。 >、 經由上述圖2、3、4、5之說明，已經明確說明本每 施例中測試信號SN、SP之電路架構與信號波形。接下來具 進刀步說明本實施例之充放電單元13〇，以下說明請 參照圖1。圖6為根據本實施例之充放電單元之電路圖。 ，放電單元130包括第一 P型電晶體卩丨（以下簡稱p二三 =體P1 )、第二P型電晶體P2(以下簡稱p型電晶體P2 )、 第N型電晶體N1 (以下簡稱n型電晶體ν〗）、第二 型電晶體N2(以下簡稱N型電晶體n2)。其中p型^曰 =第N型電晶體串聯柄接於工作電壓獅與接地:: 、， 心其中P型電晶體P1之閘極耦接於測試信號卯， 二一二參考電流11 ’而N型電晶體N1之閘極耦接至測 試化戚SN。 型電晶體P2與N型電晶體N2串聯耦接於工作電壓 η、接，，VSS之間。而電容140 (在本實施例中以一 之黾谷為例作為說明）|馬接於p型電晶體P2與n 型包曰曰體N2之共用節點與接地端vss 帝曰 zf# 1 J /、 1 土 包曰曰1之祕聽於賴信號sp，並減測試信號 12 19791twf.doc/g 1302202 pt.ap699 SP，產生充電電流12。而N型電晶體N2之閘極耦接至測 試信號SN，並根據測試信號SN，對電容140進行放電之 動作，電容量測電路110根據充電電流12、參考電流Ιι與 上述之測試信號SN、SP之時脈週期，計算電容140之電 容值。其計算公式如下： Q = (工2 _ 工1 ) VDD X Fre C :電容值 Ιι :參考電流 工2 ·充電電流 VDD :工作電壓 Fre :測試信號之頻率 由於電容所儲存的電荷量與其兩端的電壓差成正 比，而所儲存的電荷量則與單位時間流入電容的電流成正 比。而單位時間流入電容的電流則可以充電電流12與參考 電流I!的差，並除以測試信號之頻率來表示。而電容值乘 以電容兩端之電壓則等於電容内所儲存之電荷量。因此， 可藉由上式公式求得待測電容之電容值。 綜合上述，本發明因直接設計信號產生電路，用以產 生量測電容時所需之量測信號，因此，不只可直接與量測 電路或是待測電容整合於同一晶片上，增加量測方便性。 更可在不需要信號產生儀器的情況下量測電容，且可提供 更高之量測信號頻率，以取得更準確之電容值量測數據。 131302202 pt.ap699 19791 twf.d〇c/g and reverse or gate. Wherein, the above-mentioned inverse (four) inverts the above-mentioned _ money, and outputs - the inverted-phase-removed signal ' is used to connect the gate to the output of the inverter and the clock generation single/use reverse frequency-free frequency and The clock signal is reversed or axially operated*, and the second inverter is outputted by the output inverter. #,亚 via a invention, because of the direct circuit, the measurement of the 曰, signal 'Therefore, it can be directly integrated with the capacitance to be tested in the same -: ^ 卜 信号 signal generator, you can carry out capacitance measurement, The above-mentioned and other objects, features and advantages of the present invention will become more apparent and more obvious. The preferred embodiments of the present invention are described in detail below. 1 is a block diagram of a capacitance measuring circuit according to an embodiment of the present invention. As shown in FIG. 1, the capacitance measuring circuit 110 includes a signal generating circuit 12 and a charge and discharge unit. 130. The signal generating circuit 120 outputs a first test signal SN (hereinafter referred to as a test signal Sn) and a second test signal sP (to be referred to as a test signal sp) to the charge and discharge unit no, and the charge and discharge unit 13A is consumed by the capacitor 140, generating a charging current according to the test signal SP for charging the capacitor 140, and discharging the capacitor according to the test signal sn. The current of the charging and discharging and the period of the test signals SN, SP are utilized. Calculating the capacitance value of the capacitor 140. Next, the circuit structure of the detail of the embodiment is further explained, and Fig. 2 is a circuit diagram of the signal generating circuit according to the embodiment. The signal generating circuit 8 1302202 pt.ap699 19791 twf.doc/g 120 includes The clock generation unit 210, the frequency divider 22 and the logic operation unit 230. The clock generation unit 210 is coupled to the input end of the frequency divider 22A, and outputs a clock signal CKS to the frequency divider 22A, and After the frequency action, a frequency division signal DKS is generated in addition to the frequency state 220. In the present embodiment, the frequency divider 220 divides the clock signal CKS by 2, thereby generating a frequency division signal DKS having a frequency only half of the clock signal CKS1. The logic operation unit 230 is coupled to the clock generation unit 21 and the frequency division 220 for logically differentiating the clock signal CKS from the frequency division signal MS and outputting the test k number SN and the test signal sp. The operation unit 230 includes an inverse OR gate 232, 236 and an inversion!| 234, and an output inverter Na. wherein the 'reverse or gate 232 is coupled to the clock generation unit 21 and the frequency division cry 22, for the clock. The signal CKS is inverse or logically operated with the frequency-divided signal DKS The sub-output test signal SN. The inverter 234 is lightly connected to the frequency divider 22A for inverting the frequency-removing DKS, and outputting the --phase de-clocking frequency. The anti-236 is coupled to the inverter 234. The pulse generating unit 21A is configured to perform an inverse or logical operation on the inverted frequency-divided signal IDKS and the clock signal CKS. The output inverter 238 outputs the test signal SP. ^ ω Next, the signal of the embodiment is described in conjunction with the waveform diagram. The waveform is a signal waveform diagram according to the actual _. The clock signal CKS generated by the following 2' clock generation unit 2 Η) is as shown in the figure - the clock is divided by the frequency divider 22 ( ( Ben: = 2 and a half). , the frequency signal DKS is generated, and the frequency is only the clock signal. Since the test signal SN is reversed or logically transmitted by the inverse or the gate, the result is only the current pulse signal CKS and When the frequency-divided signal DKS is at a logic low level, the test signal SN generates a signal of a logic high potential (as indicated by time T1), and its waveform diagram is as shown in the test signal of FIG. The IDKS is known by the inversion of the frequency-divided signal DKS. Since the test signal sp is inversely or logically operated by the inverted frequency-divided signal IDKS and the clock signal CKS, it is inverted by inverting it. Therefore, when the inverted frequency-divided signal IDKS and the clock signal CKS are both logic low, the test signal sp will generate a logic low signal (as indicated by time T2). Therefore, it is apparent from Fig. 3 that in the present embodiment, the negative half period ΤΝ of the test signal SN^ is greater than the positive half period ΤΝ+, and the positive half period TP+ of the test signal sp is greater than the positive half period Tp_. And the test signal SN has the same clock cycle as the test signal SP. Fig. 4 is a circuit diagram of a clock generating unit according to the present embodiment. In the present embodiment, a clock signal CKf is generated using a circuit configuration of a ring oscillator. Of course, the manner in which the clock signal cKS of the present invention is generated is not limited to the structure of the %-shaped vibration. As long as the circuit capable of providing a stable clock signal can be generally known in the art, the disclosure by the present invention should be The circuit architecture of the remaining clock signals can be easily and inferred, and will not be described here. The day-of-day pulse generation unit 210 mainly includes an odd number of inverting units 401 to 401S [. Gan τφ?, 1 /, τ In the present embodiment, the inverting unit 401 can be the inverse gate jNANDgate)' can control the oscillation of the clock to generate a single 兀^1〇 by the uniform energy signal εν. When the enable signal EN is at a logic high level, the effect of the inverted single-turn 401 is similar to that of the inverter, thus causing the clock generation unit 10 1302202 pt.ap699 19791twf.doc/g 210 to start oscillating and output the clock ^ logic At low potential, it stops at cks, and the right enable signal EN is as shown in Fig. 5 according to the actual number (10). Including the inverter 510 ~ 550 Wp * as shown in the circuit diagram. Frequency divider 220 A switching element 525-555 is used to turn off elements 525-555. In each of the embodiments, when it is the receiving end - the receiving end and the - receiving end. When the low potential is programmed, the c potential is turned on, and the negative receiving terminal is turned off. When it is missing, the switching elements 525~555 are designed to be set to 1 positive 2 and another. In the embodiment, when the logic is high, the gate is turned on: the logic is low, and the negative receiving milk is presented. Turn off the state switch, otherwise, the switch component is still ~ = Figure 5 shows the clock signal CKs = = its signal polarity and clock signal ^ and 丄: the positive receiver of the 555, 555 is coupled with the inverting clock The signal is smooth, fCKs ° ^ 535' phase clock signal CKS, and its negative junction is connected to the inverse a*. Therefore, '#魏钱CKS is logic high potential two = 1 545 '535?' and thus causes the short-circuit 1 of the frequency-divided signal DKS to be changed (such as from logic 1 to logic low or from logic low) Is logic high). When the clock money CKS is logic low, the input terminal of the switching element 525, the mountain V-pass 'inverting s 52 轻 is lightly connected to the inverter, the output of 555 = thus the 'inverted state 520 output and the frequency-divided signal DKS the same logic letter ~ and the clock signal CKS is again a logic high potential, then the frequency signal 1302202 pt.ap699 19791 twf.doc / g UKS logic level change pulse signal CKS twice, that is, the frequency is 1/2 times the cycle time is shown in FIG. 5 is only a circuit diagram of the frequency divider of the consistent embodiment of the present invention, and the present invention is not limited thereto, and other circuit structure dividers such as a positive/reactor can also be used. D flip flop) and so on. GENERAL INFORMATION OF THE INVENTION In the art, the remaining applicable electrical and pertinent details should be readily inferred from the disclosure of the present invention, and are not described herein. >, through the above description of Figs. 2, 3, 4, and 5, the circuit architecture and signal waveforms of the test signals SN, SP in each of the embodiments have been clearly explained. Next, the charging/discharging unit 13A of the present embodiment will be described with reference to the steps. Referring to Fig. 1, the following description will be given. Fig. 6 is a circuit diagram of a charge and discharge unit according to the embodiment. The discharge unit 130 includes a first P-type transistor 卩丨 (hereinafter referred to as p 2-3 = body P1 ), a second P-type transistor P 2 (hereinafter referred to as a p-type transistor P 2 ), and an N-type transistor N1 (hereinafter referred to as The n-type transistor ν ′′, the second type transistor N 2 (hereinafter referred to as the N-type transistor n 2 ). Where p-type ^ 曰 = N-type transistor series shank connected to the working voltage lion and ground::,, the heart of the P-type transistor P1 gate is coupled to the test signal 卯, 221 reference current 11 ' and N The gate of the transistor N1 is coupled to the test transistor SN. The transistor P2 and the N-type transistor N2 are coupled in series between the operating voltages η, 接, and VSS. The capacitor 140 (in the present embodiment, a valley is taken as an example) | The horse is connected to the common node of the p-type transistor P2 and the n-type package body N2 and the ground terminal vss 曰zf# 1 J / 1 The secret of the earthen bag 听1 listens to the signal sp and reduces the test signal 12 19791twf.doc/g 1302202 pt.ap699 SP to generate the charging current 12. The gate of the N-type transistor N2 is coupled to the test signal SN, and discharges the capacitor 140 according to the test signal SN. The capacitance measuring circuit 110 according to the charging current 12, the reference current Ι and the test signal SN, The clock period of the SP is calculated by calculating the capacitance value of the capacitor 140. The calculation formula is as follows: Q = (Work 2 _ work 1) VDD X Fre C : Capacitance value Ιι : Reference current 2 · Charge current VDD : Operating voltage Fre : The frequency of the test signal due to the amount of charge stored by the capacitor The voltage difference is proportional, and the amount of stored charge is proportional to the current flowing into the capacitor per unit time. The current flowing into the capacitor per unit time can be expressed as the difference between the charging current 12 and the reference current I! divided by the frequency of the test signal. The capacitance value multiplied by the voltage across the capacitor is equal to the amount of charge stored in the capacitor. Therefore, the capacitance value of the capacitor to be tested can be obtained by the above formula. In summary, the present invention directly designs a signal generating circuit for generating a measuring signal required for measuring a capacitor. Therefore, not only can the measuring circuit or the capacitor to be tested be directly integrated on the same wafer, thereby increasing the measurement convenience. Sex. It also measures the capacitance without the need for a signal-generating instrument and provides a higher measurement signal frequency for more accurate capacitance measurement data. 13
1302202 pt.ap699 19791twf.doc/g 雖然本發明已以較佳實施例揭露如上，然其並非用r 限定本發明，任何熟習此技藝者，在不脫離本發明之铲ζ 和範圍内’當可作些許之更動與潤飾’因此本 = 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為根據本發明一實施例之電容量測電路之方塊 圖2為根據本實施例之信號產生電路之電路 圖3為根據本實施例之信號波形圖。 回 圖4為根據本實施例之時脈產生單元之電路 圖5為根據本實施例之除頻器之電路圖。回 圖6為根據本實施例之充放電單元 【主要元件符號說明】 圖。 DD :工作電壓 VSS ·接地端 CKS :時脈信號 DKS :除頻信號 IDKS :反相除頻信號 TN+、TP+ :正半週期 TP-、TP-:負半週期 ΤΙ、T2 :時間 SN、SP :測試信號 EN :致能信號 ICKS ·反相時脈信號 14 19791twf.doc/g 1302202 pt.ap699 Π、P2 : P型電晶體 N1、N2 : N型電晶體 11 :參考電流 12 :充電電流 110 :電容量測電路 120 :信號產生單電路 130 :充放電單元 140 :電容 210 :時脈產生單元 220 :除頻器 232、236 :或反閘 234 :反相器 238 :輸出反相器 401〜40N :反相單元 520〜550 :反相器 525〜555 :開關元件 151302202 pt.ap699 19791 twf.doc/g Although the present invention has been disclosed in the preferred embodiments as above, it is not intended to limit the invention, and any skilled person will be able to do so without departing from the scope and scope of the invention. Make a few changes and refinements' Therefore, the scope of this application is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a capacitance measuring circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a signal generating circuit according to the present embodiment. FIG. 3 is a signal waveform diagram according to the present embodiment. 4 is a circuit diagram of a clock generating unit according to the present embodiment. FIG. 5 is a circuit diagram of a frequency divider according to the present embodiment. 6 is a diagram of a charge and discharge unit according to the present embodiment. DD : Operating voltage VSS · Ground terminal CKS : Clock signal DKS : Frequency dividing signal IDKS : Reverse frequency dividing signal TN+, TP+ : Positive half cycle TP-, TP-: Negative half cycle ΤΙ, T2 : Time SN, SP: Test signal EN: Enable signal ICKS · Inverted clock signal 14 19791twf.doc/g 1302202 pt.ap699 Π, P2: P-type transistor N1, N2: N-type transistor 11: Reference current 12: Charging current 110: Capacitance measuring circuit 120: signal generating single circuit 130: charging and discharging unit 140: capacitor 210: clock generating unit 220: frequency divider 232, 236: or reverse gate 234: inverter 238: output inverter 401~40N : Inverting units 520 to 550: inverters 525 to 555: switching element 15