JP2655165B2 - Synchronization method of synchronous inverter, synchronous signal generation circuit and synchronous inverter device - Google Patents

Description

The present invention relates to a method for synchronizing a synchronous inverter, a synchronous signal generating circuit, and a synchronous inverter device.

[Conventional technology]

A synchronous inverter is driven by synchronizing an inverter frequency with an AC to be synchronized, such as a commercial power supply, and is conventionally known, for example, as disclosed in JP-A-59-28882.

According to this, the phase difference between the AC to be synchronized and a reference waveform signal (inverter driving waveform) generated in the inverter is detected by a PLL (Phase Locked Loop) circuit, and the frequency of the reference waveform signal is determined based on the phase difference. To adjust and thereby synchronize.

[Problems to be solved by the invention]

However, according to the above prior art, in order to configure a PLL circuit, a phase comparator that detects a phase difference and converts it into a voltage signal, and a voltage controlled oscillator (VCO) whose oscillation frequency changes in proportion to the output voltage ) Is required, and there is a problem that the circuit configuration becomes complicated.

Further, in the case of the power supply synchronous CVCF, the synchronization width is generally narrowed, and when the power supply frequency fluctuates beyond that, switching is performed asynchronously, so that the operation is performed at a so-called free-running frequency. In such a case, according to the above-described related art, it is necessary to set the upper limit and the lower limit of the oscillation frequency of the VCO according to the synchronization width. However, since the VCO is generally formed of a semiconductor integrated circuit, there is a problem that the oscillation frequency fluctuates under the influence of the ambient temperature, and it is difficult to set the upper and lower limit frequencies with high accuracy.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization method of a synchronous inverter, which can simplify the configuration of a synchronous circuit and increase synchronization accuracy, a synchronous signal generating circuit using the same, and a synchronous inverter device.

[Means for solving the problem]

In order to achieve the above object, a method for synchronizing a synchronous inverter according to the present invention sets a synchronous adjustment band having a variable time width for each predetermined period of a reference waveform pattern for driving an inverter element,
The purpose is to synchronize the inverter output with the AC to be synchronized by adjusting the time width of the synchronization adjustment band.

Further, the synchronization signal generating circuit according to the present invention has means for generating a unit waveform pattern corresponding to a predetermined period of the reference waveform pattern for driving the inverter element, and the unit waveform pattern responds to a given reset signal. A reference waveform pattern generating means for adding and outputting a synchronization adjustment pattern having a fixed time width to the synchronization waveform, and detecting a phase change of an AC to be synchronized and corresponding to a reference phase of the synchronization adjustment pattern output from the reference waveform pattern generation means. Synchronization detection means for outputting a synchronization signal at a timing at which the AC phase is detected, and determining whether or not the output timing of the synchronization signal is during the output of the synchronization adjustment pattern. On the other hand, when the judgment is negative, the reference waveform pattern is generated in synchronization with the output end timing of the synchronization adjustment pattern. A synchronization adjustment unit for outputting a reset signal to the means, those comprising a.

[Action]

According to the present invention having such a configuration, the above object is achieved by the following operation.

That is, according to the method of the present invention, only by adjusting the time width of the synchronization adjustment band (for example, about ± 1% of the frequency),
The output waveform of the inverter can be synchronized with the AC waveform to be synchronized. Therefore, there is no need to adjust the waveform (frequency) of the reference waveform pattern itself, so that the circuit configuration can be simplified and the synchronization accuracy can be improved.

The method of adjusting the time width can be realized, for example, by detecting the period of the AC to be synchronized and adjusting the period according to the difference from the period of the reference waveform pattern.

Further, the present invention can also be realized by detecting the phase of the AC to be synchronized corresponding to the reference phase of the synchronization adjustment band, and setting the remaining synchronization adjustment band to zero when the detection timing is included in the synchronization adjustment band.

In any of the above methods, the waveform of the reference wave pattern is slightly different from the waveform of the AC to be synchronized because it is affected by the waveform pattern of the synchronization adjustment band. However, in general, the frequency deviation related to the synchronization adjustment is ±
Since it is 1% or less, there is almost no problem.

On the other hand, according to the circuit of the present invention, first, a reference waveform pattern in which a synchronization adjustment pattern is sequentially added to a unit waveform pattern (for example, 1/2 cycle unit) in response to a reset signal from the reference waveform pattern generation means is continuous. Output. Then, according to the synchronous inverter device of the present invention, based on this, the inverter element is driven by, for example, PWM control, and an inverter output based on the reference waveform pattern is obtained. When the reset signal is input during the output of the synchronization adjustment pattern, the output is immediately switched to the next unit waveform pattern output, and the reference waveform pattern synchronized with the AC to be synchronized is output. Thus, the inverter output is synchronized with the AC to be synchronized. When the period (frequency) of the AC to be synchronized fluctuates significantly, the operation becomes asynchronous due to a free-running frequency based on a fundamental wave pattern to which a synchronization adjustment pattern having a fixed time width is added. Unit waveform pattern is not limited to 1/2 cycle, 1 cycle, it can be selected 1 _^1/2-cycle or the like. The time width of the synchronization adjustment pattern is set according to the frequency fluctuation width of the AC to be synchronized. Generally, it is about ± 1% or less.

〔Example〕

 Hereinafter, the present invention will be described based on examples.

FIG. 1 shows a block diagram of an embodiment of the apparatus to which the present invention is applied. In the figure, a reference waveform pattern generating means 5 is formed by a crystal oscillator 1, a counter 2, a counter 3, and a memory (ROM) 4.

The zero point detector 8 has a function as a synchronization detecting means. The zero point detector 8 detects a zero point of the input AC to be synchronized, that is, a timing at which the AC changes from positive to negative or from negative to positive, and outputs the synchronization signals b ₀ and b ₁ , respectively. Is output.

The synchronization adjusting means 9 comprises an inverter 10, AND gates 11, 12, 1
4, formed from an OR gate 13. The output signal a ₇ the synchronization signal b ₀ of the counter 3 is input to the AND gate 11. The output signal a ₇ the synchronization signal b ₁ of the counter 3 which is inverted is input by the inverter 10 to the AND gate 12. The output of these AND gates 11 and 12 is OR gate 13
Is input to the AND gate 14. The other input terminal of the AND gate 14 receives from the counter 2 a signal A indicating that the output state of the reference waveform pattern is in the synchronous adjustment band.
Is entered. This signal A will be described later in detail.

A synchronization signal generation circuit is formed by the reference waveform pattern generation means 5, the zero point detector 8, and the synchronization adjustment means 9. Then, the reference waveform pattern signal to be output from this is converted into an analog waveform signal by the D / A converter 6 and then supplied to the PWM inverter 7. PWM inverter 7
Has a well-known configuration, and drives an inverter element by PWM control based on a reference waveform pattern.

Next, the operation of the reference waveform pattern generating means 5 which is a main part will be described.

The crystal oscillator 1 always generates a stable constant frequency pulse as a clock pulse. Counter 2 is used, for example, 128-ary counter for counting the clock pulses, counter 3 is binary counter for the most significant bit signal a ₆ counter 2 and the clock, the output bit signal a ₀ ~a ₇ of these counters To count clock pulses from 0 to 255.

Data relating to the reference waveform pattern shown in FIG. 2 is stored in the ROM 4 in advance. As shown in the figure, the reference waveform pattern 15 is set to a pattern in which a half cycle of a sine waveform is used as a unit waveform pattern, and a synchronization adjustment band (pattern) 16 having a fixed time width (n clocks) is added thereto. ing. Then, set the phase of each positive and negative 1/2 cycle to 1
Divide into 28 and set addresses 0 to 127 and 128 to 255,
Positive half-wave waveform data is stored corresponding to 0 to (127-n), and the synchronization adjustment pattern 16 of "0" is stored for (127-n) to 127.
Is stored, and the negative half-wave waveform data is stored corresponding to the following 128 to (255-n), and "0" is stored for (255-n) to 255 similarly to the positive. Has become.

As shown in FIG. 2, the signal A is a signal which becomes “H” level in synchronization with the synchronization adjustment pattern 16 of the reference waveform pattern 15. That is, the content of the counter 2 is (127−
"H" when it is between n) to 127 and between (255-n) to 255
Becomes

The counter 3 is because a binary counter, the most significant bit signal a ₆ of counter 2 content of the output whenever a change twice alternately changes to "H" or "L". Therefore, each time the counter 2 is reset, it changes to “H” or “L”, and as a result, it becomes a signal indicating a positive or negative half cycle. Here, the counter 2 is reset by the AND gate 14.
Are automatically reset when the reset signal B based on the synchronization signal is output from the CPU 2 and when the counter 2 reaches the full count. This latter reset can be regarded as a reset signal that is output in synchronization with the timing at which the period adjustment pattern 16 ends, and constitutes a part of the synchronization adjustment means 9.

The zero point detector 8 is configured as shown in FIG. The comparator 20 outputs an output signal v _c of the synchronization when the target AC v ₁ is positive "H", when negative "L". By the circuit consisting of the inverter 21, the resistor 22, the capacitor 23 and the AND gate 24, v _c
Falling, that is, a zero point that changes from positive to negative,
Outputs a pulse-shaped synchronizing signal b _0. Similarly, inverter 25
And by a resistor 26 and a capacitor 27 and an AND gate 24 circuit detects the rising edge of v _c, namely it detects a positive change zeros from negative to output a pulse-shaped synchronizing signal b _1. FIG. 4 shows a time chart of these signal waveforms.

Here, the operation relating to the synchronization adjustment will be described with reference to FIG. If the reset signal B is not input to the counter 2,
The output of the D / A converter 6 has a waveform as shown by the broken line in the figure because the data in the ROM 4 is output as it is. On the other hand, the pulse signal b ₀ when the synchronization target AC v ₁ changes from positive to negative is
When the signal A is input at "H", the counter 2 time t ₁
Reset with. This makes the contents of counters 2 and 3
t Start counting from ₁ to 128. That is the negative half-wave from the t ₁ is started. Similarly, at time t _2, the counter 2 is reset by b ₁ again. In this way, the waveform of the sinusoidal synchronized with the synchronized alternating v ₁ is obtained.

Here, if those that fluctuation width is small of about 1% as the center frequencies there is synchronized AC v _1, the time width of the synchronization adjustment pattern may in about ± 1% of the total, for example, the synchronization adjustment pattern center phase Is set to a range of ± 1% based on. As a result, in a state synchronized with the AC to be synchronized, the period expands and contracts within the range of the synchronization adjustment band of about ± 1%. In addition, since the adjustment width is small with respect to the whole, the output waveform of the inverter is substantially a sine wave.

On the other hand, if v input ₁ is not, or, if the synchronized alternating current with a frequency which deviates from the synchronization adjustment pattern 16 is input,
Counter 2 is not reset. Therefore, in FIG.
The waveform indicated by the broken line of the D / A output is the PWM reference waveform pattern.

As described above, according to the present embodiment, first, the waveform data in the ROM 4 is read out by the clock signal based on the crystal oscillator 1 having a stable oscillation frequency and high accuracy to generate the reference waveform pattern. Therefore, the accuracy of the frequency is extremely high.

Also, since the synchronization is adjusted by expanding and contracting the synchronization adjustment band set every 1/2 cycle of the reference waveform pattern, the synchronization accuracy of the frequency and the accuracy of the synchronization range are high, and the circuit configuration is extremely high. Easy.

In addition, even during asynchronous operation, a high-accuracy free-running frequency can be obtained for the same reason as described above.

In the above embodiment, the case where the synchronization adjustment band is provided for each unit cycle pattern of 1/2 cycle is shown, but once in one cycle as shown in FIG. 6A or as shown in FIG. Once every 1.5 cycles, and even once every more cycles.

In the above embodiment, the waveform of the synchronization adjustment pattern 16 is set to "0". However, the ending portion of the sine wave as shown in FIG. 7A or the ending portion as shown in FIG. The waveform may be an approximate waveform that is arbitrarily deformed, or a waveform of an arbitrary portion of a sine wave as shown in FIG.

In addition, the present invention can be applied to arbitrary waveforms such as a triangular wave output as shown in FIG. 8A and a square wave output as shown in FIG.

Further, in the above embodiment, an example was shown in which the waveform pattern data for one cycle was stored in the ROM 4, but only the data corresponding to the positive half cycle was stored, and based on the output of the counter 3, It is also possible to invert the data in the ROM 4 and use it.

〔The invention's effect〕

As described above, according to the method of the present invention, since the synchronization is performed by adjusting the time width of the synchronization adjustment band, it is not necessary to adjust the waveform of the reference waveform pattern itself. No need for an oscillator (VCO)
The circuit configuration can be extremely simplified, and the synchronization accuracy can be improved.

Further, according to the synchronous signal generating circuit and the synchronous inverter device according to the present invention, in addition to realizing the above method, the configuration of the reference waveform pattern generating means and the synchronous adjusting means includes a crystal oscillator, a counter, a memory, and a D / A converter. , A zero point detector, a logic circuit, and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a reference waveform pattern and a signal A, FIG. 3 is a detailed diagram of a zero point detector, and FIG. Operation waveform diagram,
FIG. 5 is a time chart for explaining the overall operation of the embodiment of FIG. 1, and FIGS. 6 to 8 are diagrams showing modified examples of the method of setting the reference waveform pattern and the synchronization adjustment pattern. 1: Crystal oscillator, 2, 3, Counter, 4: Memory (ROM),
5 ... reference waveform pattern generating means, 6 ... D / A converter, 8 ...
Zero detector, 9: synchronization adjustment means, 15: reference waveform pattern, 16: synchronization adjustment pattern.

Claims (6)

(57) [Claims] A synchronous adjustment band having a variable time width is set for each predetermined period of a reference waveform pattern for driving an inverter element,
A synchronous inverter synchronization method for adjusting the time width of the synchronous adjustment band to synchronize the inverter output with the AC to be synchronized. 2. The method according to claim 1, wherein the time width adjustment of the synchronization adjustment band detects a cycle of the AC to be synchronized and expands and contracts based on a difference between the detection cycle and the cycle of the reference waveform pattern. Synchronization method of inverter. 3. The time width adjustment of the synchronization adjustment band is performed by detecting a phase of the synchronization target AC corresponding to a reference phase of the adjustment band, and when the detection timing is included in the adjustment band, the adjustment is performed. 2. The method according to claim 1, wherein the remaining time of the band is set to zero. 4. A unit for generating a unit waveform pattern corresponding to a predetermined period of a reference waveform pattern for driving an inverter element, wherein a synchronous adjustment of a predetermined time width to the unit waveform pattern in response to a given reset signal. A reference waveform pattern generating means for adding and outputting a pattern, and a timing for detecting a phase change of an AC to be synchronized and detecting an AC phase corresponding to a reference phase of the synchronization adjustment pattern output from the reference waveform pattern generating means. A synchronization detecting means for outputting a synchronization signal to the control unit; determining whether an output timing of the synchronization signal is during the output of the synchronization adjustment pattern; synchronizing with the output timing when the determination is affirmative; In the case of, in synchronization with the output end timing of the synchronization adjustment pattern,
A synchronization adjustment means for outputting a reset signal to the reference waveform pattern generation means; and a synchronization signal generation circuit for a synchronous inverter. 5. The reference waveform pattern generating means includes a counter for counting clock pulses output from the clock pulse generating means, and a memory in which data of the unit waveform pattern and the synchronization adjustment pattern are stored using a time axis as an address. Wherein the counter reads and outputs pattern data at an address corresponding to the content of the counter, wherein the counter outputs a reset signal in synchronization with the end of the output of the synchronization adjustment pattern; 5. The synchronization signal generation circuit according to claim 4, wherein the synchronization signal is reset by a reset signal output from the synchronization signal generator. 6. A synchronous inverter device using the synchronous signal generating circuit according to claim 4.