JPH01259762A - Synchronization of synchronous inverter, synchronous signal generation circuit and synchronous inverter device - Google Patents

Abstract

PURPOSE:To improve synchronous precision, by synchronizing the reference waveform pattern inadjusting the time amplitude of a synchronizing band. CONSTITUTION:A reference waveform pattern generation means 5 is formed by a crystal oscillator 1, counters 2-3, and a load 4. A zero point detector 8 has a function as a synchronization detection means and outputs synchronous signals b0-b1. A synchronizing means 9 is composed of an inverter 10, AND gates 11-14, and an OR gate 13. A synchronous signal generation circuit is composed of these pattern generation means 5, zero point detector 8 and synchronizing means 9. The reference waveform pattern signal is given to a PWM inverter 7 through a D/A converter 6 to drive it. On this occasion, the time amplitude of the synchronizing zone is adjusted. The adjustment method is to detect the cycle of a synchronous object and to adjust it in proportion to the difference between the cycle of a fundamental waveform pattern. An inverter element is thereby driven by PWM control and with a reset signal the synchronized fundamental waveform pattern is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for synchronizing a synchronous inverter, a synchronous signal generation circuit, and a synchronous inverter device.

[Conventional technology]

A synchronous inverter operates by synchronizing the inverter frequency with a synchronized alternating current such as a commercial power source.

Conventionally, for example, the one disclosed in Japanese Patent Application Laid-Open No. 59-28882 is known.

According to this, P L L (Phase Locke
d Loop) circuit to detect the phase difference between the AC to be synchronized and the reference waveform signal (inverter drive waveform) generated in the inverter, adjust the frequency of the reference waveform signal based on the phase difference, and synchronize using this. That is.

[Problem to be solved by the invention]

However, according to the above-mentioned conventional technology, in order to configure a PLL circuit, a phase comparator that detects a phase difference and converts it into a voltage signal, and a voltage controlled oscillator (VCO) whose oscillation frequency changes in proportion to the output voltage are used. ) is required, and there is a problem that the circuit configuration becomes complicated.

Furthermore, in a power supply synchronized CVCF, the synchronization width is generally narrow, and when the power supply frequency fluctuates beyond this width, the synchronization is switched to asynchronous mode, and the synchronization width is operated at a so-called free-running frequency. In such a case, according to the prior art described above, it is necessary to set upper and lower limit frequencies for the oscillation frequency of the VCO according to the synchronization width. However, since vCOs are generally constructed from semiconductor integrated circuits, the oscillation frequency fluctuates due to the influence of ambient temperature.
There is a problem in that it is difficult to set the upper and lower limit frequencies with high accuracy.

An object of the present invention is to simplify the configuration of a synchronous circuit.

Another object of the present invention is to provide a method for synchronizing a synchronous inverter, which can improve synchronization accuracy, and a synchronizing signal generating circuit and a synchronous inverter device using the method.

[Means to solve the problem]

In order to achieve the above object, the method for synchronizing a synchronous inverter of the present invention sets a synchronization adjustment band with a variable time width for each predetermined period of a reference waveform pattern that drives an inverter element, and adjusts the time width of the synchronization adjustment band. The goal is to synchronize the inverter output with the synchronized AC.

Further, the synchronizing signal generating circuit according to the present invention has means for generating a unit waveform pattern corresponding to a predetermined period of a reference waveform pattern for driving an inverter element, and the unit waveform pattern is generated in response to a reset signal provided. a reference waveform pattern generating means for adding and outputting a synchronization adjustment pattern of a constant time width; and detecting a phase change of the synchronization target alternating current and corresponding to the reference phase of the synchronization adjustment pattern output from the reference waveform pattern generation means. a synchronization detection means for outputting a synchronization signal at a timing when an alternating current phase is detected; In the case of a negative judgment, on the other hand, in synchronization with the output end timing of the synchronization adjustment pattern,
and a synchronization adjustment means for outputting a reset signal to the reference waveform pattern generation means.

[Effect]

According to the present invention having such a configuration, the above object is achieved through the following actions.

That is, according to the method of the present invention, it is possible to synchronize the output waveform of the inverter with the AC waveform to be synchronized only by adjusting the time width of the synchronization adjustment band (for example, about ±1% of the frequency). Therefore, there is no need to adjust the waveform (frequency) of the reference waveform pattern itself.
The circuit configuration can be simplified and synchronization accuracy can be improved.

The method for adjusting the time width 'fA is as follows: 1. For example, detect the period of the synchronized AC, and L! This can be realized by adjusting according to the difference from the period of the i quasi-waveform pattern.

It can also be realized by detecting the phase of the synchronization target AC that corresponds to the reference phase of the synchronization adjustment band, and when the detection timing is included in the synchronization adjustment band, by setting the remaining synchronization adjustment band to zero.

In any of the above methods, the waveform of the reference wave pattern will be slightly different from the waveform of the alternating current to be synchronized because it is influenced by the waveform pattern of the synchronization adjustment band. However, in general, the frequency deviation related to synchronization adjustment is ±1
% or less, so there is almost no problem.

On the other hand, according to the circuit of the present invention, a reference waveform pattern in which a synchronization adjustment pattern is sequentially added to a unit waveform pattern (for example, in 1/2 cycle units) is successively generated from the chamber waveform pattern generating means in response to a reset signal. is output. According to the synchronous inverter device of the present invention, the inverter elements are driven by, for example, PWM control based on this, and an inverter output based on the reference waveform pattern is obtained. If the reset signal is input while the synchronization adjustment pattern is being output, the output is immediately switched to the next unit waveform pattern, and the reference waveform pattern synchronized with the AC to be synchronized is output. Thereby, the inverter output becomes synchronized with the synchronized alternating current. Note that if the period (frequency) of the synchronized AC changes significantly, the free-running frequency based on the fundamental wave pattern to which the synchronization adjustment pattern of a certain time width is added results in asynchronous operation. The unit waveform pattern is not limited to 1/2 cycle but 1 cycle.

118 cycles etc. can be selected. Further, the time width of the synchronization adjustment pattern is set according to the frequency fluctuation width of the synchronization target AC. Generally, it is about ±1% or less.

〔Example〕

Hereinafter, the present invention will be explained based on examples.

FIG. 1 shows a block diagram of an embodiment of an apparatus to which the present invention is applied. In the figure, crystal oscillator 1 and counter 2
A reference waveform pattern generating means 5 is formed by the counter 3 and the memory (ROM) 4.

The zero point detector 8 has a function as a synchronization detection means, and detects the zero point of the input AC to be synchronized, that is, the timing at which it changes from positive to negative or from negative to positive, and generates a synchronization signal. l bi is output.

The synchronization adjustment means 9 is an inverter 10. and gate 11,
12,14. It is made up of or games 1-13. The AND gate 11 receives the output signal a7 of the counter 3 and a synchronization signal. is entered. The output signal a of the counter 3 inverted by the inverter 10 and the synchronization signal b□ are input to the AND gate 12. The outputs of these AND gates 11 and 12 are input to an AND gate 14 via an OR gate 13. A signal A indicating that the output state of the reference waveform pattern is in the synchronization adjustment band is input from the counter 2 to the other input terminal of the AND gate 14. This signal A will be described in detail later.

These reference waveform pattern generation means 5, zero point detector 8,
The synchronization adjustment means 9 forms a synchronization signal generation circuit. Then, the reference waveform pattern signal to be output from now on is converted into an analog waveform signal by the D/A converter 6 and then given to the PWM inverter 7. The PWM inverter 7 has a well-known configuration, and 4! The inverter elements are controlled by PWM control based on the quasi-waveform pattern.

Next, the reference waveform pattern generating means 5, which is the main part, will be explained along with its operation.

The crystal oscillator 1 always generates a stable pulse with a constant frequency as a clock pulse. The counter 2 is, for example, a 128-decimal counter that counts clock pulses, and the counter 3 is a binary counter whose clock is the most significant bit signal a6 of the counter 2, and the output bit signal a of these counters.

-a7 counts clock pulses from 0 to 255.

Data related to the reference waveform pattern shown in FIG. 2 is stored in the ROM 4 in advance. As shown in the figure, the reference waveform pattern 15 is set to a pattern in which 172 cycles of a sine waveform is used as a unit waveform pattern, and a synchronization adjustment band (pattern) 16 of a fixed time width (n clocks) is added to this. .

Then, the phase of each positive and negative 1/2 cycle is set to 12
Divide into 8 and set addresses O~127 and 128~255, store positive half wave waveform data corresponding to O~(127-n), and store "0" from (127-n) to 127. " synchronization adjustment pattern 16 is stored, and the next 128 to (255
−n), and store negative half wave waveform data corresponding to (25
For 5-n) to 255, 1101+ is stored in the same way as the positive one.

As shown in FIG. 2, the signal A is a signal that reaches the ItHII level in synchronization with the synchronization adjustment pattern 16 of the reference waveform pattern 15. That is, the contents of counter 2 are between (127-n) and 127 and between (255-n) and 25.
When it is between 5, it becomes II HII.

Further, since the counter 3 is a binary counter, the content of the output changes alternately to ')i'' or L''' every time the highest pin 1 to signal aG of the counter 2 change twice. Therefore, each time counter 2 is reset, “HII
Or it changes to "L", resulting in a signal indicating a positive or negative half cycle. Here, the counter 2 is automatically reset when the AND gate 14 outputs the reset signal B based on the synchronization signal and when the counter 2 reaches the full count 1-. This latter reset can be regarded as a reset signal that is output in synchronization with the timing at which the cycle adjustment pattern 16 ends, and constitutes a part of the synchronization adjustment means 9.

The zero point detector 8 is configured as shown in FIG. A circuit consisting of a capacitor 23 and an AND gate 24 detects the fall of Vc, that is, the zero point where it changes from positive to negative, and outputs a pulsed synchronization signal b0.
to appear. Similarly, the voltage is
It detects the rising edge of C, that is, detects the zero point that changes from negative to positive, and outputs a pulse-like synchronization signal b□. A time chart of these signal waveforms is shown in FIG.

Here, the operation related to synchronization adjustment will be explained using FIG. 5. If reset signal B is not input to counter 2, D
The output of the /A converter 6 has a waveform as shown by the broken line in the figure because the data in the ROM 4 is output as is. on the other hand,
When the pulse signal b0 when the synchronization target AC V changes from positive to negative is input when the signal A is ``H'''', the counter 2 is reset at time t1. The count starts from 128 on the content line □.That is, the negative half wave starts from t□.

Similarly, at time t2, counter 2 is reset again by b□. In this way, a sinusoidal waveform synchronized with the synchronization target AC v1 is obtained.

Here, if the synchronization target AC v1 has a small fluctuation range of about 1% around a certain frequency.

The time width of the synchronization adjustment pattern is approximately ±1%1% of the total,
For example, ±1% based on the center phase of the synchronization adjustment pattern.
Set the width to . As a result, in the state of being synchronized with the synchronization target AC, the period will expand or contract within the range of the synchronization adjustment band by about ±1%1%. Furthermore, since the adjustment range is small relative to the whole, the inverter output waveform is approximately a sine wave.

On the other hand, if there is no human power for v1, or if a synchronization target alternating current with a frequency outside the synchronization adjustment pattern 16 is manually powered, the counter 2 will not be reset.

Therefore, the waveform shown by the broken line of the D/A output in FIG. 5 becomes the PWM reference waveform pattern.

As described above, according to this embodiment, first, the waveform data in the ROM 4 is read out using a clock signal based on the highly accurate crystal oscillator 1 with a stable oscillation frequency to generate a reference waveform pattern. Therefore, the frequency accuracy is extremely high.

In addition, since synchronization is achieved by adjusting the synchronization adjustment band set every 172 cycles of the reference waveform pattern, the synchronization accuracy of one frequency and the accuracy of the synchronization range are high, and the circuit configuration is extremely simple. be.

Also, even when asynchronous, for the same reason as mentioned above,
A highly accurate free-running frequency can be obtained.

In the above embodiment, a synchronization adjustment band is provided for each 1/2 cycle unit waveform pattern, but the synchronization adjustment band is provided once per cycle as shown in (a) in FIG. 6, or (b).
), such as once every 1.5 cycles, or even once every more cycles.

In addition, in the above embodiment, the waveform of the synchronization adjustment pattern 16 is set to 0'', but the terminal part of the sine wave as in the seventh part (a) or the terminal part as in (b) is shown. It is also possible to use an arbitrarily modified approximate waveform, or even a waveform of an arbitrary part of a sine wave as shown in (c).

Also, regardless of the inverter with a sine wave output, Fig. 8(a)
It can also be applied to arbitrary waveforms such as triangular wave output as shown in (b) and square wave output as shown in (b).

Further, in the above embodiment, an example was shown in which one cycle's worth of waveform pattern data was stored in the ROM 4, but only the corresponding 1/2 cycle's worth of data is stored, and based on the output of the counter 3, It is also possible to invert the data in the ROM 4 and use it.

〔Effect of the invention〕

As explained above, according to the method of the present invention, synchronization! l!
Since synchronization is achieved by adjusting the banding time width, there is no need to adjust the waveform of the reference waveform pattern itself, eliminating the need for a voltage controlled oscillator (VC○) and greatly simplifying the circuit configuration. It is possible to simplify the process and improve synchronization accuracy.

Further, according to the synchronization signal generation circuit and the synchronous inverter device according to the present invention, in addition to realizing the above method, the configuration of the reference waveform pattern generation means and the synchronization adjustment means includes a crystal oscillator, a counter, a memory, and a D/A converter. , a zero point detector, a logic circuit, and the like.

[Brief explanation of the drawing]

Fig. 1 is a block configuration diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the reference waveform pattern and signal A, Fig. 3 is a detailed configuration diagram of the zero point detector, and Fig. 4 is a diagram of the zero point detector. Operating waveform diagram,
FIG. 5 is a time chart illustrating the overall operation of the embodiment shown in FIG. 1, and FIGS. 6 to 8 are diagrams showing modified examples of the method of setting the reference waveform pattern and the synchronization adjustment pattern, respectively. DESCRIPTION OF SYMBOLS 1... Crystal oscillator, 2, 3... Counter, 4... Memory (ROM), 5... Reference waveform pattern generation means, 6... D/A converter, 8... Zero point detector, 9... Synchronization adjustment means, 15... Reference waveform pattern, 16...
Synchronous adjustment pattern.

Claims (1)

[Claims] 1. A synchronization adjustment band with a variable time width is set for each predetermined period of a reference waveform pattern that drives an inverter element, and the time width of the synchronization adjustment band is adjusted to adjust the inverter output to synchronized AC. How to synchronize synchronous inverters. 2. The synchronous inverter according to claim 1, wherein the time width adjustment of the synchronization adjustment band is performed by detecting the period of the synchronization target alternating current and expanding or contracting it based on the difference between the detected period and the period of the reference waveform pattern. How to synchronize. 3. To adjust the time width of the synchronization adjustment band, detect the phase of the synchronization target AC that corresponds to the reference phase of the adjustment band, and when the detection timing is included in the adjustment band, adjust the time width of the adjustment band. Claim 1 is based on reducing the time to zero.
How to synchronize a synchronous inverter as described. 4. It has means for generating a unit waveform pattern corresponding to a predetermined period of a reference waveform pattern for driving the inverter element, and adds a synchronization adjustment pattern of a certain time width to the unit waveform pattern in response to a reset signal provided. a reference waveform pattern generation means that detects a phase change of an AC to be synchronized, and generates a synchronization signal at a timing when an AC phase corresponding to a reference phase of the synchronization adjustment pattern outputted from the reference waveform pattern generation means is detected; a synchronization detection means for outputting a synchronization signal; and a synchronization detection means for determining whether or not the output timing of the synchronization signal is during the output of the synchronization adjustment pattern, and when a positive determination is made, the synchronization signal is synchronized with the output timing, and when a negative determination is made, the synchronization detection means In synchronization with the output end timing of the synchronization adjustment pattern,
A synchronous signal generation circuit for a synchronous inverter, comprising: synchronous adjustment means for outputting a reset signal to the reference waveform pattern generation means. 5. The reference waveform pattern generation means includes a counter that counts clock pulses output from the clock pulse generation means, and a memory in which data of the unit waveform pattern and the synchronization adjustment pattern are stored with the time axis as an address. The counter is configured to read and output pattern data at an address corresponding to the contents of the counter, and the counter receives a reset signal output in synchronization with the end of output of the synchronization adjustment pattern, and a reset signal output from the synchronization adjustment means. 5. The synchronizing signal generating circuit according to claim 4, wherein the synchronizing signal generating circuit is reset by a reset signal. 6. A synchronous inverter device using the synchronous signal generation circuit according to claim 4 or 5.