KR950001436B1 - Reference pulse generated circuit - Google Patents

Abstract

The circuit improves the response speed of the PLL (Phase Locked Loop) and easily changes the pulse width of the reference pulse. The circuit comprises; a reference frequency generator (1) providing the reference frequency; a reference frequency controller (5) inputting the reference frequency (5) of a reference frequency generator synchronizing with the comparison input pulse; a counter counting the output signal of the reference frequency controller; a register (8) storing the reference pulse width data; a comparator (9) controlling the reset of the defence frequency unit (5); a S-R flip-flop generating the reference signal after receiving the reset control signal; the phase detector (3) outputting the pulse width difference between the reference pulse of the S-R flip-flop and the comparison input pulse.

Description

Reference pulse generator

1 is a conventional reference pulse generating circuit diagram.

2a, d is a waveform diagram of each part according to FIG.

3 is a reference pulse generation circuit diagram of the present invention.

4 is a detailed circuit diagram of a reference pulse generator according to FIG. 3;

5 is a waveform diagram of each part according to FIG.

* Explanation of symbols for main parts of the drawings

1: reference frequency oscillator 2: frequency divider circuit

3: phase detection unit 4: reference pulse generator

5: reference frequency control unit 6: SL flip-flop

7: counter 8: register

9: comparator D-F / F: deflip-flop

AND ₁ : ANDGATE

The present invention relates to a reference pulse generating circuit used for a phase detector of a PLL (Phase Locked Loop: PLL), in particular, to improve the response speed of the PLL and to easily change the pulse width of the reference pulse to a desired width. It relates to a reference pulse generating circuit.

1 is a conventional reference pulse generating circuit diagram, as shown therein, which is output from a reference frequency oscillation unit 1 for oscillating a reference frequency by an oscillation signal of a crystal oscillator (X-Tal) and the reference frequency oscillation unit 1 thereof. A division circuit 2 for generating a reference pulse having a desired pulse width by dividing the reference frequency at an arbitrary division ratio, and a reference pulse output from the division circuit 2 and a pulse of a comparison input pulse CP supplied from the outside; The phase detection section 3 which compares the width and outputs the pulse width difference signal is described. The operation of the conventional circuit configured as described above will be described with reference to the waveform diagram of FIG.

The reference frequency is oscillated and output from the reference frequency oscillator 1 by the oscillation signal of the crystal oscillator (X-Tal), and the reference frequency is divided by an arbitrary division ratio in the frequency divider circuit (2) and (b) of FIG. Similarly, a reference pulse having a desired pulse width is output, and the reference pulse is input to the phase detector 3.

At this time, a comparison input pulse CP is output from the external oscillator (not shown in the drawing) as shown in FIG. 2A and input to the phase detection unit 3, and the phase detection unit 3 is compared with the reference pulse. Comparing the width of the pulses (CP), outputs a waveform as shown in (d) of FIG. 2 from the time when the comparison input pulse (CP) becomes low potential until the reference pulse becomes low potential, and converts this output into a voltage Control the external oscillator to oscillate at a certain frequency.

If the comparison input pulse CP generated in the external oscillator coincides with the pulse width of the reference pulse generated in the frequency divider 2, the frequency of the reference pulse and the comparison input pulse CP coincide.

On the other hand, (d) of FIG. 2, which is the output waveform of the phase detector 3, the phase detector is obtained from the point at which the comparison input pulse CP and the reference pulse change from a low potential to a high potential, and then either signal changes to a low potential. It is a waveform until a detection completion signal is generated as shown in (c) of FIG. 2 output in (3).

However, as described above, in the conventional reference pulse generating circuit, since the start of the pulse is compared with the reference pulse, the output of the phase detector 3 is different from the pulse width difference between the reference pulse and the comparison input pulse. Inconsistencies arise.

Accordingly, the output of the phase detector 3 controls the external oscillator so that the external oscillator does not have a stable oscillation and the speed decreases until the reference pulse and the comparison input pulse are synchronized.

In order to solve such a conventional problem, the present invention has been made a reference pulse generating circuit for generating a reference pulse in synchronization with the comparison input pulse so that the pulse width difference between the comparison input pulse and the reference pulse coincides with the output waveform. This will be described in detail with reference to the accompanying drawings.

3 is a reference pulse generation circuit diagram of the present invention, and as shown therein, a reference frequency oscillator 1 for oscillating a reference frequency by an oscillation signal of a crystal oscillator (X-Tal) and an output from the reference frequency oscillator 1 A reference pulse generator 4 for generating a reference pulse by synchronizing the reference frequency to be generated from an external oscillator (not shown in the drawing) with the reference input pulse CP, and the reference output from the reference pulse generator 4 And a phase detector 3 for comparing the pulse width of the comparison input pulse CP generated by the external oscillator and outputting a pulse signal corresponding to the pulse width difference.

FIG. 4 is a detailed circuit diagram of the reference pulse generator 4 of FIG. 3, and as shown therein, a deflip-flop (DF / F) to which a comparison input pulse CP is applied as a clock signal and its deflip-flop (DF). A reference frequency controller (5) composed of an AND gate (AND ₁ ) for and / or combining the output signal (Q) of the / F) with the reference frequency output from the reference frequency oscillator (1), and controlling the input of the reference frequency; A counter 7 for counting an output signal of the reference frequency controller 5, a register 8 for storing data for setting a reference pulse width, a reference frequency counted at the counter 7 and the register ( 8) a comparator 9 for controlling the reset of the flip-flop DF / F by comparing the data stored in the data and a signal output from the AND gate AND ₁ of the reference frequency controller 5; Under the control of the set and the reset control by the output signal of the comparator 9 JSR constitute a flip-flop (6) for generating a scan.

The operation and effects of the present invention configured as described above will be described in detail with reference to the waveform diagram of FIG. 5.

When the reference frequency is oscillated and output by the oscillation signal of the crystal oscillator (X-Tal), the reference frequency is applied to one input terminal of the AND gate AND ₁ . On the other hand, when the comparison input pulse CP, which is the output signal of the external oscillator, is input to the clock terminal CK of the deflip-flop DF / F, the deflip-flop DF / F is clocked and its output signal Q ) Is the other input terminal of the AND gate (AND ₁ ), that is, when the comparison input pulse (CP) output from the external oscillator is changed from low potential to high potential as shown in (a) of FIG. 5, the comparison input pulse (CP) of At the rising edge, the flip-flop DF / F is clocked so that its output signal Q is output at high potential, and this high potential signal is applied to the other input terminal of the AND gate AND ₁ . Therefore, at this time the AND gate the reference frequency signal input to one input terminal of the (AND ₁₎ is output via the AND gate (AND _1), i.e., the high potential at the reference frequency signal the high-potential signal when the AND gate (AND ₁₎ Since the signal is outputted, the SL flip-flop 6 is set, and the reference pulse which is the output signal of the SL flip-flop 6 becomes high potential as shown in FIG.

On the other hand, the output signal of the AND gate AND ₁ is counted by the counter 7 and input to the comparator 9 as a comparison signal, wherein the reference pulse width setting data previously stored in the register 8 is input to the comparator 9. The comparator 9 compares the signal counted and output from the counter 7 with the reference pulse width setting data.

Therefore, the comparator 9 outputs a high potential signal from the comparator 9 when the signal counted and output from the counter 7 becomes equal to the reference pulse width setting data output from the register 8. The def flip-flop (DF / F) and the SL flip-flop 6 will be reset. As the flip-flop DF / F is reset in this way, its output signal Q is output at a low potential, so that a low potential signal is output from the AND gate AND ₁ regardless of the reference frequency signal, thereby counting the counter 7. Since the operation is stopped and the SL flip-flop 6 is reset, the reference pulse which is the output signal thereof becomes low potential as shown in Fig. 5B. That is, the reference pulse section output from the SL flip-flop 6 is from the time point at which the comparison input pulse CP is input to the time point at which the high potential signal is output from the comparator 9 according to the count signal of the counter 7.

For example, if the period of the reference frequency output from the reference frequency oscillator 1 is 1 mu sec, and the width of the desired reference pulse is 500 mu sec, 500 is stored in the register 8 as the reference pulse width setting data. At this time, the output of the SL flip-flop 6 becomes high potential while the reference frequency output from the reference frequency oscillator 1 is counted 500 times by the counter 7 after the comparison input pulse CP is input as described above. When the counter 7 is counted 500 times, a high potential signal is output from the comparator 9 to reset the SL flip-flop 6 and stop the operation of the counter 7.

Therefore, as shown in (b) of FIG. 5 generated by the above operation, the reference pulse and the comparison input pulse (CP) as shown in (a) of FIG. 5 output from the external oscillator are the phase detector (3). Is inputted to the phase detection section 3, the phase detection section 3 is inputted to the phase detection section 3, and the phase detection section 3 has a comparison input pulse as shown in d of FIG. When the CP) outputs a high potential signal as soon as it changes from high potential to low potential, and then outputs a low potential signal when the reference pulse changes from high potential to low potential, accordingly, the output signal of the phase detector 3 is compared with the reference pulse. It is always coincident with the pulse width difference of the pulse CP.

On the other hand, the phase detector 3 outputs a detection completion signal such as (c) of FIG. 5 to the counter 7 at the time when both the reference pulse and the comparison input pulse CP are changed to the low potential, and the counter 7 Clear).

As described in detail above, the present invention generates a reference pulse synchronized with the comparison input pulse so that the pulse width difference between the comparison input pulse and the reference pulse can be accurately detected, and thus it can be applied to a circuit requiring a high response speed. There is an effective effect, and the pulse width can be easily changed, which is useful for a circuit requiring a change in the pulse width.

Claims (3)

A reference frequency oscillator 1 for oscillating a reference frequency, a reference frequency controller 5 for receiving the reference frequency output from the reference frequency oscillator 1 in synchronization with a comparison input pulse supplied from the outside, and the reference frequency controller A counter 7 for counting the output signal of (5), a register 8 for storing the reference pulse width setting data, and a count signal of the counter 7 with the reference pulse width setting data of the register 8; The comparator 9 which controls the reset of the reference frequency control unit 5 by comparison, and the set control by the output signal of the reference frequency control unit 5 and the reset control by the output signal of the comparator 9 Received by the R flip-flop (6) for generating a reference pulse, and the phase detection unit (3) for comparing the reference pulse output from the R flip-flop (6) and the comparison input pulse and outputs the pulse width difference That Reference pulse generating circuit for a gong. 2. The flip-flop (DF / F) according to claim 1, wherein the reference frequency controller (5) receives a comparison input pulse as a clock signal and is reset by the output signal of the comparator (9). And an AND gate (AND ₁ ) which AND-combines the output signal of the (DF / F) and the reference frequency output from the reference frequency oscillator (1). The reference pulse generation circuit according to claim 1, wherein the counter (7) is configured to be cleared by a detection completion signal generated at the time of detecting the pulse width by the phase detection unit (3).