KR950007610B1 - Double speed deflection-sync signal system of television - Google Patents

Abstract

The system comprises an oscillator(10) for generating reference clock of the system, a divider(20) for dividing the output clock of the oscillator(10) by two, a first counter(30) for counting the output clock of the oscillator(10), a second counter(40) for counting the output signal of the divider(20), a latch(50) for latching an output value of the second counter for a period of a horizontal synchronization signal(Hsync), a comparator(60) for comparing the counted value of the first counter(30) with a latched value of the second counter(40) to output high voltage in case of the equal values, an OR gate for ORing the output of the comparator(60) and the horizontal synchronization signal(Hsync) to output it as a reset signal(RE) of the first counter(30), and a decoder(80) for receiving the output of the first counter(30) to output a pulse in the set time.

Description

Double Speed Deflection Synchronous Signal Generation System for Television Receiver

1 is a block diagram of a double speed deflection synchronization signal of a typical television receiver;

2 is a block diagram of a double speed deflection synchronous signal generation of a television receiver according to the present invention;

3 is a waveform diagram of each part of (a) to (h).

4 is a waveform diagram for explaining a periodic change of a horizontal synchronization signal.

(A) and (b) of FIG. 5 are waveform diagrams for explaining the decoding of the decoder in FIG.

* Explanation of symbols for main parts of the drawings

10: oscillator 20: divider

30: first counter 40: second counter

50: latch 60: comparator

70: Oagate 80: Decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for generating a double scan synchronizing signal in a double scan television receiver, and in particular, to make it suitable for actively generating a horizontal synchronizing signal even when the syringes of one horizontal scanning line vary in a nonstandard signal. A double speed deflection synchronization signal generation system of a television receiver.

FIG. 1 is a block diagram of a double-speed deflection synchronization signal generation of a general television receiver. As shown in FIG. 1, a phase comparator for comparing a phase of an input signal iN with a signal divided and returned and outputting a signal corresponding to the difference ( 1), a low pass filter 2 for low pass filtering the signal output from the phase comparator 1, and a voltage controlled oscillator for generating a signal having a frequency corresponding to the level of the signal output from the low pass filter 2; (VCO) 3, a 2 / N divider 4 for dividing the output signal of the voltage-controlled oscillator 3 by 2 / N, and two output signals for the 2 / N divider 4 It is composed of a 1/2 divider (5) for supplying this as an input signal of one side of the phase comparator 1, the operation thereof will be described as follows.

The input signal iN of the predetermined frequency f _H is compared with a phase of a predetermined frequency signal output from the 1/2 divider 5 by the phase comparator 1 and thus corresponds to a phase difference between the two input signals. The signal is output.

The signal output from the phase comparator 1 is low-pass filtered by the low pass filter 2 so that only the DC component is supplied to the voltage controlled oscillator 3, and the voltage controlled oscillator 3 receives the input DC voltage. A signal N · f _H having a frequency according to the level of N is generated, which is divided by a predetermined division ratio in the 2 / N divider 4 and output to the output terminal Out.

In addition, the output signal of the 2 / N divider 4 is supplied to the 1/2 divider 5 on the one hand, and is further divided by 2 and output from the voltage controlled oscillator 3 therefrom. The frequency signal of 1 / N of f _H ) is output, which is supplied to one input of the phase comparator 1 so that its output signal is changed, that is, the phase difference between the two input signals of the phase comparator 1 When this process is performed several times by operating in a decreasing direction compared to the previous phase difference, the phase difference between the two input signals of the phase comparator 1 is exactly the same.

Accordingly, a signal having a frequency corresponding to twice the frequency of the input signal iN is output to the output terminal Out. Therefore, when the horizontal sync signal H _sync is supplied as the input signal iN, a signal having a frequency twice as high as the horizontal sync signal H _sync is output from the output terminal Out. It can be used as.

However, the conventional PEL-type double speed system has to use an analog oscillator and a low pass filter, which is difficult to design the oscillator and low pass filter. Moreover, the voltage-controlled oscillator is often unstable and the output is unstable. .

The present invention has been devised to digitally generate a double speed signal without using a low pass filter or a low pressure controlled oscillator in a PLL method. It will be described in detail by the accompanying drawings.

2 is a block diagram of a system for generating a double speed deflection synchronization signal of a television receiver according to the present invention. As shown therein, an oscillator 10 for generating a reference clock signal of the system and an output signal of the oscillator 10 are shown in FIG. The frequency divider 20 to divide, the first counter 30 for counting the output signal of the oscillator 10, the second counter 40 for counting the output signal of the frequency divider 20, and horizontal synchronization The latch 50 latching the output value of the second counter 40 during one period of the signal H _sync , and the count value of the first counter 30 and the second counter 40 latched to the latch 50. Value of the comparator 60 and outputting a high potential when the same value, and the output signal of the comparator 60 and the horizontal synchronization signal (H _sync ) and the reset signal of the first counter 30 A decoder for outputting a pulse at a predetermined time by receiving the output of the OR gate 70 and the output of the first counter 30 To be configured in 80, if to this third reference also to the accompanying FIG. 5 explained in detail as follows.

The oscillator 10 generates and outputs a reference clock signal as shown in (a) of FIG. 3 required by the system, and the divider 20 divides the reference clock signal into two and divides the signal as shown in (d) of FIG. The second counter 40 counts the pulses output from the divider 20.

If in the initial state, the horizontal sync signal (H _sync), such as a third-degree (f) type, of the second counter 40, such as a third-degree (e) by the rising edge of the horizontal synchronizing signal (H _sync) The output is latched to the latch 50 so that the count value of the second counter 40 immediately before the high potential of the horizontal sync signal H _sync is input to the latch 50 is latched and output. If the count value of 40 is " N ", the value output to the latch 50 is also " N ".

Then, the first and second counters 30 and 40 are reset by the high potential of the horizontal synchronization signal H _sync as shown in (b), (e) and (f) of FIG. It starts counting from 00˝ and outputs a value that is continuously increasing. The comparator 60 compares the value latched by the latch 50 with the value output from the first counter 30, and the compared value is the same. The first counter 30 is reset by the high potential as the high potential is output as shown in FIG. 3 (c).

That is, since the divider 20 is a 1/2 divider and the second counter 40 counts one cycle value of the horizontal sync signal H _sync , the value input to the comparator 60 is a horizontal sync signal. (H _sync ) It becomes 1/2 of the number of clocks of oscillator 10 in one period.

On the other hand, since the first counter 30 counts the clock signal output from the oscillator 10 without counting the divided signal, the first counter 30 is reset twice in one period of the horizontal sync signal H _sync , resulting in the first counter. Since the counter 30 counts at twice the speed of the second counter 40, the first counter 30 becomes N counter, and if the latched value of the latch 50 is N + 1 When the first counter 30 is operated to N + 1 counter.

Cycle variation of the horizontal synchronous signal (H _sync) is a periodic change in the means the changes such as the first time period of the horizontal synchronous signal (H _sync), etc. V CR is gradually changed, and the horizontal synchronizing signal (H _sync) very slow In this case, above T ₂₁ ((h) of FIG. 3), there is an influence of the rising edge signal t2 output from the comparator 60, and when smaller than that, until the horizontal synchronization signal H _sync is input after t2. It's time.

That is, assuming that the horizontal synchronous signal is the same as in FIG. 4 (ta = tb = tc = td), when the output of the tb section is based on the value of the ta section, and when ta = tb, the output of tb is generated. An error occurs. However, although this error may be less than or equal to T11, it is negligible because T11 is very small compared to ta. And, since the degree of change of ta to tb is very small, it can be seen that the change of the horizontal sync signal (H _sync ) period is small.

The periodic change of the horizontal synchronization signal H _sync is stored in the latch 50 and used as a next reference value, so that the signal becomes one half of the horizontal synchronization signal H _sync period, that is, the first signal. When the value output from the one counter 30 is supplied to the decoder 80, the decoder 80 decodes and outputs the value input from the predetermined value as shown in (a) and (b) of FIG.

As described in detail above, in the present invention, in generating a horizontal synchronous signal of 2 times, a signal obtained by dividing an output signal of an oscillator by two and a signal which is not divided are counted for one period of the horizontal synchronous signal and not divided based on this. By comparing the value counted with the unsigned signal and outputting the signal when it is the same, digital speed signal can be generated without using low-pass filter or voltage controlled oscillator, which simplifies the production process and stabilizes the output. It has an effect.

Claims (1)

An oscillator 10 for generating a reference clock signal of the system, a divider 20 for dividing the output signal of the oscillator 10, and a first counter 30 for counting the output signal of the oscillator 10; And a second counter 40 for counting the output signal of the divider 20, a latch 50 for latching the output value of the second counter 40 during one period of the horizontal sync signal H _sync . The comparator 60 outputs a high potential when the count value of the first counter 30 and the value of the second counter 40 latched to the latch 50 are equal to each other, and the output of the comparator 60. And an ORA gate 70 for outputting the horizontal sync signal H _sync and outputting it as the reset signal RE of the first counter 30, and receiving the output of the first counter 30. A double speed deflection synchronous signal generation system for a television receiver, characterized by comprising a decoder (80) for outputting a pulse at a time point.