JPS6174464A - Vertical synchronizing signal generation circuit - Google Patents

Abstract

PURPOSE:To obtain stable and accurate inside vertical synchronizing signals corresponding to various outside vertical synchronizing signals different in phase relation from horizontal synchronizing signals by synchronizing outside vertical synchronizing signals by a timing reference signal which is always separated sufficiently from the leading edge of the outside vertical synchronizing signal. CONSTITUTION:An input signal of an outside vertical synchronizing signal input terminal 1 is frequency-divided into 1/2 by an 1/2 frequency dividing circuit 2 of a vertical synchronizing signal generation circuit, and a logical value of the input signal and the frequency divided signal is obtained by and the result is supplied to the first synchronizing circuit 4 and the second phase detecting circuit 17. Also the input signal of an outside horizontal synchronizing signal input terminal 12 is processed at an nfH VC09 and a 1/N dividing circuit 10, and two pulse signals used as reference signal different in phase are outputted. And, the output of the circuit 4 is processed by the output of a window pulse generating circuit 16 which has processed the outputs of the circuit 10 and circuit 17 at the 2nd synchronizing circuit 5, the first counter 6 and the second counter 7. The result is synchronized with the reference signal at timing always separated sufficiently, producing a stable and accurate inside vertical synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Application in M Industry The present invention relates to a vertical synchronization signal generation circuit used in image display devices such as television receivers and image processing devices such as image file systems.

(b) Conventional technology There are methods for creating accurate and stable internal vertical synchronization signals in image processing devices, etc. as mentioned in the introduction, for example.
As shown in Japanese Patent No. 9-15595, a method of obtaining a frequency signal that is an integer multiple of the horizontal frequency by frequency-dividing it to a vertical frequency has been used for a long time.

However, such a method is not suitable for processing various image signals such as television receivers, special playback VTRs, etc.
Alternatively, it is not appropriate when handling image signals from a computer or the like. This is because the frequency of the horizontal and vertical synchronizing signals and the phase relationship between the two synchronizing signals are not constant in each of the above image signals. This is because it may not be possible to accurately capture an external vertical synchronization signal input through a gate that is opened and closed by the frequency output.

Therefore, as a simple alternative to this method, it is conceivable to take in an external vertical synchronization signal at the timing of a reference signal of a constant phase, and use the signal obtained thereby as an internal vertical synchronization signal. However, in this way, simply the constant phase base 4
! ! In the method of capturing and synchronizing at the same timing, if the leading edge of the external vertical synchronizing signal is located very close to the timing of the reference signal, the phase fluctuation of the leading edge of the vertical synchronizing signal will A phase fluctuation of one cycle width of the reference signal occurs in the obtained internal vertical synchronization signal. This phenomenon is particularly noticeable when an external vertical synchronizing signal separated from a 2:1 incremental system television composite video signal is input. This is because, with the above external vertical synchronization signal, the signal waveform immediately before the vertical synchronization signal part in the composite video statement is different between odd and even fields, and the video signal part is shifted to the synchronization signal level. As a result of the so-called video-in-network,
This is because "fluctuation" of the leading edge as described above is very likely to occur. Therefore, this method cannot be applied to the above-mentioned image processing apparatus which requires a stable internal vertical synchronization signal.

(C) Problems to be Solved by the Invention The present invention can accommodate various external vertical synchronization signals that differ in vertical frequency itself or phase relationship with the horizontal synchronization signal.
Moreover, it is an object of the present invention to provide a vertical synchronization signal generation circuit that can create a stable and accurate internal vertical synchronization signal in response to the phase fluctuation of the vertical synchronization signal.

(d) Means for solving the problem In the present invention, the means for generating the first, second, and fourth signals having different phases from each other, and the phase difference between the first and second reference signals and the external vertical synchronization signal are detected. and a means for taking in the vertical synchronization signal at the timing of the reference signal corresponding to the detected phase difference and deriving it as an internal vertical synchronization signal.

(E) Effect According to the above configuration, the external vertical synchronizing signal is always synchronized with the reference signal whose timing is separated by light from the leading edge, so the influence of the phase fluctuation of the leading edge is eliminated. Ru.

Embodiment FIG. 1 shows an embodiment of the vertical synchronization signal generation circuit of the present invention. In the figure, (1) is an external vertical synchronization signal (hereinafter referred to as external > input terminal, (2) is a 172 frequency dividing circuit for the V signal, (3) is an AND gate that receives the frequency divided output signal and the above V signal as input, (4)
is the internal horizontal sync pulse (hereinafter referred to as
6(5), which is the first synchronization circuit consisting of a D flip-flop, etc., which captures data at the timing of the internal H pulse
(6) is a second synchronization circuit that can have the same configuration as this first synchronization circuit and captures its output signal by another internal H pulse; (6) counts the number of internal H pulses within one cycle of the output signal; The first counter, 7), is preset with the count result, and the second synchronization circuit (7) is preset with the count result.
a second counter (8) that is reset by the output signal of (5);
is the output terminal from which the internal vertical synchronization signal is derived.

Also, (9) is an integral multiple of the standard vertical layer wavenumber f, that is, n
A vCo (voltage controlled oscillator) with a center frequency of rI ((n-1), R10) generates from its output signal two reference signals having a frequency rH and mutually different phases, namely a first, second internal H pulse, and A frequency dividing circuit that creates a 2f'H pulse, and (11) a first phase detection circuit that detects the phase of the first internal H pulse and the external H pulse that is input to the terminal (12). (phase-locked loop) circuit (13). (14) introduces the first and second internal H pulses and flips one of them.
A selector circuit (16) that selects according to the output of the flop (15) outputs the selected H pulse toward the first synchronization circuit (4), and widens the pulse width of the pulse forward and backward. A window pulse generation circuit (17) is a second phase detection circuit that detects the phase difference between the wide pulse and the output signal of the AND gate (3).
15) is now inverted.

Note that (18) is an output terminal for the internal H pulse.

The operation of this embodiment will be explained with reference to the signal waveform diagrams of FIGS. 2 and 3. Now, if the mV flaw signal a) outside the field period (IV) shown in Figure 2 is input to the terminal (1), the output signal of the 172 frequency divider circuit 2) will be as shown in the figure (B), The output number A of ANDGATE 3) is the same figure (c).
becomes. This signal (c) is taken in by the next first synchronization circuit (4) at the timing of the leading edge of the internal H pulse output from the win 1 pulse generation circuit (16). Therefore, now, as the internal H pulse, the selector circuit <14
If the second internal H pulse (e) is outputted from the first second inner gl (1 (pulse), kuho) input to The signal will be as shown in the same figure.

Then, this output signal (f) is taken in by the second synchronization circuit (5) at the leading edge timing of the first internal H pulse (d), so the output signal is as shown in the same figure (g). As a result, an internal vertical synchronization signal with a 2v period, that is, a frame period is obtained.

On the other hand, the second phase detection circuit (17) compares the phase of the rise timing of the output signal (C) of the AND gate (3) with the wide pulse (N) (Figure 3) from the window pulse generation circuit (16). ). Here, Figures 2 and 3
In the figures, the same letters indicate the same signals.

Therefore, the selector circuit (
Assuming that the first internal H pulse (E) is output from 14), in this state, the wide pulse (N) is
i, P2, and it is detected whether a rising edge of the signal (C) exists within this pulse (Pl) (P2) period. That is, when the above-mentioned rising edge does not exist within the period as in the P1 period, the output (S) of the second phase detection circuit (17) is maintained at a high level; If the above-mentioned rising edge exists in The state described above in which the pulse (D) is output is switched to the state in which the second internal H pulse (E) is output.

Therefore, the pulse given from the window pulse generation circuit (16) to the first synchronization circuit (4) is also t1
After this point, the second internal H pulse (E) becomes as shown in the figure, and this pulse (E) synchronizes (takes in) the signal (C) as described above, and the first synchronization circuit (
The signal (to) can be obtained from (4). That is, here, of the first and second internal H pulses (2) (E), the phase that is sufficiently far from the leading edge (rising) position of the external V signal (C) of the frame period from the AND gate (3) is selected. The internal H pulse that has one is selected, and the V signal (C) is synchronized with that H pulse. Similarly, the wide pulse (L) from the window pulse generation circuit (16) is also synchronized. As shown in the figure, the above-mentioned operation is repeated thereafter.

The frame period internal V signal (FIG. 2) obtained from the second synchronization circuit (5) as described above then resets the first counter (6) at its leading edge. Therefore, this first
The counter (6) will be reset next time after this is reset.
In other words, the number of first internal H pulses within one frame period (2V) is counted until the count is reached, and the count f is preset in the second counter (7). This second counter (7
) is also reset at the leading edge of the signal (G), and after this reset, the 2r from the frequency dividing circuit (10)
Count H pulses. This second counter (7) generates an output when it counts up to the preset value, and also counts up to the preset value again, and is then reset by the next internal V signal (g). This operation is repeated. Therefore, as the output signal of this second counter (7), the internal V of the field period synchronized with the external ■ signal (A) as shown in Figure 2 (H).
A signal will be obtained.

Note that the first synchronization circuit (4) is a flip-flop (
Since it will operate with two different synchronization timings depending on the state of 15), in order to always obtain an internal V signal with a constant phase, 2. Although the output signal of the first synchronization circuit (4) is resynchronized with an internal H pulse of a constant phase,
If the external V signal to be supplied does not have a large phase change, that is, the switching of the two synchronization timings described above does not occur frequently, and a very strict internal V signal is not required, the second The synchronization circuit (5) can be removed.

Further, the pulses supplied to the second synchronization circuit (5) and the first counter (6) are either one of the first, second, and second internal H pulses (k2) and (e), or the internal H pulse of the third phase. Alternatively, a pulse with an appropriate frequency division ratio may be taken out from the frequency division circuit (13) and used.

(G) Effects of the Invention According to the vertical synchronization signal generation circuit of the present invention, the vertical frequency itself or the horizontal synchronization can correspond to various external vertical synchronization signals having different phase relationships with the signal, and moreover, the vertical synchronization It is possible to create an internal vertical synchronization signal that is stable and accurate against signal phase fluctuations. Furthermore, the circuit configuration is relatively simple and can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are signal waveform diagrams for explaining its operation. (1): External vertical synchronization signal input terminal, (8>: Internal vertical synchronization signal output terminal, (12): External horizontal synchronization signal input terminal.

Claims (2)

[Claims] (1) A circuit for creating an internal vertical synchronization signal synchronized with an external vertical synchronization signal, the first and second signals having different phases from each other.
A reference signal is provided, the phase difference between the first and second reference signals and the external vertical synchronization signal is detected, and the external vertical synchronization signal is taken in at the timing of the reference signal with the larger phase difference to perform internal vertical synchronization. A vertical synchronization signal generation circuit that derives it as a signal. (2) Creating a vertical synchronization signal according to claim 1, wherein the first and second reference signals are generated from an oscillation circuit that is PLL controlled using an external horizontal synchronization signal as a reference. circuit.