JPH0644831B2 - Video signal color frame creation device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal color frame creation device that can be used in the field of video equipment such as VTRs, cameras, and video signal generators.

2. Description of the Related Art A sync signal and a color subcarrier of a composite video signal have a constant phase relationship (SCH). For example, in the NTSC signal, as is well known, the phase relationship between the vertical synchronizing signal and the color subcarrier is the same in four fields. This phase relationship is called a color frame. As a synchronizing signal generator for video signals, it is necessary to always maintain a constant SCH when the power is turned on. Also,
When switching multiple video signals or editing with VTR,
The SCH between video signals needs to be continuous. For this purpose, the synchronizing signals of a plurality of video signals must be locked to those of the reference video signal and the SCHs must be the same.
Further, in the editing with the VTR, the servo of the VTR is controlled based on the color frame of the reference video signal, and the signals having the continuity of the color frames are connected to each other, so that there is no screen shift at the editing point. Can be done. Japanese Patent Laid-Open No. 55-86271 discloses a method of always maintaining a constant SCH when the power is turned on and creating a color frame signal according to the SCH. This is to divide a frequency from a reference oscillator to obtain a color frame signal, and further control a frequency divider for forming a color subcarrier based on the color frame signal.

As a method of creating a signal representing the color frame from the reference video signal (NTSC), there is a method shown in FIG. In FIG. 13, 1 is a reference video signal input terminal, 2 is a burst gate, 3 is a sync signal separator, 4 is a horizontal sync signal separator, 5 is a horizontal sync signal separator, 6 is a frame detector, and 7 is a delay. Reference numeral 8 is a PLL, 9 and 10 are latches, and 11 is a color frame signal output terminal. First
FIG. 4 is a diagram showing the waveform of each part in FIG. 13, and FIG. 15 is a diagram showing the phase relationship between the synchronizing signal of the NTSC signal and the color subcarrier and the color frame. In FIG. 13, from the video signal applied to the reference video signal input terminal 1, the composite sync signal 12 is separated by the sync signal separator 3, the horizontal sync signal 13 is separated by the horizontal sync signal separator 4, and the vertical sync signal is separated. Bowl 5
The vertical sync signal 14 is separated by. Composite sync signal 1
2, the frame signal 15 is created by the frame detector 6 from the horizontal synchronizing signal 13 and the vertical synchronizing signal 14. As shown in FIG. 14, the vertical sync signal 14 is latched by the composite sync signal 12 (the vertical sync signal 14 is slightly delayed from the vertical sync signal component in the composite sync signal due to integration or the like in the process of separation). It can be configured by latching the horizontal synchronizing signal 13 with the output. On the other hand, the burst signal is separated from the input video signal of the terminal 1 by the burst gate 2,
A continuous wave 17 synchronized with the burst is created by L8. 13A, 16A, 17A, and 18A of FIG. 14 are enlarged views of the B1 portion and the B3 portion of the signals 13, 16, 17, and 18, respectively. Since the phase relationship between the sync signal of each color field and the color subcarrier is as shown in FIG.
The relationship between the horizontal synchronizing signal and the color subcarrier in the B1 and B3 parts is as shown in 13A and 17A. The signal 16 obtained by delaying the signal 13 by the color subcarrier about 1/4 period delay device 7 (enlarged diagram 16
A), the color subcarrier 17 is latched and the signal 18 (enlarged view 1
8A) is obtained. The color frame signal 19 is obtained at the terminal 11 by latching this signal 18 with the frame signal 15. The color frame signal 19 is the first in the first field.
It rises at serration A1 and the first of the third field
It is a signal that falls at serration A3.

Problems to be Solved by the Invention In the sync signal generator described in Japanese Patent Laid-Open No. 55-86271, it is possible to obtain a sync signal, a color subcarrier, and a color frame signal by dividing the frequency from a reference oscillator. It is not possible to obtain these signals synchronously coupled to the external reference video signal. This is inconvenient when constructing a system synchronized with one reference video signal. In the example of FIG. 13, a color frame signal synchronized with an external reference video signal can be obtained, and the horizontal and vertical synchronization signals separated from the color frame signal and the input reference video signal are
These signals synchronized with the reference video can be obtained by defining the phase when dividing the clock (4 _SC ) having a frequency four times as high as the output of the PLL 8 and creating the sync signal and the color subcarrier. However, the operation of the latch 9 has the following problems. 14A, 16A, 17A, 1
As shown in FIG. 8A, a signal 1 obtained by delaying the horizontal synchronization signal 13
The signal 18 is obtained by latching the color subcarrier 17 at 6. However, in reality, the SCHs of the video signals do not always match as shown in FIG. In such a case, when latching 17A in FIG. 14A, latch timing (rising of 16A) and 17A
There may be a case where it overlaps with the change point of. In this case, the polarity of the latch output 18A is not fixed and the signal 18 oscillates irregularly, so that the sync signal and the color subcarrier generated based on this signal 18 cause phase fluctuations. In addition, the signal 18 is used as a reference for the color frame servo.
Can not be used. From the above points, S
Even if there is a CH relationship, if the signal 18 is stably set to either polarity, a color frame is defined according to the signal 18, color frame servo is performed, and a synchronization signal and a color subcarrier are created to be stable. Can perform various actions.

Means for Solving the Problems The present invention solves the above problems, and in order to create a stable color frame signal, the horizontal synchronizing signal in the input video signal or a part thereof is delayed, and the time is several nanoseconds. First means for extracting the polarities of the color subcarriers of the input video signal with a plurality of signals having a time difference, a frame signal created from a vertical synchronizing signal and a horizontal synchronizing signal, and an input video signal from the output of the first means. The polarity of the extraction output by the minimum delay output and the extraction output by the maximum delay output of the horizontal synchronizing signal or a part thereof in the first means is the same as that of the second means for generating the signal representing the color frame of Only when
It has a third means for transmitting the output of the first means to the second means.

Further, according to the present invention, when the input video signal is not applied, the horizontal synchronizing signal in the first means, which is used for the determination of the coincidence of the output polarities in the third means, or a minimum delayed output thereof is used. The extraction output and the extraction output by the maximum delay output are matched, and the output of the first means is
It has means for fixing the polarity determination of the substantial frequency dividing operation of the second means in a state where it is not regulated.

Action When the timing for latching the color subcarrier coincides with the change point of the color subcarrier as in the above example, neither polarity of the color frame can be determined (the first field and the third field cannot be distinguished). ) Distinguishes the 1st and 3rd fields in creating the sync signal, the color subcarrier and the servo reference signal based on the color frame signal, and keeps the polarity thereafter and does not invert in the middle. Need to

According to the present invention, the output of the first means is the color frame output only when the extraction output of the horizontal synchronizing signal in the first means or a part thereof of the minimum delay output and the extraction output of the maximum delay output match. In such a case, the polarities of the two outputs of the first means do not match and do not affect the generation of the color frame signal. Therefore, the polarity of the color frame decided at the beginning is maintained,
It is possible to obtain a stable color frame signal without inversion in the middle.

Further, in the present invention, when the input reference video signal is not applied, in the third means, the outputs of the first means used for the determination of the coincidence of the output polarities are the same, and the output of the first means is the same. Is in a state in which the polarity determination of the substantial frequency dividing operation of the second means is not regulated, the color frame signal is generated by self-propagation from the frame signal generated from the vertical synchronization signal and the horizontal synchronization signal. When the video signal is applied, the output of the first means immediately coincides with the output of the first means when the reference video signal is not applied.
To determine the polarity of the frame signal when the frame signal is substantially divided by two to generate a correct color frame signal.

EXAMPLE The present invention will be described with reference to FIG. 1 showing an example of the present invention and FIG. In FIGS. 1 and 2, the same reference numerals as those in FIGS. 13 and 14 represent the same items and have the same functions. 71 to 73 are delay devices, 81 is a VCO,
Reference numeral 82 is a frequency divider, 91 to 93 are latches, 100 is a color frame detector, 20 is a matching circuit, and 25 is a signal detector. Similar to FIG. 13, the reference video signal input terminal 1
The composite sync signal 12, the horizontal sync signal 13, and the vertical sync signal 14 are separated from the video signal applied to the frame signal 15 to create a frame signal 15. Further, from the output burst signal of the burst gate 2, a continuous wave of frequency 4 _SC ( _SC : color subcarrier frequency) locked to the output of the VCO 81 by a PLL circuit composed of a VCO 81 and a frequency divider 82 is divided into 4 minutes. A continuous wave of frequency _SC is obtained at the output of the frequency divider 82. FIG. 2 shows the first part in B1 and B3 part of FIG.
It is an enlarged waveform of each part of the figure. The horizontal sync signal 13 is a delay device 7 that is slightly shorter than the 1/4 cycle of the color subcarrier (several nanoseconds).
It is delayed by 1 to obtain the signal 161. The signal 161 is further delayed by the delay devices 72 and 73 for a very short time (several nanoseconds) to obtain the signals 162 and 163. When the SCH of the input reference video signal is exactly matched, the signal 162 is set to be substantially at the center of the change point of the color subcarrier 17.
By latching (91, 92, 93) the color subcarrier 17 with the signals 161, 162, 163, the signals 181, 1
82,183 is obtained. These signals are the input signal SCH
When they match, both fall at the B1 part and B3
This is the signal that rises in the section (Fig. 2 (a)). The signals 181 and 183 at the timings at both ends are guided to the coincidence circuit 20 to obtain the output signal 26. The matching circuit 20 outputs a high level when both input signals match and a low level when they differ. Therefore, an output like 26A in FIG. 2 (a) is obtained, but since this output is a signal that goes to a low level only for a very short period, it always goes to a high level by the integrating circuit consisting of the resistor 21 and the capacitor 22. 23 to one input. Therefore, the gate 23 transmits the signal 182, which is an intermediate timing of the three signals, to the color frame detector 100. The color frame detector operates as follows. The output signal 24 of the gate 23 determines the polarity of the frequency divider that divides the horizontal synchronizing signal 13 by two, and the frame signal 15 is latched by the output of this frequency divider so that the same color as in the case of FIG. The frame signal 19 is obtained at the terminal 11. Here, the reason why the frame signal 15 is not directly latched by the signal 24 is that even if the signal 24 is not present, the frequency-divided output of the horizontal synchronizing signal 13 is always obtained and a stable color frame signal output is obtained.

However, as described above, the SCH of the video signal is not always set accurately, and a part of the latch of the signal 17 by the signals 161, 162, 163 is instantaneously inverted due to the influence of noise and temperature. There is a fear. Signal 1 in Fig. 2 (b)
Waveforms when the rising points of 61, 162 and 163 are near the changing point of the signal 17 will be described, and the manner in which a stable color frame signal is obtained by the present invention will be described. In such a case, output 1 obtained by latching signal 17 with signal 161
The output 183 obtained by latching the signal 17 with 81 and the signal 163 has opposite polarities, and the signal 26 becomes as shown in FIG. 2 (b) 26A. Further, the polarity of the signal 182 obtained by latching the signal 17 with the signal 162 becomes unstable. The signal that passes the signal 26 through the resistor 21 and the capacitor 22 becomes a low level by integration, and the gate 23 does not transmit the signal 182 to the color frame detector 100.
Therefore, the color frame detector 100 uses the horizontal sync signal 1
It operates by a signal obtained by frequency-dividing 3 by 2 and outputs a stable color frame signal 19. If the state shown in FIG. 2 (b) is caused by noise or temperature, the polarity of the output color frame signal is normal when the signals 161, 162, 1
The signal 17 will be latched at 63 and the resulting polarity will be maintained. Also, in order to invert the color frame signal,
Since the outputs of the signals 171, 162, 163 latched by the signal 17 all change from the same state to the same state of the opposite polarity, the time from the rising of the signal 161 to the rising of the signal 163, That is, fluctuations within the range of the sum of the delay amounts of the delay devices 72 and 73 are not affected.

Further, in the present invention, the SCH of the input reference video signal is shown in FIG.
Even when the first field and the third field are in a phase relationship that cannot be distinguished from each other as shown in (b), either polarity can be determined and a stable color frame signal can be output. That is, when the power is turned on, the input to which the resistor 21 and the capacitor 22 of the gate circuit 23 are connected has a high potential until the capacitor 22 is charged through the resistor 21 because the capacitor 22 is connected to the power source. It has become. During this period, the signal 182 is transmitted to the color frame detector 100 through the gate 23. As shown in FIG. 2 (b), the signal 26
Goes low for most of the time, so it goes low to this input of gate 23 when capacitor 22 is charged. The polarity of the color frame signal 19 is determined by the polarity of the signal 182 immediately before the input threshold level of this gate changes from the high level to the low level.
Since this does not transmit, this polarity is maintained stable. At this time,
The determined polarity is determined by latching the signal 17 with the signal 162, and the signal 162 is delayed by 1/4 cycle of the color subcarrier from the original change point of the color subcarrier. Will be the most correct one.

Further, in the present invention, the signal detector 25 detects the presence or absence of the application of the input reference video signal, and when not applied, the latches 91, 92, 93 are forcibly reset, and the output signals 181, 182, thereof are output. 183 is fixed at a low level. By doing so, the output of the coincidence circuit 20 goes high and the gate 23 transmits the signal 182. However, since the signal 182 is always low, the frequency division of the color frame detector 100 is substantially reduced. The polarity determination of the operation is not restricted (for example, the polarity that is substantially divided by two when the signal 24 rises is determined to be a fixed direction).
When the input signal is applied here, the output of the coincidence circuit 20 is already set to the high level from the time when the signal is not applied, so that the signal 182 is immediately sent to the color frame detector 100 through the gate 23. This signal, that is, the signals 161, 162, 1 having three time differences are transmitted.
The color frame is determined by the signal obtained by latching the signal 17 with the signal 162 at the intermediate timing of 63, and the most correct color frame signal is obtained.

In the waveform charts shown in FIGS. 2A and 2B, when the duty of the signal 17 deviates from 50%, the signals 161, 162, 163 are generated.
There is a possibility that the output obtained by latching the signal 17 with the same polarity may be different from the normal one while having the same polarity. In this case, the color frame output signal 19 may not have a regular four-field cycle (inversion every two fields). In such a case, the duty is discriminated from the color frame signal 19 (the duty is 5 when the signal is passed through the integrating circuit.
When it is 0%, the central DC potential is obtained, and when it falls to either side, this DC rises or falls.
If it deviates from C, it can be determined that the duty has deviated),
When the duty is deviated, the transmission of the signal 182 is prohibited to allow the color frame detector 100 to run by itself.
A stable color frame output can be obtained.

Further, by setting the duty of the signal 17 to be slightly longer in the low level period than in the high level period, the latching of the signal 17 by the signals 161, 162, 163 is made a second value.
Even when the latch output has the same polarity and the signal 182 is transmitted at a delicate time as in the case of FIG. 6B, the signal 182 is at a low level because the signal 17 has a low low level period, and the frame detector 100 is substantially A stable color frame signal 19 can be obtained because the polarity determination of the dynamic frequency division operation is not restricted.

FIG. 3 shows another embodiment of the color frame detector 100, and FIG. 4 shows the waveform of each part. The same numbers as in FIGS. 1 and 2 represent the same items. Reference numeral 27 is a latch and 28 is a frequency divider. Latch signal 24 with frame signal 15 (27)
Signal 29 is obtained. At the rising edge of signal 29, signal 1
A color frame signal 19 is obtained by determining the polarity of dividing 9 by 28 (28). Also in this example, when the signal 182 is not transmitted and the signal 24 is at a low level, the signal 29 is always at a low level, and the frequency divider 28 divides the signal 15 by free running to obtain a stable color frame signal 19. Is obtained. The operation when the power is turned on and when a signal is applied is also as described above. When the cycle of the signal 19 becomes irregular, the signal 182 is prohibited and the signal 24 is fixed at a low level, or the duty of the signal 17 is set to a low level for a long period, and the signal 24 is at a low level when unstable. It is also similar to the above that the output is stabilized by preventing the rising edge of the signal 29 from appearing outside the normal position by setting it to the side.

FIG. 5 shows another embodiment of the present invention, and FIG. 6 shows the waveform of each part thereof. The same numbers as in FIGS. 1 and 2 represent the same items. FIG. 6 (b) is an enlarged view of each part. The difference from the example of FIG. 1 is that when the polarity of the color subcarrier 17 is extracted by the latches 91, 92, 93, the frame signal 15 is temporarily latched (30) by the signal 161 obtained by delaying the horizontal synchronizing signal by the delay device 71. Signal 164 and the delay device 72,
The point is that the signals 165 and 166 delayed by 73 are used. By doing so, the signals 164, 165,
166 is a signal that rises once every two fields (in odd fields), and the output signals 184, 185, 186 of the latches 91, 92, 93 are signals that distinguish the first and third fields. These signals 184 and 186 are led to the coincidence circuit 20, further led to one of the gates 23 through the resistor 21 and the capacitor 22, and the signal 1 is fed to the other input of the gate 23.
By introducing 85, the signal 185 is transmitted to the color frame detector 100 only when the polarities of the signal 17 extracted by the signal 164 and the signal 166 are the same, and the stable color frame signal 19 can be obtained as in the previous example. . Note that the color frame detector 100 in this example uses the signal 24
The polarity for simply dividing the frame signal 15 by two may be determined by (for example, rising). In FIG. 5, the latch 30 and the delay device 71 are reversed so that the horizontal synchronizing signal 1
First, the frame signal 15 is latched by 3 and then the delay device 71
It is exactly the same even if delayed by. In addition, the horizontal sync signal
The signals obtained by latching the frame signal 15 with the signals delayed by the two delay devices 71, 72, 73 are signal 164, 16 respectively.
It can also be used in place of 5,166.

As a modification of FIG. 5, there is a method in which the signal latched by the horizontal synchronizing signal 15 in the latch 30 is a color frame signal 19 instead of the frame signal 15. FIG. 7 is a block diagram of the main part of this example, and FIG. 8 shows the waveform of each part, which will be described. In FIG. 7, the same parts as in FIG. 5 are omitted. FIG. 8 (a) shows the operation when the correct color frame output is output, and FIG. 8 (b) shows the operation that is correct when the output is incorrect. When a correct color frame signal is obtained as indicated by 19 in FIG. 8 (a), the output 164 of the latch 30 is output.
Is a signal that rises in the first field and falls in the third field. At the rising edges of this signal 164 and delayed signals 165 and 166, the color subcarrier 17
Is latched, its outputs 184, 185, 186 are always low. Therefore, the signal 24 becomes low level,
The signal 166 is blocked by the gate 31 and the signal 32 becomes low level and is not transmitted to the color frame detector 100. Therefore, the color frame signal 19 maintains this correct state.

Next, as shown in FIG. 8 (b), the color frame output signal 19
The correction operation in the case where is incorrect will be described. Latch 30
The output 164 of 1 falls in the vicinity of the first field B1 and rises in the vicinity of the third field B3. This signal 1
When the color subcarrier 17 is latched at the rising edges of 64 and delayed signals 165 and 166, its output 18
4, 185 and 186 are always high level. Therefore, the signal 24 becomes high level, the gate 31 transmits the signal 166 (signal 32), and the rising edge thereof determines the polarity of division of the signal 15 by the color frame detector 100 (signal 3).
By setting so that the signal 19 becomes low level at the rising edge of 2, the signal 19 is inverted at this point and has the correct polarity, and thereafter, the same state as in FIG. 8 (a) is maintained and this state is maintained. . This operation corresponds to the color frame output (signal 1
9) and signals related to the sync signal (signals 164, 16
5, 166), the output signal (Signal 1
84, 185, 186) is equivalent to defining the frequency division polarity of the color frame detector 100.

In this example, the other operations are exactly the same as the previous example.

The above description mainly deals with the NTSC signal.
As for the signal, since the color frame has a period of 8 fields, some changes are necessary. FIG. 9 shows the essential parts of an embodiment in which the embodiment of FIG. 5 is applied to PAL, and FIG. 10 shows the waveforms of the respective parts. In FIG. 9, 33
Is a latch, 34 is a PAL pulse, and others are the same as in FIG. In the PAL signal, the modulation phase of the RY signal is inverted line by line. The signal indicating the polarity of this modulation axis is PA
It is called L pulse. That is, the PAL pulse is a signal with a cycle of two lines, and one frame has 625 lines (P
Since the ALM is 525 lines), the polarity of the PAL pulse for each frame (2 fields) is inverted. Tenth
FIG. 34 shows a PAL pulse. Therefore, the frame signal 1
By latching (33) the PAL pulse 34 at 5, for example, a 2-frame signal 35 that rises in the first field and falls in the third field is obtained. This signal 3
5 is latched with a signal 161 obtained by delaying the horizontal synchronizing signal (3
0) to obtain the signal 164. The signals 184, 185, 186 are obtained by latching the color subcarrier 17 with the signal 164 and the delayed signal 165.166. These signals are, for example, signals that fall in the first field and rise in the fifth field. Thereafter, the color frame signal 19 is obtained by the same operation as that in FIG. 5 (the cycle is half of that in FIG. 5). The signal 19 is, for example, a signal with an 8-field period that rises in the first field and falls in the fifth field.

To apply the embodiment of FIG. 7 to PAL, use signal 19 instead of signal 35 directed to latch 30 in FIG. 9 (see FIG. 7 for latch 33, PAL pulse 3 in FIG. 9).
4 Add the operation according to 4) Good. At this time, the operation is performed at a half cycle of FIG. 7, and a color frame signal is obtained in the same manner.

Furthermore, the present invention can be configured to include a synchronization signal generator. An embodiment at this time will be described with reference to FIG. In FIG. 11, the same numbers as those in FIGS. 1 and 2 represent the same items. 200 is the same as the block shown at 200 in FIG. 36 is a 455 frequency divider, 37 is a latch, 38 is a gate, 39 is a 2 frequency divider, 40 is a 525 frequency divider, 41 is a composite sync signal generator, 60 is a frame detector, 101 is a color frame detector. is there. VCO81
The output 4 _SC signal is divided by 455 (36) to obtain a 2 _H signal, and further divided by 2 (39) to obtain a horizontal synchronizing signal 42. At the time of this frequency division, the horizontal synchronization signal 13 is extracted by the gate 38 once in every four fields by the color frame signal 190 generated from the output of the synchronization signal generator, and the signal is latched by the color subcarrier 17. By resetting, it is possible to always obtain a sync signal and a color subcarrier in which the color frame coincides with the external reference signal. The 2 _H signal is divided by 525 (40) to obtain the vertical synchronizing signal 44. At this time, the position is determined by the vertical synchronizing signal 14 of the external reference signal. A composite sync signal 43 is created (41) from the 2 _H signal, the horizontal sync signal 42, and the vertical sync signal 44. Further, similarly to the case of FIG. 1, a frame signal 45 is generated by the frame detector 60 from the horizontal synchronizing signal 42, the composite synchronizing signal 43, and the vertical synchronizing signal 44, and the frame signal 45, the horizontal synchronizing signal 42, and the block 200 are created. The color frame signal 190 is created by the color frame detector 101 from the signal 24 thus generated.

FIG. 12 shows an embodiment in which the synchronization signal generator is included in the embodiment of FIG. The numbers in FIG. 12 represent the same as in the above example. Reference numeral 300 is a block 300 in FIG. 5, and reference numeral 400 is a block 400 in FIG. In the embodiment of FIG. 5, the frame signal 1 of the input reference video signal is set by the latch 30 in the block 300.
5 is latched by the output signal 161 of the delay device 71, the signal 161 is latched by the sync signal generator output frame signal 45 in the embodiment of FIG. Other actions are
This is similar to FIG. 5 block 300 and FIG. 11 block 400.

As a modification of FIG. 12, a signal 190 may be used in place of the signal 45 to the latch 30, and a gate 31 may be used as shown in FIG. As for the PAL signal, the structure shown in FIG. 9 and the structure using the color frame signal 190 for the latch 30 can be adopted.

With the configuration including the sync signal generator, when the external reference video signal is not applied, the sync signal, color subcarrier, and
Generates frame signals, color frame signals, etc., and
When the power is turned on, a signal in which the phase relationship of these signals is always maintained (SCH is maintained) is obtained, and color frame servo or the like is performed using this output signal to perform continuous editing of color frames. be able to.

EFFECTS OF THE INVENTION According to the present invention, a color frame signal that matches an external reference video signal can be stably obtained, and the most correct color frame signal can always be obtained even when the reference video signal is applied and the power is turned on. By adopting a configuration that includes a sync signal generator, it is possible to stably generate sync signals, color subcarriers, frame signals, color frame signals, etc., which are synchronously coupled to an external reference video signal, and a reference video signal. When no signal is applied, these signals can be generated by self-propagation, and can be used for color frame editing or the like to minimize the image shift at the editing point.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a detailed block diagram of the color frame detector of FIG. 1. FIG. 4 is a waveform diagram of each part of FIG. 3, FIG. 5, FIG. 7, FIG. 9, FIG. , FIG. 12 is a block diagram showing another embodiment of the present invention or its essential part, FIG.
FIGS. 8 and 10 are waveform diagrams of respective parts of FIGS. 5, 7, and 9, respectively, FIG. 13 is a block diagram of a conventional example, FIG. 14 is a waveform diagram of respective parts of FIG. 13, and FIG. FIG. 4 is a phase relationship diagram of a sync signal of an NTSC signal and a color subcarrier. 3 ... Sync signal separator, 4 ... Horizontal sync signal separator, 5
... vertical sync signal separator, 71, 72, 73 ... delay device, 30, 91, 92, 93 ... latch, 20 ... matching circuit, 23 ... gate, 100, 101 ... color frame detector, 6 ... Frame detector, 25 ... Signal detector.

Claims (12)

[Claims] 1. A first means for extracting the polarity of a color subcarrier of an input video signal with a plurality of signals having a time difference of several nanoseconds, which is obtained by delaying a horizontal synchronizing signal or a part thereof in the input video signal. A frame signal generated from the vertical synchronizing signal and the horizontal synchronizing signal, second means for generating a signal representing a color frame of the input video signal from the output of the first means, and the input video signal is applied for the first time. When the polarity of the extraction output by the minimum delay output and the extraction output by the maximum delay output of the horizontal synchronizing signal in the first means or a part thereof is the same except when the power is turned on and when the power is turned on. A video signal color frame creation device comprising: a third means for transmitting the output of the first means to the second means. 2. The horizontal synchronizing signal in the first means, or a part of the horizontal synchronizing signal in the first means, which is used for determining the coincidence of the output polarities in the third means when the input video signal is first applied or when the power is turned on. There is provided means for transmitting to the second means an output obtained by extracting the polarity of the color subcarrier of the input video signal with the horizontal synchronizing signal having a timing between the minimum delay output and the maximum delay output or a delayed output signal of a part thereof. The video signal color frame creation device according to claim 1, wherein 3. The second means outputs the output of the first means,
2. The video signal color frame creation device according to claim 1, further comprising defining a polarity when substantially dividing a frame signal created from a vertical sync signal and a horizontal sync signal. 4. A second means is a color frame output and a first means.
2. The output of the means of claim 1 is compared to define the polarity when the frame signal generated from the vertical synchronizing signal and the horizontal synchronizing signal is substantially divided. The video signal color frame creation device described in. 5. The method according to claim 1, wherein the transmission of the output of the first means to the second means is prohibited when the color frame signal output is different from the regular repetition cycle.
The video signal color frame creation device according to the item. 6. The first means comprises means for latching a color subcarrier by a horizontal synchronizing signal in an input video signal or a signal obtained by delaying a part of the horizontal synchronizing signal, and the duty ratio of the color subcarrier is 5
The video signal color frame creation device according to claim 1, wherein the setting is performed by shifting from 0%. 7. A first means for extracting the polarity of a color subcarrier of an input video signal by a plurality of signals having a time difference of several nanoseconds, which is obtained by delaying a horizontal synchronizing signal in the input video signal or a part thereof. A frame signal generated from the vertical synchronizing signal and the horizontal synchronizing signal, second means for generating a signal representing a color frame of the input video signal from the output of the first means, and the input video signal is applied for the first time. When the polarity of the extraction output by the minimum delay output and the extraction output by the maximum delay output of the horizontal synchronizing signal in the first means or a part thereof is the same except when the power is turned on and when the power is turned on. The third means for transmitting the output of the first means to the second means, and the first means used for determining the coincidence of the output polarities in the third means when the input video signal is not applied. The extraction output by the minimum delay output and the extraction output by the maximum delay output of the horizontal synchronization signal or a part of the horizontal synchronization signal in the means, and the output of the first means is the polarity of the frequency dividing operation of the second means. An image signal color frame creation device comprising means for fixing a decision so as not to be restricted. 8. A horizontal synchronizing signal in the first means or a part of the horizontal synchronizing signal in the first means, which is used for determining the coincidence of output polarities in the third means when the input video signal is first applied or when the power is turned on. There is provided means for transmitting to the second means an output obtained by extracting the polarity of the color subcarrier of the input video signal with the horizontal synchronizing signal having a timing between the minimum delay output and the maximum delay output or a delayed output signal of a part thereof. The video signal color frame creation device according to claim 7, characterized in that. 9. The second means outputs the first means,
8. The video signal color frame creating device according to claim 7, further comprising defining a polarity when substantially dividing a frame signal created from the vertical synchronizing signal and the horizontal synchronizing signal. 10. The second means uses the output obtained by comparing the output of the color frame and the output of the first means to determine the polarity when substantially dividing the frame signal generated from the vertical synchronizing signal and the horizontal synchronizing signal. The video signal color frame creation device according to claim 7, wherein the video signal color frame creation device comprises: 11. The method according to claim 7, wherein the transmission of the output of the first means to the second means is prohibited when the color frame signal output is different from the regular repetition cycle. The video signal color frame creation device described in. 12. The first means comprises means for latching a color subcarrier with a horizontal synchronizing signal in an input video signal or a signal obtained by delaying a part of the horizontal synchronizing signal, and shifting the duty ratio of the color subcarrier from 50%. The video signal color frame creation device according to claim 7, wherein the setting is performed.