KR100219516B1 - Pll for horizontal synchronous signals - Google Patents

Abstract

A phase locked loop for a horizontal sync signal is disclosed. This phase-locked loop having a phase comparator and a divider has a horizontal sync separated from a self-oscillating sync signal or a composite sync signal divided from a predetermined clock in response to a sync detection signal indicating whether a composite sync signal has been detected from the composite video signal. A horizontal synchronization signal compensation means for selectively outputting a signal, a vertical synchronization signal separation means for separating the external vertical synchronization signal from the composite synchronization signal, and a reset in response to the external vertical synchronization signal, and counting the number of horizontal synchronization signals to track the field And a phase-locked loop reset signal generating means for outputting a phase comparator and a first reset signal for resetting the frequency divider in a section in which a pulse occurs, wherein the phase-locked loop is a horizontal signal as a reference signal when the phase-locked loop is reset. The output of the signal compensation circuit and the phase of the comparison signal It is effective to prevent.

Description

Phase-locked loop for horizontal sync signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL), and more particularly, to a phase locked loop for a horizontal synchronization signal embedded in an on screen display (OSD) circuit.

The phase-locked loop for the horizontal sync signal included in the conventional OSD circuit is composed of an input compensation circuit stage, a phase comparator, a voltage controlled oscillator and a 32 divider.

The input compensation stage circuit inputs a horizontal sync signal extracted from a composite video signal in an external mode in which the output of a sync detector (not shown) is high level, so that the frequency tracking operation is performed only for an input edge of 890 divisions or more of 4FSC (14.31818 MHz) for NTSC By outputting, the equalizing pulse of 0.5H (where H is the horizontal synchronizing signal) period, the serrated vertical pulse and the reference signal from which the noise is removed are output to the phase comparator. Here, FSC is the color carrier frequency of the video signal, which is 3.579545 MHz. The phase comparator phase compares the input reference signal with a comparison signal which is a 32-division output signal of the voltage controlled oscillator, and outputs the compared result. The voltage controlled oscillator oscillates frequency in accordance with the changed voltage to perform the operation of the phase locked loop.

However, the input compensation stage circuit does not need to perform a phase locked loop operation on the input signal in the case of an internal mode in which the output of the sync detector is low level, and generates an oscillation signal divided by 4FSC by 910 to generate a reference for the phase locked loop. Output as a signal to the phase-lock loop. Therefore, the frequency of the signal output from the voltage controlled oscillator can maintain a state of 15.73426 KHz.

However, in the above-described conventional phase synchronization loop for horizontal synchronization signals, when a synchronization signal is used as an input when driving a video tape, a field tracking pulse is generated and the period is shifted once so that the phase synchronization loop is locked for a long time. This takes This locking speed may be faster by changing an external application, but there is an undesirable problem because the locking speed may be sensitive to noise during a weak electric field.

An object of the present invention is to provide a phase lock loop for a horizontal lock signal for resetting a phase comparator and a divider of a phase lock loop in a section in which a field tracking pulse is generated by using an output of a horizontal lock signal compensation circuit.

1 is a block diagram of a phase locked loop for a horizontal sync signal according to the present invention.

2 is a block diagram of a preferred embodiment of the present invention of the PLL reset signal generator shown in FIG. 1.

3A to 3K are waveform diagrams of respective parts shown in FIGS. 1 and 2.

4 is a circuit diagram of a preferred embodiment of the present invention according to the present invention.

In order to achieve the above object, a phase synchronization loop for a horizontal synchronization signal according to the present invention having a phase comparator and a divider is divided in frequency from a predetermined clock in response to a synchronization detection signal indicating whether a composite synchronization signal is detected from a composite video signal. Horizontal synchronization signal compensation means for selectively outputting an oscillation synchronization signal or a horizontal synchronization signal separated from the composite synchronization signal, vertical synchronization signal separation means for separating an external vertical synchronization signal from the composite synchronization signal, and the external vertical synchronization signal. And a phase locked loop reset signal generating means for counting the number of the horizontal sync signals and outputting a first reset signal for resetting the phase comparator and the divider in a section in which a field tracking pulse is generated. desirable.

Hereinafter, a configuration and an operation of a phase locked loop for a horizontal sync signal according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a phase synchronization loop for a horizontal synchronization signal according to the present invention, wherein the horizontal synchronization signal compensator 10, the vertical synchronization signal separator 20, the PLL reset signal generator 30, and the logical product 32 And a logical sum 34.

The horizontal synchronizing signal compensator 10 shown in FIG. 1 inputs the composite synchronizing signal CSY separated from the composite image signal and the synchronizing detection signal SYD which is an output of the synchronizing detector (not shown), so that the SYD is at a high level. In this case, the horizontal synchronizing signal is separated from the composite synchronizing signal, and the separated horizontal synchronizing signal COMP is output. However, when SYD is at a low level, the horizontal synchronizing signal compensator 10 generates a self-oscillating synchronizing signal divided by 4910 (14.31818 MHz in the case of NTSC) 910 and outputs it to the logical sum 34. Detailed operation thereof is disclosed in the patent application filed by the Applicant on October 18, 1996, entitled 'Digital Phase Locked Loop for Horizontal Sync Signal'. Here, the synchronization detection signal is output from the synchronization detector as a signal indicating whether or not the composite synchronization signal is detected from the composite video signal.

Meanwhile, the vertical synchronizing signal separator 20 separates only the vertical synchronizing signal from the composite synchronizing signal CSY and outputs the external synchronizing signal EVSY. The PLL reset signal generator 30 is reset in response to an external vertical synchronizing signal, and outputs a reset signal for resetting the phase comparator and the divider of the phase synchronizing loop through the output terminal OUT1, and the horizontal synchronizing signal COMP. An enable signal (EN) for enabling is generated and output as the logical product (32). Therefore, when SYD is high level and the enable signal is high level, the horizontal synchronizing signal COMP is input to the logical sum 34, and when SYD is low level, the oscillating synchronizing signal is often input to the logical sum 34 to output the output terminal OUT2. It is output as a reference signal of the phase locked loop.

FIG. 2 is a block diagram of a preferred embodiment of the PLL reset signal generator 30 shown in FIG. 1 according to the present invention, and includes a counter 40, a counter reset signal generator 42, a decoder 44, and a reset signal. It consists of a generator 46 and an enable signal generator 48.

3A to 3K are waveform diagrams of respective parts shown in FIGS. 1 and 2, and FIG. 3C is a waveform diagram of a composite synchronization signal.

The counter reset signal generator 42 shown in FIG. 2 detects the low level of the external vertical synchronization signal EVSY shown in FIG. 3B, and detects the low level of the external vertical synchronization signal EVSY shown in FIG. The counter reset signal is generated during one period of the falling edge of the horizontal synchronization signal COMP. The counter 40 may be implemented as a 9-bit synchronous counter. The counter 40 may be reset in response to the counter reset signal output from the counter reset signal generator 42 and output from the horizontal sync signal compensator 10. ), The number of horizontal synchronization signals is counted, and the counted value shown in (e) of FIG. 3 is output to the decoder 44. The decoder 44 sets a section in which the PLL reset signal shown in FIG. 3 (f) for resetting the phase comparator and the divider is generated, that is, a section in which the field tracking pulse is generated. To this end, the decoder 44 generates the low level PLL reset signal shown in FIG. 3F when the counted value shown in FIG. 3E output from the counter 40 is 250. FIG. Where 250 is for NTSC (262.5H / 1field). The time point when the PLL reset signal becomes a high level is when the counter 40 is reset by the falling edge of the external vertical synchronization signal shown in FIG. 3B, and then counts five horizontal synchronization signals.

The reset signal generator 46 generates a PLL reset signal by synchronizing the output values of D_250 and D_5 generated by the decoder 44 with the rising edge of the horizontal synchronizing signal COMP. The phase comparator (not shown) of the phase-locked loop according to the present invention includes the reference signal shown in FIG. 3 (h) output through the output terminal OUT2 shown in FIG. 1 and the comparison signal shown in FIG. Since the rising edge of is compared, the time point at which the reset is released must be the rising edge of the horizontal synchronization signal COMP, which is a reference signal. Therefore, when the frequency divider of the phase locked loop is reset, the rising edge of the horizontal reference signal COMP, which is the next reference signal, coincides with the rising edge of the divided signal, thereby preventing phase shift. The PLL reset signal is generated only when the SYD shown in FIG. This makes it work.

On the other hand, the enable signal generator 48 generates the PLL reset signal shown in FIG. 3 (f), and then the horizontal synchronization signal COMP, which is the reference signal shown in FIG. By preventing the signal from being operated as a reference signal, the enable signal shown in FIG. 3 (g) is generated to prevent the edge of the reference signal from occurring when the PLL reset signal is released. Therefore, when the enable signal shown in Fig. 3G is brought to the low level by bringing the PLL reset signal at the falling edge of the horizontal synchronizing signal COMP, the horizontal synchronizing signal COMP is disabled in the interval.

FIG. 4 is a circuit diagram of a preferred embodiment of the PLL reset signal generator 30 shown in FIG. 2 according to the present invention. The inverters 72 and 74 constituting the counter 60 and the counter reset signal generator 70 are shown in FIG. And 76), D flip-flop 82, AND 78, AND 80, and inverted AND 92, 94, 96, and 98 and the inverted OR 100 and 102 constituting the decoder 90. ), The J / K flip-flop 112 and the logical product 114 and the logical sum 116 constituting the reset signal generator 110, the inverter 122 and the D flip constituting the enable signal generator 120. It consists of a flop 124.

The reset signal RESET is a power reset. When the reset signal RESET is at a high level, the reset signal RESET is reset by initializing the D flip-flop 82 and the counter 60. The negative output QN of the D flip-flop 82 is initially at a high level. When the external vertical synchronizing signal EVSY is at a low level, the outputs of the inverter 72 and the logical product 78 are at a high level. ) Output goes low. This resets the counter 60. After the counter 60 is reset, the negative output of the D flip-flop 82 becomes low at the falling edge of the horizontal synchronizing signal COMP, so that the counter 60 is reset and the counter 60 is reset. The counter starts at the rising edge of the horizontal synchronizing signal COMP. Therefore, the 9-bit synchronous counter 60 counts the number of horizontal sync signals from the edge of the external vertical sync signal EVSY.

The decoder 90 uses WQ8: 0 and WQB8: 0, which are outputs of the counter 60, to the decoder 5 D_5 and the inverse AND ( 96 and 98) and a decoder 250 (D_250) by the inverted AND 100.

When the number of horizontal sync signals reaches 250, the reset signal generator 110 resets the J / K flip-flop 112 at the 251 th horizontal sync signal and outputs the negative output (QN) of the J / K flip-flop 112. FIG. ) Becomes the high level, and the PLL reset signal is disabled. When a reset signal is applied to a phase comparator (not shown) of the PLL, a high impedance state is obtained. When a divider is reset, the output is a high level state. Therefore, since there is no voltage change in the voltage controlled oscillator while the PLL reset signal outputted through the output terminal OUT1 is applied, the 32 frequency division is performed at the locked voltage controlled oscillator frequency at the point where the PLL reset signal is released.

The enable signal generation unit 120 performs horizontal synchronization to prevent the rising edge of the horizontal synchronization signal COMP from being input to the phase comparator as the PLL reference signal shown in FIG. 3H when the PLL reset signal is released. This can be obtained by taking the PLL reset signal at the falling edge of the signal COMP. Therefore, after the PLL phase comparator and the divider are reset, the phase shift can be prevented by performing a phase comparison at the rising edge of the next PLL reference signal, the horizontal synchronization signal COMP and the divider output.

As described above, the phase synchronization loop for the horizontal synchronization signal according to the present invention has an effect of preventing the phase of the output signal and the comparison signal from the horizontal synchronization signal compensation circuit, which is a reference signal, out of phase when the phase synchronization loop is reset.

Claims (4)

In a phase locked loop for a horizontal locked signal having a phase comparator and a divider, Horizontal synchronizing signal compensating means for selectively outputting a self-oscillating synchronizing signal divided from a predetermined clock or a horizontal synchronizing signal separated from the composite synchronizing signal in response to a synchronizing detection signal indicating whether a composite synchronizing signal is detected from the composite image signal; Vertical synchronization signal separation means for separating an external vertical synchronization signal from the composite synchronization signal; And A phase locked loop reset signal which is reset in response to the external vertical sync signal and outputs a first reset signal for resetting the phase comparator and the divider in a section in which a field tracking pulse is generated by counting the number of the horizontal sync signals; And a generating means. A phase locked loop for a horizontal synchronizing signal. 2. The apparatus of claim 1, wherein the phase locked loop reset signal generating means Counter reset signal generating means for generating a second reset signal during a predetermined period of the horizontal synchronization signal in response to the external vertical synchronization signal; Counting means reset by the second reset signal and counting the clock signal by counting the horizontal synchronization signal; Decoding means for setting a section in which the field tracking pulse occurs in response to the counted value; And And reset signal generating means for outputting said first reset signal during said period in response to said horizontal synchronizing signal. The phase lock loop of claim 1, wherein the phase lock loop for the horizontal lock signal is Logical AND of the enable signal and the horizontal synchronizing signal output from the horizontal synchronizing signal compensation means; And And a logical sum of the logical product and the self-oscillating synchronization signal and outputting the logical sum to the phase comparator as a reference signal. And the enable signal is generated from the phase-locked loop reset signal generator in response to the first reset signal. 4. The apparatus of claim 2 or 3, wherein the phase locked loop reset signal generating means And an enable signal generating means for outputting the enable signal at an edge of the horizontal synchronization signal in response to the first reset signal.

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