JPS5930371A - Synchronizing signal processing circuit - Google Patents

Abstract

PURPOSE:To detect surely a vertical synchronizing pulse, when the pulse width is deviated from the TV standards, by taking a pulse of a timing delayed for a prescribed time from a start timing of each synchronizing pulse of a composite synchronizing signal as a sampling pulse and holding an input signal. CONSTITUTION:A synchronizing signal processing circuit consists of a pulse generating circuit 1 and a sample-and-hold circuit 3, and the circuit 1 is provided with an oscillator 9, an AND gate 8, a counter 10, a decoder 11 and an FF7. The composite video signal is inputted to an input terminal of the circuit, and a pulse is generated from the circuit 1 in the timing delayed by a time Ts [H/2<Ts<(H/2+E)] from the start timing of each synchronizing pulse of the synchronizing signal, where H is a horizontal scanning period of the synchronizing signal when E is the equalizing pulse width. This pulse is applied to the circuit 3 as a sampling pulse, the synchronizing signal from a terminal 2 is held at the circuit 3, an equalizing pulse and a vertical synchronizing pulse are detected and outputted from the circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to means for detecting an equalization pulse period and a vertical synchronization pulse period from a composite synchronization signal of a television.

Conventional configuration and its problems Various methods have been devised and put into practical use for detecting equalization pulses and vertical synchronization pulses. These methods can be roughly divided into two methods. The first method is to use an integrating circuit,
The second method is to determine the difference in pulse width of the horizontal synchronization pulse, equalization pulse, and vertical synchronization pulse.

However, the first method has the disadvantage that in principle a delay determined by a time constant occurs in the output, and it is difficult to detect the equalization pulse.

In addition, the second method is to reduce the delay time of the detection output to 3.
It can be made compact, can be configured with digital circuits, and is suitable for IC implementation. However, the pulse width of the equalization pulse is narrower than that of the horizontal sync pulse, and the difference is approximately 2
．． Since the pulse width of the equalization pulse is as small as 4μsec, if the pulse width of the equalization pulse is widened by about 1.2μ, or if the pulse width of the horizontal synchronization pulse is narrowed by about 1.2μ, the equalization pulse and horizontal synchronization can be changed. It is difficult to distinguish it from pulses, resulting in erroneous judgments.

If you input a composite sync signal that may have a pulse width 1 to 2 microns wider than the television standard pulse width, such as the composite sync signal obtained by playing a VTR, especially a dubbed tape, etc. This method has the problem of erroneously determining whether it is a horizontal synchronization pulse or a horizontal synchronization pulse.

OBJECT OF THE INVENTION An object of the present invention is to reliably detect the periods of equalization pulses and vertical synchronization pulses from the composite synchronization signal even if the pulse width of each synchronization pulse of the composite synchronization signal deviates from the television standard. do.

Structure of the Invention In the composite synchronization signal, horizontal synchronization pulses are arranged at intervals of horizontal scanning period H, and equalization pulses and vertical nkPI period pulses are arranged at intervals of 0.6H. Further, the start timing of the equalization pulse and the vertical synchronization pulse is located at a position that is an integral multiple of 0.5 H from the start timing of the horizontal synchronization pulse. Based on the properties of this composite synchronization signal, the present invention determines whether there is an equalization pulse or a vertical synchronization pulse at a position 0.5H away from the start timing of each synchronization pulse in the composite synchronization signal. Detecting the period of sync pulse. Since the pulse width of the vertical synchronization pulse is sufficiently wider than the equalization pulse, the presence or absence of the equalization pulse and vertical synchronization pulse can be determined at the start timing of each synchronization pulse in the composite synchronization signal, when the equalization pulse width is E. The composite synchronization signal may be sampled at a timing delayed by the time Ts obtained by adding W to Equation (1).

DESCRIPTION OF THE EMBODIMENTS Page 6 FIG. 1 shows the basic configuration of the present invention. The pulse generating circuit 1 detects the start timing of each synchronizing pulse in the composite synchronizing signal applied to the terminal 2, and outputs a sampling pulse after a time TB. Sample and hold circuit 3
reads the composite synchronizing signal input using the output of the pulse generating circuit 1 as a sampling pulse. This sample and
The output of the hold circuit 3 is the detection output of the equalization pulse and vertical synchronization pulse periods.

FIG. 2 shows an example of its operating waveforms. A is the waveform of the composite synchronization signal of the odd field, D is the waveform of the even field, and 4
indicates the horizontal synchronizing signal, 6 indicates the equalization pulse, and 6 indicates the vertical synchronizing pulse. OB and E indicate the pulse generation circuit 1.
In this example, C2F is the output of the sample-and-hold circuit 3. If you look at No. 2 and F in Figure 2, the time delay for equalization pulse and vertical synchronization pulse detection in even fields is small, but if you look at A and C, the equalization pulse and vertical synchronization pulse detection in odd fields is 0.5H. It can be seen that a time delay occurs. However, the time delay of 0.5H for 6 pages does not pose a practical problem. A.

D is a synchronization signal in the case of the NTSC system, but it can also be applied to the PAL system and SECAM system.

FIG. 3 shows a specific embodiment of the present invention. The pulse generation circuit 1 includes a digital monostable multivibrator and a decoder that decodes the state of the counter of the digital monostable multivibrator and generates a sampled pulse output. In addition, sample and hold circuit 3
consists of flip-flops. The digital monostable multivibrator is triggered at the start timing of each synchronization pulse of the composite synchronization signal, and outputs a pulse with a time width of 1w0 that satisfies the following equation (2).

T8≦TW H・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・(2) Because time Ts
In order to detect T8≦Tw, it is sufficient that Tw<H since each synchronization pulse does not come after time TII until time H. Of course, if the time "w" is not required, Tw=Ts may be used, which simplifies the circuit configuration.

The operation shown in FIG. 3 will be explained. The flip-flop on page 77 is the start timing of the synchronization pulse, that is, the rising edge.
It will be set twice. Furi Ruff “Flop completion output Q”
, the AND gate 8 opens and the oscillator 9 (o in Fig. 3) opens.
A clock from the counter 10 (abbreviated as SC) begins to be input to the counter 10. Decoder 11 decodes the state of the counter and generates timing pulses. The output α of the decoder is the detection output at time TW and resets the flip-flop 7. AND gate 8 by the Q output of flip-flop 7
is closed, and the 0 output of flip-flop 7 causes counter 1
0 is reset to complete the operation of the digital monostable multivibrator. The decoder output β is a detection output of the time TSs, that is, the sampling timing. The sample-and-hold circuit 3, that is, the flip 70 tube 12 reads the composite synchronization signal using the decoder output β as a sampling pulse.

FIG. 4 shows operating waveforms of the circuit example shown in FIG. 3. As shown in Figure 4A, even if the width of each synchronization pulse in the composite synchronization signal becomes narrow as shown by the broken line or wide as shown by the dotted line, the equalization pulse and vertical synchronization are reliably maintained. It is easy to see that the duration of the pulse can be detected.

In addition, B in FIG. 4 is the Q output of the flip-flop 7, and C
is the output of the gate 8, D is the output a of the decoder 11, E is the output β of the decoder 11, F is the output of the knob flop 12, and the output of the flip-flop 12 determines the equalization pulse period and the vertical synchronization signal. This output is obtained by detecting the period and the horizontal synchronization signal period.

The pulse generation circuit 1 in this embodiment operates as a horizontal synchronization signal separation circuit that removes equalization pulses and vertical synchronization signals, as can be seen from the operating waveform in FIG. Conversely, by adding one decoder and one 7-trip loop to the horizontal synchronization signal separation circuit, an equalization pulse and vertical synchronization pulse period detection circuit can be realized with a simple configuration. Furthermore, this configuration has the advantage of being suitable for IC implementation because it can be realized using only digital circuits.

The above was 9 pages for the case where there is no phase fluctuation of the composite synchronization signal, but even with a composite synchronization signal with phase fluctuation, by controlling the oscillation frequency of the oscillator 9 in Fig. 3 with the amount of phase fluctuation. It can be seen that the period of the equalization pulse and vertical pulse can be detected reliably. An example of a configuration in which the oscillation frequency of the oscillator 9 is controlled by the phase fluctuation of the composite synchronization signal is shown in FIGS.
As shown in the figure. FIG. 6 shows the phase comparison between the horizontal synchronization signal separated from the composite synchronization signal and the signal obtained by dividing the oscillation frequency of the variable oscillator 9 by the counter 13 in the phase comparator 14, and the output of this phase comparator 14. This is an APC method in which the variable oscillator 9 is controlled via a low-pass filter 16. Figure 6 shows terminal 1 having a phase variation proportional to the phase variation of the composite synchronization signal.
APC method in which a phase comparator 14 compares the phases of the reproduced color burst applied to the color burst 6 and a color burst reference oscillator 17, and the output of the phase comparator 14 is used to control the oscillator 9 via a low-pass filter 16. It is. The APC method requires a pulsed gate pulse to extract the color burst, but a set of 70 flips and 70 flips for burst gel generation, and a decoder to detect the 10 page set timing are implemented as shown in Figure 3. It can be easily constructed by adding it to the example circuit.

As described in detail, according to the present invention, the periods of equalization pulses and vertical synchronization pulses can be reliably detected even if the pulse width of each synchronization pulse in a composite synchronization signal is outside the television standard.

Furthermore, the circuit configuration is simple and can be constructed using only digital circuits, making it suitable for IC implementation.

By further adding a circuit, it is possible to detect the periods of equalization pulses and vertical synchronization pulses even in composite synchronization signals having phase fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a diagram of the same operating principle, FIG. 3 is a block diagram of one embodiment of the synchronization signal processing circuit according to the present invention, and FIG. 4 is the same as that shown in FIG. The operating waveform diagrams, Figures 5 and 6, are equalization pulses of a composite synchronization signal with phase fluctuations, respectively. Another embodiment of the present invention for detecting vertical synchronization pulses is shown in 112.
- FIG. 1... Pulse generation circuit, 3... Sample and hold circuit, 9... Oscillator, 8...
...AND game), 7.12 ... group flip-flop, 15 ... low-pass filter, 1o ... counter, 14 ... phase comparator, 17 ...Reference oscillator.

Claims (2)

[Claims] (1) When the horizontal scanning synchronization of a composite synchronization signal consisting of a horizontal synchronization pulse, an equalization pulse, and a vertical synchronization pulse is set to H1, where the equalization pulse width is E, the start timing of each synchronization pulse of the composite synchronization signal is equal to the time T. . HH (However, a pulse generation circuit that generates a pulse with a timing delayed by (T, < (H + E), and a sample-and-hold circuit that uses the output signal of the pulse generation circuit as a sampling pulse and the composite synchronization signal as input. 1. A synchronous signal processing circuit comprising: a circuit for obtaining an output signal from the sample-and-hold circuit. (2) The pulse generation circuit determines the output pulse width TW (however, 1857w (H)) by counting the clocks from the generator, and determines the output pulse width TW (however, 1857w (H)), and generates a digital signal triggered at the start timing of each synchronization pulse of the composite synchronization signal. The synchronous signal processing circuit according to claim 1, comprising a stable multivibrator and a degoder that decodes the state of a counter in the digital monostable multivibrator and outputs a sampling pulse at time T8.
°′、゛