JPS62190972A - Frame synchronizing signal detecting circuit - Google Patents

Abstract

PURPOSE:To detect a frame synchronizing signal from a composite synchronizing signal through simple circuit constitution by providing two latch signal generating circuits which generate the 1st and the 2nd latch signals, and obtaining the frame synchronizing signal with the output of a pulse shifting circuit. CONSTITUTION:A signal C which goes up to a high level at time t2 after a signal (a) rises and is held at the high level until a counter 25 is reset is outputted from the output terminal of a two-input AND gate 27 which constitutes a latch signal generating circuit 2. The 1st latch circuit 3 and the 2nd latch circuit 4 latch the signal with leading edges of signals (b) and (c) with the leading edges of signals (b) and (c) to obtain signals (d) and (e). The 3rd latch circuit 5 latches the level of the signal (e) with the leading edge of the signal (d) to obtain a signal (f). The signal (f) becomes a signal (g) which is a frame synchronizing signal by latching the signal with the leading edge of the signal (a) a signal (f) pulse shifting circuit 6, by a pulse shifting circuit 6. The signal (g) has stable phase relation with the signal (g).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frame synchronization signal detection circuit for obtaining a frame synchronization signal from a composite synchronization signal separated from a video signal.

2. Description of the Related Art Conventionally, frame synchronization signals have been used in various video equipment such as VTRs. Particularly in VTRs, this signal is very important as a reference signal for the phase control system of the rotary head and capstan during recording. In a simple home VTR, the vertical synchronization signal is separated from the composite synchronization signal separated from the video signal using a low pass filter (LPF), the waveform is shaped by a waveform shaper, the countdown is performed by two, and this is used as the reference for the phase control system. It is often used as a signal. (For example, “V
Introduction to TR Technology” Philosophy Publishing P224) Problems that the invention attempts to solve Currently, video signals in use include NTSC, -PAL.
, SECAM, and the luminance signals of these video signals form one picture (frame) from even and odd fields. The horizontal synchronizing signal has a phase difference of 0.5H between the even field and the odd field. Therefore, when editing is performed using a reference signal like in the conventional example, it is impossible to distinguish between even and odd fields, so it may not be possible to perform frame-by-frame [[], and during playback, the screen may be disturbed at the editing point. The present invention solves the problems of the above-mentioned prior art, and provides a frame synchronization signal that can obtain a frame synchronization signal with a field discrimination function from a composite synchronization signal with a simple configuration. The purpose is to facilitate the synchronization signal detection circuit.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a first synchronization signal having a different phase than the composite synchronization signal. A latch signal generation circuit that generates a second latch signal, a first latch signal, and a second latch signal that each latch a composite synchronization signal. The second part is a child circuit, and the first part is a child circuit. A third latch circuit that latches the output pulse of the other latch circuit with one output pulse of the second latch circuit, and frame synchronization from the output of a pulse source circuit that synchronizes the output pulse of the third latch circuit with a composite synchronization signal. It is used to obtain signals.

Effect of the Invention With the above-described configuration, the present invention can detect a frame synchronization signal in which even fields and odd fields constituting a frame have been determined from a composite synchronization signal with a simple circuit configuration.

Embodiment There are NTSC, PAL, SECAM, etc. video signals, and in this embodiment, the NTSC format will be explained.

FIG. 1 is a diagram showing an embodiment of a frame synchronization signal detection circuit according to the present invention. In FIG. 1, l is an input terminal to which a pulsed composite synchronizing signal separated from a video signal is input.

21 is a differentiator which manually inputs the composite synchronization signal and generates a reset pulse which becomes high level for a short time at +ii K& of the composite synchronization signal. 22 is a two-man powered AND gate circuit, one input terminal receives the output of the differentiator 21, the other input terminal receives the output signal of the two-man powered AND gate circuit 27, and the output terminal is connected to the reset R terminal of the counter 25. It is connected. 23 is a clock pulse generator whose frequency is ".

LK=6 f,, (fH29,97X525: Horizontal synchronizing signal frequency. 24 is a two-person AND gate circuit, one input terminal has the output terminal of the clock pulse generator 23, and the other input terminal has the inverter. The output terminal of the circuit 28 is connected, and the output terminal is connected to the clock (CK) terminal of the counter 25.The counter 25 is a 3-bit up counter with output terminals Q, , Q2, Q3, and Q.
,,Q2゜Q3 output number 3 and complementary signal to 61゜◇2. Output from d3 terminal. The output signal of the output terminal Q1 is inverted at every rising edge of the human input signal of the CK terminal, the output of the Q2 terminal is inverted at every rising edge of the output signal of the Q1 terminal, and the output of the Q3 terminal is inverted at every rising edge of the output signal of the Q2 terminal. Inverts the output level on every rising edge.

When a high level is input to the reset R terminal of the counter 25, the output terminals Q, , Q2 . The output signal of Q3 is reset to low level. 26 is a three-man-operated AND gate circuit, each input terminal of which is connected to the output terminal Q2 of the counter 25. Q...
Q3 is connected and its terminal outputs the first latch signal. 27 is a two-man-operated AND gate, one input terminal of which is connected to the output terminal Q of the counter 25, the other input terminal of which is connected to the output terminal Q3, and the second latch signal is outputted to the output terminal. The input terminal of the inverter circuit 2 is connected to the output terminal of the AND gate 27, and a signal obtained by inverting the level of the input signal is output to the output terminal of the 0wX divider 21.2 input terminal of the AND gate circuit 22.24 .27.3 human power AN
D gate circuit 27, inverter circuit 28, counter 25
, the clock pulse generator 23 constitutes the latch signal generation circuit 2. 3 is a first latch circuit, 4 is a second latch circuit, 5 is a third latch circuit, and 6 is a pulse shift circuit. The first to third latch circuits and pulse shift circuits 6 are composed of D-FFs, and these D-FFs have a data input terminal D, a clock input terminal C, and an output terminal Q. At the edge, the signal level input to the input terminal is output to the output terminal Q. 1st and 2nd
A composite synchronization signal is input to the D terminal of the latch circuit 3.4, the C terminal of the first latch circuit 3 is input to the output terminal of the three-man power AND gate circuit 26, and the C terminal of the second latch circuit 4 is input to the D terminal of the latch circuit 3.4. They are respectively connected to the output terminals of the two-man power AND gate circuit 27. The D terminal of the third latch 5 is connected to the C terminal of the second latch circuit 4, and the C terminal is connected to the C terminal of the first latch circuit 3. The D terminal of the pulse shift circuit 6 is the third
is connected to the C terminal of the latch circuit 5, and a composite synchronization signal is input to the C terminal.

FIG. 2 is a diagram of main signal waveforms in FIG. 1.

In Figure 2, signal a is a composite synchronization signal of the NTSC system, and TV and TV' in the figure are vertical synchronization pulse periods, and after the first vertical synchronization pulse of the TV period is an even field, and after the vertical synchronization pulse of the Tv' period. is an odd field. The signal is the output of the 3-man power AND gate 26 (No. 3, C is the 2-man power AND gate 26)
The output signal of the D gate circuit 27, the signal d is the output signal of the first latch circuit 3, the signal l is the output signal of the second latch circuit 4, the signal f is the output signal of the third latch circuit 5, and the signal g is a pulse. The output signal of the shift circuit 6 is a frame synchronization signal.

The operation of the above embodiment will be explained below.

The composite synchronization signal a has a horizontal synchronization period "11" of "T11"
(μ5aG), horizontal synchronization pulse H width is approximately 4.7 (μsp:c>' vertical synchronization pulse period is T
v is TV=37. , is. The vertical sync pulse width is 27.
1 (μSEC>' Also, the equivalent pulse width before and after the vertical synchronization pulse period is about 2.3 (μ5ac). When the signal a is manually input to the differentiator 21, the finer 21 has a minute width after the rising edge of the signal a. generates a pulse, and resets the counter 25 via the AND gate 22. When the counter 27 is reset, the output of the AND gate 27 becomes low level, and the output of the inverter 28 outputs high level. Therefore, the output of the two-manual AND gate becomes low level, prohibiting the counter 25 from being reset. Further, the clock signal which is the output signal of the clock signal generator 23 is output to the counter 2.
It is manually input to the clock terminal of 5. The counter 25 counts up by the clock input, and when 2CLK is input to the reset 1 & CK terminal, the 3-man power AND gate circuit 2
6 outputs a high level signal, which becomes a low level after 3 CLK input. Since the clock frequency is 6fH, after the rising edge of the signal a, the two-man AND circuit becomes high level at the 5th CLK after the counter 25 is reset, and the output of the inverter 24 becomes low level, and the subsequent output to the counter 25 becomes high level. In addition to prohibiting CLK input and keeping the high level after the 6th CLK,
It is possible to reset the counter 25 by the output of the differential 2S21.

That is, a signal C is outputted to the output terminal of the two-manufactured AND gate 27, which becomes a high level and thereafter remains at a high level until the counter 25 is reset. Since the counter 25 is prohibited from inputting and resetting CLK during the period when the signal A is at a high level, the period of the signal S, c becomes T. Signals d and e are obtained by latching at the rising edge of c. Signals d and e are connected to signal a.
It is at a high level for 3TH near the vertical synchronization pulse period and is at a low level during the other periods. The high level period near the vertical sync pulse period of the even field of signal d is delayed by L1 time with respect to the vertical sync pulse period Tv of signal a, and the high level period near the vertical sync pulse period of the odd field is the vertical sync of signal a. It has a 12 hour delay with respect to the pulse period Tv'.

The high level period near the vertical synchronizing pulse period of the even field of signal e is 12 hours relative to Tv, and the high level period near the intercostal space of the vertical synchronizing pulse of the odd field is Tv'
There is a time lag of tl. The third latch circuit 5 latches the level of the signal e at the rising edge of the signal d to obtain the signal ``.The signal r becomes a certain signal r by the pulse shift circuit 6.The signal f is a composite synchronization signal. This is a frame synchronization signal that maintains a stable phase relationship with respect to the vertical synchronization pulse period of the even field, changes from high level to low level during the vertical synchronization pulse period of the even field, and changes from low level to high level during the vertical synchronization pulse period of the odd field.

Effects of the Invention As described above, according to the present invention, a frame synchronization signal having a stable phase relationship with respect to a composite synchronization signal can be obtained with an extremely simple circuit configuration, and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a frame synchronization signal separation circuit according to the present invention, and FIG. 2 is a signal waveform diagram of a main part in FIG. 1. 2...U, child signal generation circuit, 3...First latch circuit, 4...Second latch circuit, 5
...Third latch circuit, 6...Pulse soft circuit.

Claims (1)

[Claims] The operation is started by the leading edge of the pulsed composite synchronization signal separated from the video signal, and t_1 hours after the operation (0<t_1<
T_H/2, T_H: horizontal synchronization period of video signal)
After t_2 hours (T_H/2<t
a latch signal generation circuit that generates a second latch signal at _2<T_H) and prohibits re-operation within at least t_2 hours after operation, and latches the pulse level of the composite synchronization signal using the first latch signal. a first latch circuit; a second latch circuit that latches the pulse level of the composite synchronization signal using the second latch signal;
a third latch circuit that latches the output level of the second latch circuit using the output of the first latch circuit; and a pulse shift circuit that shifts the output pulse signal of the third latch circuit using the composite synchronization signal. A frame synchronization signal detection circuit configured to obtain a frame synchronization signal from the output of the pulse shift circuit.