JP3475773B2 - Video signal processing device and liquid crystal display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device suitable for clamping a video signal without malfunction in a vertical blanking period, and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art The average level of a video signal varies depending on the brightness of the screen. Therefore, in the video signal processing device, it is necessary to clamp the input signal to a predetermined potential in order to secure the input dynamic range of the circuit.

An example of a conventional clamp circuit will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a conventional clamp circuit.

In the figure, 1 is a sync signal input terminal, 2 is a video signal input terminal, 3 is a sync signal separation circuit, 4 is a clamp pulse generation circuit, 5 is a clamp circuit, and 6 is a video output terminal.

The sync signal S input from the sync signal input terminal 1 is input to the sync signal separation circuit 3. The horizontal sync signal Sh obtained by the sync signal separation circuit 3 is input to the clamp pulse generation circuit 4. Clamp pulse generation circuit 4
Generates a clamp pulse CP in the pedestal portion of the input video signal Vin based on the input horizontal synchronizing signal Sh.

The pedestal portion of the video signal is a front porch for one horizontal period (a portion after the horizontal synchronizing signal rises from the sync tip level to the pedestal level and before the picture period starts) or a back porch (the picture period is After the end, the part from the pedestal level to fall to the sync tip level) exists. For this reason, the clamp pulse generating circuit 4 is often configured by a mono-multivibrator that generates a pulse delayed for a predetermined period by using the horizontal synchronizing signal Sh as a trigger.

This clamp pulse CP is applied to the clamp circuit 4
When the pedestal portion of the input video signal Vin input from the video signal input terminal 2 is clamped to a predetermined potential in the clamp circuit 5, the input video signal Vin is output from the video output terminal 6 as the output video signal Vout. It

[0008]

By the way, the video signal in the vertical blanking period is different from the normal period so that the reference timing of the vertical synchronization can be detected. It is configured. Specifically, as shown in FIG. 2A, the input video signal Vin in the vertical blanking period has six positive-direction equivalent pulses, six negative-direction equivalent pulses, and six positive-direction equivalent pulses. Composed of pulses.

Here, the clamp pulse CP is shown in FIG.
As shown in, the horizontal synchronizing signal Sh is generated as a reference. When clamping is performed using this clamp pulse CP, the portion of the low level VL shown in FIG. 2A is clamped as the pedestal portion during the equivalent pulse period in the negative direction. Two
As shown in (c), there is a problem that sags occur and correct clamping is not performed.

Further, in the liquid crystal display device equipped with the conventional video signal processing device, there is a problem that the display quality becomes unstable because the clamp is unstable in the video signal processing device.

Therefore, an object of the present invention is to provide a video signal processing device which prevents the pedestal portion of an output video signal from being clamped to a potential different from a predetermined potential.

Another object of the present invention is to provide a liquid crystal display device which eliminates unstable display quality.

[0013]

In order to solve the above-mentioned problems, in the video signal processing apparatus according to the present invention, a horizontal synchronizing signal and a vertical synchronizing signal are separated from a synchronizing signal synchronized with an input video signal. A sync separation circuit, pulse generation means for generating a pulse signal in a period in which the input video signal is periodically at a constant level based on the horizontal sync signal separated by the sync separation circuit, and a vertical blanking period. Is detected and the masking signal generating means for generating a masking signal for masking the period and the pulse signal masked by the masking signal are used to clamp the input video signal to a constant potential to generate an output video signal. A video signal processing device comprising: clamp means for performing the vertical retrace period masked by the mask signal. Characterized in that it does not clamp the fill force video signal at a constant potential.

According to the present invention, since the clamping is performed by the masked pulse signal in which the vertical blanking period is masked,
It is not clamped to a potential different from the predetermined potential. Therefore, the pedestal portion can always be stably clamped to a predetermined potential.

Further, in the video signal processing apparatus according to the present invention, the pulse generating means generates the clock signal with reference to the cycle of the horizontal synchronizing signal separated by the synchronizing separating means. And the PLL
It is characterized by comprising counting means for counting the clock signal generated by the means, and decoder means for generating the pulse signal by comparing the count value of the counting means with a reference value.

Further, in the video signal processing device according to the present invention, the pulse generating means generates the pulse signal during a period when the input video signal is at a pedestal level or a sync chip level. It is characterized by

According to these means, the pedestal portion of the video signal can be specified and clamped.

The video signal processing device according to the present invention is characterized by including the video signal processing device and displaying an image based on the output video signal.

According to this means, an image is displayed based on a stable output video signal, so that a liquid crystal display device with stable display quality can be obtained.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1. Configuration of Embodiment FIG. 3 is a block diagram showing a configuration of a video signal processing device according to an embodiment of the present invention. Further, FIG. 4 is a waveform diagram showing signal waveforms of respective parts in the block diagram of FIG.

In FIG. 3, reference numeral 1 is a sync signal input terminal, in which the sync signal S of the input video signal Vin is provided in an external device or a video signal processing device (a sync signal generating circuit) (not shown). No.) will be supplied from. Reference numeral 2 is a video signal input terminal, to which the input video signal Vin is input. In this example, a composite video signal will be described as an example.

Reference numeral 3 denotes a sync signal separation circuit, which converts the input sync signal Vin into a horizontal sync signal Sh and a vertical sync signal S.
Separate into v. Since the synchronization signal separation circuit 3 has a well-known configuration, detailed description thereof will be omitted here, but for example, it may be configured by combining a slice circuit that slices at a constant potential, a low-pass filter, and the like.

4 is a clamp pulse C at a predetermined timing.
A clamp pulse generating circuit for generating P
Circuit 401, counter circuit 402, and decoder circuit 4
It is composed of 03. The PLL circuit 401 generates a high-frequency clock signal CK synchronized with the horizontal synchronization signal Sh. When the clock signal CK is supplied to the counter circuit 402, the counter circuit 402 causes the clock signal C
It is configured to count up K, reset when a predetermined number is counted, and generate a ripple carry signal RC. Then, the PLL circuit 401 compares the phases of the ripple carry signal RC and the horizontal synchronizing signal Sh and generates a clock signal CK according to the comparison error. Therefore, the clock signal CK and the horizontal synchronization signal Sh are always synchronized, for example, the frequency of the clock signal CK is Fck, the frequency of the horizontal synchronization signal is Fh,
If the maximum count number of the counter circuit 402 is N, then F
The relationship of h = N · Fck is established.

Here, in the PLL circuit 401, the phase error signal is generated so that the phases of the ripple carry signal RC and the horizontal synchronizing signal Sh match, and the clock signal CK is generated based on this, so that the counter 402 counts. The numerical value indicates the phase in one horizontal period.
The decoder circuit 403 uses this to generate the clamp pulse CP. Therefore, the decoder circuit 403
In the column, a reference value indicating how many clock signals CK are counted from the start of the horizontal scanning period to reach the pedestal portion is stored. The reference value and the count value of the counter circuit 402 are compared with each other, and the clamp pulse CP is generated at the timing when the two coincide with each other.

Next, the vertical blanking period detection circuit 7 counts the ripple carry signal RC (synchronized with the horizontal synchronizing signal) output from the counter circuit 402 with the vertical synchronizing signal Sv as a reference, and thereby the vertical blanking period. A mask signal M which becomes a low level during the period and becomes a high level during the other period.
Is configured to generate.

Next, the AND gate 8 is adapted to mask the clamp pulse CP during the vertical blanking period by the mask signal M to generate a masked clamp pulse CP '. A clamp circuit 5 clamps the input video signal Vin by the masked clamp pulse CP 'to generate an output video signal Vout.

With the above-described structure, the clamp can be performed by the masked clamp pulse CP 'that masks the vertical blanking period. Therefore, the clamping should be performed during the period in which the negative equivalent pulse exists within the vertical blanking period. Disappears. Therefore, it becomes possible to always clamp the pedestal portion at a predetermined potential.

2. Operation of Embodiment Next, the operation of the embodiment will be described with reference to the drawings. FIG. 4 is a diagram showing main signal waveforms of the video signal processing device according to the present embodiment.

When the sync signal S shown in FIG. 4A is supplied from the sync signal input terminal 1 to the sync signal separation circuit 3, the sync signal separation circuit 3 outputs the sync signal S horizontally as shown in FIG. 4B. The sync signal Sh and the vertical sync signal Sv shown in FIG. 4C are separated.

After that, the horizontal synchronizing signal Sh is input to the PLL circuit 401 of the clamp pulse generating circuit 4, and the phase is compared at the point where the counter circuit 402 reaches one cycle of the horizontal synchronizing signal Sh. The counter circuit 402 counts the clock signal CK and is reset at the point where the phase comparison is performed to generate the ripple carry signal RC. That is, the count value of the counter circuit 402 is synchronized with the horizontal synchronization signal Sh. The count result of the counter circuit 402 is always input to the decoder circuit 403. By comparing the count value with the reference value, the clamp shown in FIG. 4D is performed at a timing corresponding to the pedestal portion of the input video signal Vin. Generate a pulse CP.

Further, the ripple carry signal RC of the counter circuit 402 is sent to the vertical blanking period detection circuit 7 and vertically based on the vertical synchronizing signal Sv shown in FIG. 4C separated by the synchronizing signal separating circuit 3. The blanking period is detected, and Fig. 4 (e)
The mask signal M shown in is generated. Next, when the clamp pulse CP and the mask signal M are sent to the AND gate 8, the pulse excluding the clamp pulse CP in the vertical blanking period is the masked clamp pulse C shown in FIG.
It is generated as P '.

After that, the clamp circuit 5 clamps the input video signal Vin shown in FIG. 4 (g) by using the masked clamp pulse CP 'to generate the output video signal Vout shown in FIG. 4 (h). .

As described above, according to the video signal processing apparatus according to the present embodiment, the clamp pulse CP in the vertical blanking period is masked by the mask signal M, so that the actual clamping is performed outside the vertical blanking period. Will be done. Therefore, the video signal can be clamped to a predetermined potential and stably.

In the above-described embodiment, the video signal processing device has been described as an example. However, this video signal processing device is
For example, it may be a display device for displaying an image such as a liquid crystal display device, an image recording / reproducing device for recording / reproducing an image on a VTR or a DVD, or a special effect device for performing image processing such as a chroma key. Is.

In the above embodiment, the entire vertical blanking period is masked. However, the present invention is not limited to this, and the vertical synchronizing period in which a negative equivalent pulse exists (see FIG. 4 (c) vertical synchronization signal Sv
The mask processing may be performed only during a low level period.

Further, in the above-mentioned embodiment, PL
Although the pedestal portion of the video signal is specified by using the L circuit 401, the counter circuit 402, and the like, the present invention is not limited to this. The point is that the pedestal portion of the video signal is based on the horizontal synchronizing signal. Anything may be used as long as it specifies the pedestal portion.

In the above embodiment, the pedestal level is clamped, but the present invention is
For example, the sync tip level may be clamped. The point is that the video signal can be clamped to a constant level during a period in which the level of the video signal periodically becomes a constant level. It may be.

[0039]

As described above, according to the video signal processing apparatus of the present invention, the vertical blanking period is detected, and the clamp pulse is omitted by using the mask signal of this portion. And it can be clamped stably.

Further, in the liquid crystal display device of the present invention, since the clamp is stable in the video signal processing device, the display quality can be kept stable.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional video signal processing device.

FIG. 2 is a waveform diagram showing the waveform of each part in FIG.

FIG. 3 is a block diagram showing a configuration of a video signal processing device according to an embodiment of the present invention.

FIG. 4 is a waveform diagram showing the waveform of each part in FIG.

[Explanation of symbols]

1 Sync signal input terminal 2 Video signal input terminal 3 Sync signal separation circuit 4 Clamp pulse generation circuit 401 PLL circuit 402 counter circuit 403 Decoder circuit 5 Clamp circuit 6 Video output terminal 7 Vertical blanking period detection circuit 8 AND gate

Claims (2)

(57) [Claims] 1. A synchronizing signal synchronized with an input video signal,
A sync separation circuit that separates a horizontal sync signal and a vertical sync signal, and a pulse signal is generated during a period in which the input video signal periodically has a constant level based on the horizontal sync signal separated by the sync separation circuit. Pulse generating means, a mask signal generating means for detecting a vertical blanking period and generating a mask signal for masking the period, and using the pulse signal, the input video signal is clamped to a constant potential to output an image. A video signal processing device comprising a clamp means for generating a signal, wherein the clamp means masks the pulse signal so that the clamp means holds the input video signal at a constant potential during the vertical blanking period. A video signal processing device characterized by not being clamped to. 2. A liquid crystal display device comprising the video signal processing device according to claim 1, and displaying an image based on the output video signal.