JPH11275387A - Video signal processor and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processor capable of preventing the pedestal part of an output video signal from being clamped to the potential different from the prescribed potential. SOLUTION: A mask signal M is generated by a vertical fly-back period detecting circuit 7 and the mask signal M and a clamp pulse CP are inputted to an AND gate 8 so that a masked clamp signal CP' is generated. A clamping circuit 5 executes clamping processing through the use of the signal CP', so that it is prevented to be clamped to the potential different from the desired potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a video signal processing device suitable for clamping a video signal without malfunction during a vertical blanking period, and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art The average level of a video signal varies depending on the brightness of a screen. Therefore, in the video signal processing device, it is necessary to clamp the input signal to a predetermined potential in order to secure the input dynamic range of the circuit.

Hereinafter, an example of a conventional clamp circuit will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a conventional clamp circuit.

In the figure, 1 is a synchronization signal input terminal, 2 is a video signal input terminal, 3 is a synchronization signal separation circuit, 4 is a clamp pulse generation circuit, 5 is a clamp circuit, and 6 is a video output terminal.

[0005] The synchronization signal S input from the synchronization signal input terminal 1 is input to the synchronization signal separation circuit 3. The horizontal synchronization signal Sh obtained by the synchronization signal separation circuit 3 is input to the clamp pulse generation circuit 4. Clamp pulse generation circuit 4
Generates a clamp pulse CP in the pedestal portion of the input video signal Vin with reference to the input horizontal synchronization signal Sh.

[0006] The pedestal portion of the video signal may be a front porch for one horizontal period (a portion before the picture period starts after the horizontal synchronizing signal rises from the sync chip level to the pedestal level) or a back porch (the picture period is not longer than the porch). After the processing is completed, there is a portion from the pedestal level to the fall to the sync tip level). For this reason, the clamp pulse generating circuit 4 is often constituted by a mono-multivibrator that generates a pulse delayed for a predetermined period by using the horizontal synchronization signal Sh as a trigger.

This clamp pulse CP is applied to the clamp circuit 4
Supplied, the input video signal Vin input from the video signal input terminal 2 is output as an output video signal Vout from the video output terminal 6 after its pedestal portion is clamped to a predetermined potential in the clamp circuit 5. You.

[0008]

By the way, the video signal in the vertical blanking period is different from the normal period in that the video signal in the vertical blanking period is separated from the positive equivalent pulse and the negative equivalent pulse in order to detect the vertical synchronization reference timing. It is configured. Specifically, as shown in FIG. 2A, the input video signal Vin in the vertical blanking period has six positive direction equivalent pulses, six negative direction equivalent pulses, and six positive direction equivalent pulses. It consists of pulses.

Here, the clamp pulse CP is shown in FIG.
As shown in (1), the horizontal synchronization signal Sh is generated as a reference. When clamping is performed using the clamp pulse CP, the low level VL portion shown in FIG. 2A is clamped as a pedestal portion in the negative equivalent pulse period, so that the waveform of the output video signal Vout is 2
As shown in (c), there is a problem that sag occurs and correct clamping is not performed.

Further, in the liquid crystal display device equipped with the conventional video signal processing device, there is a problem that the display quality becomes unstable because the clamp is unstable in the video signal processing device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing apparatus which prevents a pedestal portion of an output video signal from being clamped to a potential different from a predetermined potential.

Another object of the present invention is to provide a liquid crystal display device in which an unstable portion of display quality is eliminated.

[0013]

According to the first aspect of the present invention, there is provided a synchronization apparatus for separating a horizontal synchronization signal and a vertical synchronization signal from a synchronization signal synchronized with an input video signal. A separation circuit, based on the horizontal synchronization signal separated by the synchronization separation circuit, pulse generation means for generating a pulse signal during a period in which the input video signal periodically becomes a constant level, and based on the vertical synchronization signal. Mask signal generating means for generating a mask signal for masking at least a period of the vertical synchronizing signal; and using the pulse signal masked by the mask signal, clamping the input video signal to a constant potential to generate an output video signal And clamping means for performing the operation.

According to the present invention, since clamping is performed by a masked pulse signal that masks the vertical blanking period,
It is no longer clamped to a potential different from the predetermined potential. Therefore, the pedestal portion can always be stably clamped at a predetermined potential.

Further, in the invention according to claim 2,
The pulse generation means includes: a PLL means for generating a clock signal based on a cycle of the horizontal synchronization signal separated by the synchronization separation means; a counting means for counting a clock signal generated by the PLL means; And a decoder for generating the pulse signal by comparing the count value of the above with a reference value.

Further, in the invention according to claim 3,
The pulse generating means may generate the pulse signal during a period when the input video signal is at a pedestal level or during a period when the input video signal is at a sync tip level.

According to these means, the pedestal portion of the video signal can be specified and clamped.

Further, in the invention according to claim 4,
The image processing apparatus includes the video signal processing device, and displays an image based on the output video signal.

According to this means, since an image is displayed based on a stable output video signal, a liquid crystal display device with stable display quality can be obtained.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

1. Configuration of Embodiment FIG. 3 is a block diagram illustrating a configuration of a video signal processing device according to an embodiment of the present invention. FIG. 4 is a waveform diagram showing signal waveforms at various parts in the block diagram of FIG.

In FIG. 3, reference numeral 1 denotes a synchronizing signal input terminal, in which a synchronizing signal S of an input video signal Vin is supplied to an external device or a synchronizing signal generating circuit (shown in FIG. )). Reference numeral 2 denotes a video signal input terminal to which an input video signal Vin is input. In this example, a composite video signal will be described as an example.

Reference numeral 3 denotes a synchronizing signal separating circuit which converts an input synchronizing signal Vin into a horizontal synchronizing signal Sh and a vertical synchronizing signal S.
v. The synchronizing signal separating circuit 3 has a well-known configuration, and a detailed description thereof will be omitted. For example, the synchronizing signal separating circuit 3 may be configured by combining a slice circuit that slices at a constant potential, a low-pass filter, and the like.

4 is a clamp pulse C at a predetermined timing.
A clamp pulse generating circuit for generating P;
Circuit 401, counter circuit 402, and decoder circuit 4
03. The PLL circuit 401 generates a high-frequency clock signal CK synchronized with the horizontal synchronization signal Sh. When the clock signal CK is supplied to the counter circuit 402, the counter circuit 402
K is counted up and reset when a predetermined number is counted, and a ripple carry signal RC is generated. Then, the PLL circuit 401 compares the phase of the ripple carry signal RC and the horizontal synchronization signal Sh, and generates a clock signal CK corresponding to the comparison error. Therefore, the clock signal CK and the horizontal synchronization signal Sh are always synchronized. For example, the frequency of the clock signal CK is Fck, the frequency of the horizontal synchronization signal is Fh,
If the maximum count number of the counter circuit 402 is N, F
The relationship h = N · Fck holds.

Here, in the PLL circuit 401, a phase error signal is generated so that the phases of the ripple carry signal RC and the horizontal synchronizing signal Sh match, and the clock signal CK is generated based on the phase error signal. The numerical value indicates the phase in one horizontal period.
The decoder circuit 403 utilizes this to generate the clamp pulse CP. Therefore, the decoder circuit 403
Stores a reference value indicating how many clock signals CK are counted from the start of the horizontal scanning period to reach the pedestal portion. The reference value is compared with the count value of the counter circuit 402, and a clamp pulse CP is generated at a timing when the two coincide with each other.

Next, the vertical retrace period detecting circuit 7 counts the ripple carry signal RC (synchronous with the horizontal synchronous signal) output from the counter circuit 402 on the basis of the vertical synchronous signal Sv, thereby obtaining the vertical retrace line. A mask signal M that is low during the period and high during the other periods
Is configured to generate

Next, the AND gate 8 generates a masked clamp pulse CP 'by masking the clamp pulse CP during the vertical blanking period by the mask signal M. Reference numeral 5 denotes a clamp circuit, which clamps an input video signal Vin with a masked clamp pulse CP 'to generate an output video signal Vout.

According to the above configuration, the clamp can be performed by the masked clamp pulse CP 'masking the vertical blanking period. Therefore, the clamping can be performed in the vertical blanking period during which a negative equivalent pulse exists. Disappears. Therefore, it is possible to always clamp the pedestal portion at a predetermined potential.

2. Operation of Embodiment Next, the operation of the embodiment will be described with reference to the drawings. FIG. 4 is a diagram showing main signal waveforms of the video signal processing device according to the present embodiment.

When the synchronization signal S shown in FIG. 4A is supplied from the synchronization signal input terminal 1 to the synchronization signal separation circuit 3, the synchronization signal separation circuit 3 converts the synchronization signal S to the horizontal signal shown in FIG. The signal is separated into a synchronization signal Sh and a vertical synchronization signal Sv shown in FIG.

Thereafter, the horizontal synchronizing signal Sh is input to the PLL circuit 401 of the clamp pulse generating circuit 4, and the counter circuit 402 compares the phases at a point where one cycle of the horizontal synchronizing signal Sh is reached. The counter circuit 402 counts the clock signal CK and is reset at a point where the phase comparison is performed to generate a ripple carry signal RC. That is, the count value of the counter circuit 402 is synchronized with the horizontal synchronization signal Sh. The count result of the counter circuit 402 is always input to the decoder circuit 403. By comparing the count value with the reference value, the clamp circuit shown in FIG. 4D is obtained at a timing corresponding to the pedestal portion of the input video signal Vin. A pulse CP is generated.

The ripple carry signal RC of the counter circuit 402 is sent to the vertical blanking period detecting circuit 7 and is vertically separated based on the vertical synchronizing signal Sv shown in FIG. The retrace period is detected, and FIG.
Is generated. Next, when the clamp pulse CP and the mask signal M are sent to the AND gate 8, a pulse obtained by omitting the clamp pulse CP in the vertical retrace period is a masked clamp pulse C shown in FIG.
Generated as P '.

Thereafter, the clamp circuit 5 clamps the input video signal Vin shown in FIG. 4G using the masked clamp pulse CP 'to generate the output video signal Vout shown in FIG. 4H. .

As described above, according to the video signal processing apparatus according to the present embodiment, the clamp pulse CP in the vertical blanking period is masked by the mask signal M, so that the actual clamp is performed in a period other than the vertical blanking period. Will be done. Therefore, it is possible to stably clamp the video signal to a predetermined potential.

In the above-described embodiment, the video signal processing device has been described as an example.
For example, a display device that displays an image, such as a liquid crystal display device, an image recording / reproducing device that records and reproduces an image such as a VTR or a DVD, or a special effect device that performs image processing such as chroma keying may be used. It is.

Further, in the above-described embodiment, the entire vertical blanking period is masked. However, the present invention is not limited to this, and the vertical synchronizing period (see FIG. The vertical synchronization signal Sv shown in FIG.
May be performed only during a low-level period).

In the above embodiment, the PL
Although the pedestal portion of the video signal is specified using the L circuit 401, the counter circuit 402, and the like, the present invention is not limited to this. Any type may be used as long as it specifies the pedestal portion.

Further, in the above-described embodiment, the pedestal level is clamped.
The present invention is not limited to this. For example, the sync tip level may be clamped. The point is that the video signal can be clamped to a constant level during a period in which the level of the video signal periodically becomes a constant level. There may be.

[0039]

As described above, according to the video signal processing apparatus of the present invention, the vertical blanking period is detected, and the clamp pulse is omitted by using the mask signal in this portion. And can be stably clamped.

Further, in the liquid crystal display device of the present invention, since the clamp is stabilized in the video signal processing device, the display quality can be kept stable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional video signal processing device.

FIG. 2 is a waveform chart showing waveforms at various parts in FIG.

FIG. 3 is a block diagram illustrating a configuration of a video signal processing device according to an embodiment of the present invention.

FIG. 4 is a waveform diagram showing waveforms at various parts in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization signal input terminal 2 Video signal input terminal 3 Synchronization signal separation circuit 4 Clamp pulse generation circuit 401 PLL circuit 402 Counter circuit 403 Decoder circuit 5 Clamp circuit 6 Video output terminal 7 Vertical blanking period detection circuit 8 AND gate

Claims (4)

[Claims] 1. A synchronizing signal synchronized with an input video signal,
A synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal; and a pulse signal is generated based on the horizontal synchronization signal separated by the synchronization separation circuit during a period in which the input video signal periodically becomes a constant level. Pulse generating means, mask signal generating means for generating a mask signal for masking at least a period of the vertical synchronization signal based on the vertical synchronization signal, and the input video signal using the pulse signal masked by the mask signal And a clamp means for generating an output video signal by clamping the video signal to a constant potential. 2. The pulse generating means comprises: a PLL means for generating a clock signal based on a cycle of the horizontal synchronizing signal separated by the synchronization separating means; and a counting means for counting a clock signal generated by the PLL means. 2. The video signal processing apparatus according to claim 1, further comprising: a decoder for generating the pulse signal by comparing a count value of the counting unit with a reference value. 3. The video according to claim 1, wherein the pulse generation unit generates the pulse signal during a period when the input video signal is at a pedestal level or a period when the input video signal is at a sync tip level. Signal processing device. 4. A liquid crystal display device comprising the video signal processing device according to claim 1, and displaying an image based on the output video signal.