JPH0218636B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to means for detecting an equalization pulse period and a vertical synchronization pulse period from a television composite synchronization signal.

Conventional configuration and its problems Various methods have been devised and put into practical use for detecting equalization pulses and vertical synchronization pulses. These methods can be roughly divided into two methods. The first is a method using an integrating circuit, and the second is a method that determines the difference in pulse width of a horizontal synchronizing pulse, an equalization pulse, and a vertical synchronizing pulse.

However, the first method has disadvantages in that it causes a delay in the output which is determined by a time constant in principle and that it is difficult to detect the equalization pulse.

Furthermore, the second method can reduce the delay time of the detection output, can be configured with a digital circuit, and is suitable for IC implementation. However, the pulse width of the equalization pulse is narrower than the horizontal synchronization pulse, and the difference between them is as small as about 2.4 μsec, so the pulse width of the equalization pulse becomes wider by about 1.2 μsec.
Or, the pulse width of the horizontal sync pulse is approximately 1.2μsec
If the width becomes narrower, it becomes difficult to distinguish between the equalization pulse and the horizontal synchronization pulse, resulting in erroneous determination. The composite synchronization signal obtained by playing VTP, especially a tape that has been repeatedly dubbed, has large time axis fluctuations, and may have a pulse width that is 1 to 2 μsec different from the television standard pulse width. If a composite synchronization signal is input, there is a problem in that the equalization pulse and the horizontal synchronization pulse may be incorrectly determined.

OBJECT OF THE INVENTION Even if the composite sync signal has time axis fluctuations, and even if the pulse width of each sync pulse deviates from the television standard, it is possible to calculate the period of the equalization pulse and vertical sync pulse from the composite sync signal. An object of the present invention is to ensure reliable detection.

Structure of the Invention In the composite synchronization signal, horizontal synchronization pulses are arranged at intervals of horizontal scanning period H, and equalization pulses and vertical synchronization pulses are arranged at intervals of 0.5H. Also, the start timing of the equalization pulse and vertical synchronization pulse is 0.5H from the start timing of the horizontal synchronization pulse.
located at a distance of an integer multiple of . Based on the properties of this composite synchronization signal, the present invention determines whether there is an equalization pulse or vertical synchronization pulse at a position 0.5H away from the start timing of each synchronization pulse in the composite synchronization signal. Detecting the duration of the pulse. This detection is performed by sampling the composite synchronization signal using a sampling pulse. This sampling pulse is created by counting the frequency clock that follows the phase and frequency fluctuations of the composite synchronization signal, so even for composite synchronization signals that have time axis fluctuations, it can follow the time axis fluctuations. A sampling pulse can be obtained, and even an equalization pulse with an extremely narrow pulse width compared to other synchronization pulses can be reliably detected. The presence or absence of equalization pulses and vertical synchronization pulses is determined by the composite synchronization at a timing delayed by a time T _s that satisfies the following formula 1 from the start timing of each synchronization pulse in the composite synchronization signal, when the equalization pulse width is E. Just sample the signal.

H/2<T _s <(H/2+E) (1) Description of Embodiment FIG. 1 shows a block configuration diagram that is the basis of the present invention. The pulse generating circuit 1 detects the start timing of each synchronizing pulse in the composite synchronizing signal applied to the terminal 2, and outputs a sampling pulse after a time _Ts . Sample and hold circuit 3
reads the composite synchronizing signal input using the output of the pulse generating circuit 1 as a sampling pulse.

In the present invention, the timing of the sampling pulse is set to satisfy equation (1). Sample and hold circuit 3 in this setting
The output is the detection output for the period of the equalization pulse and vertical synchronization pulse.

FIG. 2 shows an example of its operating waveforms. A is the waveform of the composite synchronizing signal for the odd field, D is the waveform for the even field, 4 is the horizontal synchronizing signal, 5 is the equalization pulse, and 6 is the vertical synchronizing pulse. B and E are output examples of the pulse generation circuit 1,
C and F are the outputs of the sample-and-hold circuit 3. If you look at D and F in Figure 2, the time delay for equalization pulse and vertical synchronization pulse detection in even fields is small, but if you look at A and C, the time delay for equalization pulse and vertical synchronization pulse detection in odd fields is 0.5H. It can be seen that a time delay occurs. However, a time delay of 0.5H is not a practical problem.
A and D are synchronization signals in the case of the NTSC system, but
It can also be applied to PAL and SECAM systems.

FIG. 3 shows a specific embodiment of the present invention. The pulse generation circuit 1 includes a digital monostable multivibrator and a decoder that decodes the state of the counter of the digital monostable multivibrator and generates a sampling pulse output. Further, the sample and hold circuit 3 is made up of a flip-flop. The digital monostable multivibrator is triggered at the start timing of each synchronization pulse of the composite synchronization signal, and outputs a pulse with a width of time T _w that satisfies the following equation (2).

T _s ≦T _w <H ………(2) Because, in order to detect time T _s , T _s ≦T _w must be satisfied, and after time T _s , each synchronization pulse does not come until time H. It is sufficient if T _w <H.
Of course, if the time T _w is not required, T _w = T _s may be used, which simplifies the circuit configuration.

The operation shown in FIG. 3 will be explained. flipflop 7
is set at the start timing of the synchronization pulse, that is, at the rising edge. flipflop 7
The output Q opens the AND gate 8 and the oscillator 9
(abbreviated as OSC in FIG. 3) begins to be input to the counter 10. Decoder 11 decodes the state of the counter and generates timing pulses. The output a of the decoder is the detection output of time T _w and resets the flip-flop 7. The Q output of flip-flop 7 closes AND gate 8, and the output of flip-flop 7 resets counter 10, completing the operation of the digital monostable multivibrator. The decoder output β is the detection output of the time _Ts , that is, the sampling timing. The sample-and-hold circuit 3, that is, the flip-flop 12 reads the composite synchronizing signal using the decoder output β as a sampling pulse.

FIG. 4 shows operating waveforms of the circuit example shown in FIG. 3. As shown in FIG. 4A, even if the width of each synchronization pulse in the composite synchronization signal becomes narrow as shown by the broken line or widened as shown by the dot-dashed line, the equalization pulse and vertical synchronization are reliably maintained. It is easy to see that the duration of the pulse can be detected.

Note that B in FIG. 4 is the Q of flip-flop 7.
The output, C is the output of the gate 8, D is the output a of the decoder 11, E is the output β of the decoder 11, and F is the output of the flip-flop 12.The output of the flip-flop 12 determines the equalization pulse period and the vertical synchronization signal. This output is obtained by detecting the period and the horizontal synchronization signal period.

As can be seen from the operating waveforms in FIG. 4, the pulse generation circuit 1 in this embodiment operates as a horizontal synchronization signal separation circuit that removes equalization pulses and vertical synchronization signals. Conversely, by adding one decoder and one flip-flop to the horizontal synchronization signal separation circuit, an equalization pulse and vertical synchronization pulse period detection circuit can be realized with a simple configuration. Additionally, this configuration has the advantage of being suitable for IC implementation because it can be realized using only digital circuits.

The above is a case where there is no phase fluctuation or frequency fluctuation of the decoded synchronization signal, but even if the composite synchronization signal has phase fluctuation or frequency fluctuation, the oscillation frequency of the oscillator 9 in FIG. By controlling with , it is possible to reliably detect the period of the equalization pulse and vertical synchronization pulse. In FIG. 3, a circuit for controlling this oscillation frequency is omitted for convenience of explanation. A block diagram of the synchronization signal processing circuit of the present invention, which also shows a circuit for controlling the oscillation frequency of the oscillator 9 based on the amount of phase variation of the composite synchronization signal, is shown in FIG.
As shown in Fig. 6. FIG. 5 shows the phase comparison between the horizontal synchronization signal separated from the composite synchronization signal and the signal obtained by dividing the oscillation frequency of the variable oscillator 9 by the counter 13 in the phase comparator 14, and the output of this phase comparator 14. This is an AFC method in which the variable oscillator 9 is controlled via a low-pass filter 15. Figure 6 shows terminal 1 having a phase variation proportional to the phase variation of the composite synchronization signal.
The APC method uses a phase comparator 14 to compare the phases of the reproduced color burst applied to the color burst 6 and the color burst reference oscillator 17, and controls the oscillator 9 using the output of the phase comparator 14 via a low-pass filter 15. It is. The APC method requires a burst gate pulse to extract the color burst, but this can be easily done by adding a flip-flop for generating a burst gate and a decoder for detecting the set and reset timing of this flip-flop to the circuit of the embodiment shown in FIG. It can be configured as follows.

Effects of the Invention As explained above, according to the present invention, even if the composite synchronization signal has time axis fluctuations, and even if the pulse width of each synchronization pulse is outside the television standard, the equalization pulse and the vertical synchronization pulse period can be reliably detected.

[Brief explanation of drawings]

Figure 1 is a block configuration diagram showing the basic configuration of the present invention, Figure 2 is a diagram of the operating principle of the present invention, and Figure 3 is a block diagram showing the basic configuration of the present invention.
FIG. 4 is a block diagram of an embodiment of the synchronous signal processing circuit according to the present invention, FIG. 4 is an operating waveform diagram of the synchronous signal processing circuit of the present invention shown in FIG. 3, and FIGS. FIG. 2 is a block diagram of an embodiment of the synchronous signal processing circuit of the present invention, also showing a circuit for controlling the oscillation frequency of the oscillator 9 based on the amount of phase fluctuation of the signal. 1... Pulse generation circuit, 3... Sample and hold circuit, 9... Oscillator, 8... AND
Gate, 1, 12...Flip-flop, 15...
...Low pass filter, 10...Counter, 14...Phase comparator, 17...Reference oscillator.

Claims (1)

[Scope of Claims] 1. A pulse generation circuit that generates a sampling pulse delayed by a predetermined time from the start timing of each synchronization pulse (horizontal synchronization pulse, equalization pulse, vertical synchronization pulse) of a composite synchronization signal; It consists of a sample-and-hold circuit that performs sample-holding using a sampling pulse, and the pulse generating circuit calculates the output pulse width Tw by counting clocks with a frequency approximately proportional to the phase change or frequency change of the synchronizing pulse. is determined, and the digital monostable multivibrator triggered at the start timing of the synchronization pulse and the output of the counter in the digital monostable multivibrator are decoded for a predetermined time Ts (however, the horizontal scanning period is H, and the equalization pulse width is and a decoder that outputs the sampling pulse satisfying the following conditions: H/2<Ts<E+H/2 and Ts≦Tw<H, where E is H/2<Ts<E+H/2.