JP2763340B2 - Non-standard signal detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a non-standard signal detection circuit used in a digital television receiver.

[Conventional technology]

Digital television that converts video signals to digital signals and achieves high image quality by digital signal processing, especially 3D YC using correlation between adjacent frames
A digital television that realizes high image quality by separation can perform high image quality processing on the NTSC signal standard, that is, a standard signal that satisfies the following equation (1).

f _SCB : color sub-carrier frequency f _H : horizontal scanning frequency f _V : vertical scanning frequency However, when a consumer VTR is used as a signal source,
The relationship of frequency interleaving is lost due to the jitter of the running system, etc., and the color subcarrier frequency f _SCB and the horizontal scanning frequency f _H
May not satisfy the expression (1) in this case. In this case, the image quality deteriorates rather than performing the three-dimensional digital signal processing. Therefore, it is necessary to change the digital video signal processing system between the case where the input signal is a standard signal which satisfies the NTSC standard and the case where the input signal is a non-standard signal which does not satisfy the relationship of frequency interleaving such as VTR. In order to control the video signal processing system, a non-standard signal detection circuit for automatically determining whether an input signal is a standard signal or a non-standard signal is required.

FIG. 2 shows a conventional configuration of the non-standard signal detection circuit. 7, a burst lock PLL for generating a burst lock clock ckb based on the burst signal of the input signal a;
Is a line lock PLL that generates a line lock clock ckh based on the horizontal sync separation signal of the input signal a, and 9 is a vertical cycle dividing pulse that generates pulses vb and vh obtained by dividing the input clocks ckb and ckn into a vertical cycle. The generation unit 10 is a phase comparator that compares the phase of the pulse vb obtained by dividing the burst lock clock ckb into a vertical cycle and the pulse vh obtained by dividing the line lock clock ckh into a vertical cycle. FIG. 3 shows the timing of the pulses vb and vh at this time.

If the input signal is a standard signal,
For a stable signal that satisfies the NTSC standard, the phases of the vertical period frequency dividing pulse vb created from the burst lock clock ckb and the vertical period frequency dividing pulse vh created from the line lock clock ckh almost match, and the phase difference g is extremely large. It becomes a small value. On the other hand, when the input signal is a VTR, the relationship between the subcarrier frequency and the horizontal scanning frequency does not satisfy the equation (1) and does not satisfy the NTSC standard due to the jitter of the tape running system. As a result, the phase difference g has a large value. Accordingly, the phase difference g between the vertical cycle frequency dividing pulse vb created from the burst lock clock ckb and the vertical cycle frequency dividing pulse vh created from the line lock clock ckh is detected, and when the phase difference g becomes larger than a certain amount. It can be determined as a non-standard signal. As non-standard signal sources, there are game machines including NES in addition to VTRs.

In order to perform the non-standard signal detection, a determination is made on the magnitude of the phase difference g between the vertical cycle divided pulse vb created from the burst lock clock ckb and the vertical cycle divided pulse vh created from the line lock clock ckh. It is necessary to set a threshold value for In the case of a home VTR, the magnitude of the phase difference g between the vertical period dividing pulses vb and vh is about 500 to 600 nsec due to the jitter of the tape running system. Therefore, it is necessary to set a value smaller than this jitter amount,
Generally, a determination threshold for detecting a non-standard signal is set at a position where the magnitude of the phase difference g is 100 to 200 nsec. For example, when a 4 fsc (14.3 MHz) burst lock clock is used to generate the vertical cycle divided pulse vb, the line lock clock vertical cycle divided pulse vh is ± 1 ck with respect to the burst lock clock vertical cycle divided pulse vb. If it deviates by more than (± 70 nsec), it is determined as a non-standard signal.

Here, if the deviation is more than ± 1 ck in the vertical cycle, it is determined that the signal is a non-standard signal. Therefore, the detection sensitivity is quite severe. .

[Problems to be solved by the invention]

Since the conventional non-standard signal detection circuit is configured as described above, the detection sensitivity must be set high to determine that the signal source, such as a VTR, is a non-standard signal. However, there is a problem that erroneous determination for determining a non-standard signal easily occurs due to noise or the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a non-standard signal detection circuit that is resistant to noise and that can perform stable determination in which erroneous determination is extremely unlikely to occur. Aim.

[Means for solving the problem]

The non-standard signal detection circuit according to the present invention includes a horizontal cycle counter for counting the number of system clocks in one horizontal cycle, detects a horizontal jitter amount in one line, and adds a jitter amount in each line, In this method, the amount of jitter in one field is obtained, and non-standard signal detection is performed by determination using the value.

[Action]

Since the non-standard signal detection circuit according to the present invention detects the amount of horizontal jitter in one line and adds the amount of jitter in each line to determine the amount of jitter in one field, it is possible to obtain a large value once per vertical cycle. It is possible to perform non-standard signal detection based on this value.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

Generally, in the case of a VTR, the amount of jitter in one horizontal scanning line is about 60 to 140 nsec with respect to the NTSC standard value. On the other hand, when the jitter of the VTR is observed in the vertical cycle, the jitter amount of the line-lock clock vertical cycle divided pulse is about the same as the stable burst lock clock vertical cycle divided pulse as described in the section of the related art. It is about 500 to 600 nsec. As described above, in the case of the VTR, the amount of jitter in the vertical cycle is not so large as compared with the amount of jitter in one horizontal scanning cycle due to a factor that the jitter of each line is offset in both the positive and negative directions. Therefore, the present invention focuses on the jitter in one horizontal scanning period, detects the amount of jitter, and adds the amount of jitter in each line in the field.

FIG. 1 shows the configuration of a non-standard signal detection circuit according to an embodiment of the present invention. In FIG. 1, 1 is a horizontal cycle counter, 2 is a reference count value holding unit, 3 is a subtractor, 4 is an absolute value conversion circuit, 5 is an adder in a field, and 6 is a comparator.

 Next, the operation will be described.

The horizontal period counter 1 counts the number of clocks in each horizontal scanning line. As the clock signal ck, for example, a burst lock clock (or line lock clock) 4fsc (14.3 MHz) is used, and a count operation for resetting each line by the horizontal synchronization signal h is executed. Thus, one horizontal scanning cycle is detected. The reference count value holding unit 2 is a unit that holds a count value corresponding to a standard signal satisfying the NTSC standard. The burst lock clock 4f
When sc (14.3 MHz) is used as the clock signal ck of the horizontal cycle counter 1, one horizontal scanning cycle is 910 ck, and the reference count value held by the reference count value holding unit 2 is 910. The subtractor 3 subtracts the output value of the horizontal cycle counter 1 and the output value of the reference count value holding unit 2.

The next absolute value conversion circuit 4 converts the subtraction value into an absolute value to detect the amount of jitter in one horizontal scan. The next intra-field adder 5 adds the amount of jitter in each horizontal scanning line output from the absolute value conversion circuit 4 to calculate the amount of jitter in one field. Using the jitter amount obtained once in the horizontal cycle in this way, the comparator 6
Is determined based on a certain threshold value, and when the amount of jitter output from the intra-field adder 5 becomes larger than the threshold value, the signal is determined to be a non-standard signal, and a non-standard signal n is output.

Here, the jitter amount in one horizontal cycle is 60 nsec to 140 nsec with respect to the standard value of the NTSC standard, so that when counted with the burst lock clock 4fsc (14.3 MHz), the jitter amount is 0 to 2 ck. Therefore, if the amount of jitter detected in one horizontal cycle is added within a field to obtain one amount of jitter in a vertical cycle, a considerably large amount of jitter can be obtained. As a result, the threshold value for non-standard signal determination can be set high, the noise margin increases, and the frequency of erroneous determination that a non-standard signal is determined when a standard signal is input can be greatly reduced.

〔The invention's effect〕

As described above, according to the present invention, the amount of jitter detected in one horizontal period is added in a field to obtain a large amount of jitter once in one vertical period. This makes it possible to increase the noise margin, and to greatly reduce the frequency of erroneous determination of a non-standard signal due to noise when a standard signal is input.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a non-standard signal detection circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration of a conventional non-standard signal detection circuit, and FIG. FIG. 9 is a diagram illustrating waveforms of a pulse and a line lock clock vertical period frequency dividing pulse. 1 is a horizontal period counter, 2 is a reference count value holding unit, 3 is a subtractor, 4 is an absolute value circuit, 5 is an adder in a field, and 6 is a comparator. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] An input signal mounted on a digital television receiver is a standard signal satisfying the NTSC standard.
A non-standard signal detection circuit for determining whether the signal is a non-standard signal that does not satisfy a standard, a horizontal cycle counter for counting the number of clocks in one horizontal scanning cycle, and a subtraction for subtracting the output of the counter from a reference count value Means for detecting an amount of jitter with respect to the NTSC standard value in one horizontal scanning period, and an adder for converting the output of the absolute value circuit into one field. An intra-field adder for determining the amount of jitter in one field period, and performing a threshold process on the amount of jitter in the one-field period, which is the output of the in-field adder, to determine whether the amount of jitter is larger than a threshold value. A non-standard signal detection circuit, comprising: a comparator for determining a signal.