JP2997013B2 - Vertical synchronous playback circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing circuit for reproducing a vertical synchronizing signal of a transmitted television signal by eliminating pulse noise on a receiving side.

(Summary of the Invention) The present invention relates to a vertical synchronizing signal reproducing circuit for a television signal, wherein an integrator circuit for detecting a vertical synchronizing signal after a synchronizing separation circuit on a receiving side is reset by a reset having half the horizontal synchronizing cycle. Resets with a pulse, compares it with a predetermined set level, compares the detected vertical synchronization pattern with a reference vertical synchronization pattern stored in memory in advance, and outputs a vertical synchronization signal only when matching with the reference pattern is obtained are doing.

By doing so, a vertical synchronizing signal reproducing circuit capable of stably reproducing a vertical synchronizing signal from a video signal containing pulse noise is provided.

(Prior Art) Since televisions perform decomposition and synthesis of images by scanning, it is necessary to synchronize the scanning correctly on the transmitting side and the receiving side. What plays this role is the synchronization signal,
The synchronization signal includes a horizontal synchronization signal and a vertical synchronization signal, and these are multiplexed with the video signal. The synchronization signal is multiplexed with the opposite polarity to the normal video signal so as to be easily separated from the video signal. On the receiving side, the signal is separated from the video signal by using a difference in amplitude by a sync separation circuit. The horizontal synchronizing signal and the vertical synchronizing signal are easily separated from each other.The pulse width of the vertical synchronizing signal is much wider than that of the horizontal synchronizing signal. The vertical synchronization timing is extracted using the amplitude difference of the continuous output signal. On the other hand, the horizontal synchronizing signal is separated by a differentiating circuit, and the above is a general conventional example of a synchronous reproducing circuit.

(Problems to be Solved by the Invention) The synchronizing signal as described above is tentatively devised so as not to be easily affected by noise when multiplexed with the video signal and transmitted. However, pulse noise is mixed in the video signal. In this case, the conventional vertical synchronization reproducing circuit has a drawback that a vertical synchronization signal is erroneously detected on the receiving side and the screen is displaced up and down.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a vertical synchronizing reproduction circuit capable of stably reproducing a vertical synchronizing signal even if such pulse noise is mixed in a video signal.

(Means for Solving the Problems) In order to achieve this object, a vertical synchronization reproduction circuit according to the present invention includes a synchronization separation circuit and an integration for integrating its output while resetting its output with a reset pulse having a half cycle of a horizontal synchronization cycle. A comparator circuit for comparing an output of the integrating circuit with a predetermined set level; a pattern comparing circuit for comparing a pattern of an output signal of the comparator circuit with a reference vertical synchronization pattern stored in a memory; A horizontal synchronizing pulse in which a memory storing a vertical synchronizing pattern and a vertical reset signal and a horizontal synchronizing signal which are output from a pattern comparing circuit when the compared patterns match are input and a vertical synchronizing signal is output by them. And a counter circuit.

(Operation) According to the reproducing circuit of the present invention, when the receiving side separates the synchronizing signal from the video signal and passes the same through the integrating circuit, the integrating circuit is reset with a reset pulse having a half of the horizontal synchronizing cycle, and the output is reset. Since it is compared with a predetermined set level, the vertical synchronization and pulse noise can be separated for the time being, and the detected vertical synchronization pattern is further compared with a reference vertical synchronization pattern stored in a memory on the receiving side, and the reference pattern is compared. Since the vertical synchronizing signal is output only when the pattern matching is performed, the vertical synchronizing signal can be stably reproduced from the video signal containing pulse noise.

(Example) Hereinafter, the present invention will be described in detail by way of examples with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention which is not limited to this, and FIG. 2 shows the waveforms of the respective components.

Composite video signal a including pulse noise in sync separation circuit 1
(Only the vertical synchronization part is shown in FIG. 2) is separated into a synchronization signal b. The synchronizing signal b includes noise corresponding to the pulse noise included in the input signal a (only the pulse noise having the same polarity as the signal at that portion is a signal that has been a problem in the conventional example).

Although the synchronizing signal b is integrated by the integrating circuit 2, the integrating circuit is reset by a reset pulse d having a half cycle of the horizontal synchronizing cycle, and an output signal waveform c of the integrating circuit is obtained. Next, the output signal c is processed by the comparator circuit in such a manner as to be sliced at the set level (dashed line), and a signal portion above the slice level is a digital signal one level, and a signal portion not exceeding the slice level is a digital signal one level. The digital signal zero level is output, and the vertical synchronization signal e after the comparator is obtained.

The pattern of the vertical synchronizing signal e is then compared with a digital reference vertical synchronizing pattern f stored in the memory 5 in advance by the pattern comparing circuit 4, and when both patterns match, the vertical reset signal g is sent from the pattern comparing circuit 4. Is output. When the pattern of the vertical synchronization signal e does not completely match the reference vertical synchronization pattern f, the vertical reset signal g is not output.

The vertical reset signal g is input to the reset input of the horizontal synchronization pulse counting circuit 6. The horizontal synchronizing pulse counting circuit 6 counts the horizontal synchronizing signal h and outputs a reproduced vertical synchronizing signal in this circuit. The phase of the output vertical synchronizing signal is determined by the vertical reset signal g. Further, since the horizontal synchronization pulse counting circuit 6 outputs the vertical synchronization signal at a predetermined interval as the horizontal synchronization pulse count even if the vertical reset signal is not input, a short-time malfunction of this kind of vertical synchronization reproduction circuit is allowed.

Although the embodiment according to the present invention has been described above,
It will be obvious to those skilled in the art that the present invention can be variously modified and changed within the scope of the claims.

(Effects of the Invention) As described above in detail, in the vertical synchronization reproducing circuit of the present invention, if the pattern of the vertical synchronization signal e and the reference vertical synchronization signal pattern f are not completely coincident with each other, the vertical reset signal g Is not output, and the phase of the reproduced vertical synchronizing signal remains the phase dependent on the horizontal synchronizing pulse count circuit.

Thus, when pulse noise enters the video signal in the conventional vertical synchronizing reproduction circuit, for example, the vertical synchronizing signal becomes 2
It is possible to eliminate the occurrence of jitter on the screen due to malfunction such as repeated playback.

[Brief description of the drawings]

 FIG. 1 is a block diagram showing the construction of an embodiment of the present invention, and FIG. DESCRIPTION OF SYMBOLS 1 ... Synchronization separation circuit, 2 ... Integration circuit 3 ... Comparator circuit, 4 ... Pattern comparison circuit 5 ... Vertical synchronization pattern memory 6 ... Horizontal synchronization pulse count circuit.

Continuation of the front page (56) References JP-A-57-184372 (JP, A) JP-A-59-33611 (JP, A) JP-A-62-72279 (JP, A) JP-A-63-314075 (JP) , A) JP-A-2-131081 (JP, A) JP-A-3-29573 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (1)

(57) [Claims] 1. A reproducing circuit for receiving a transmitted television signal and reproducing a vertical synchronizing signal of the television signal, the reproducing circuit comprises a synchronizing separation circuit and an output from the synchronizing separation circuit. An integration circuit that resets and integrates with a reset pulse, a comparator circuit that compares the output of the integration circuit with a predetermined set level, a pattern of an output signal of the comparator circuit, and a reference vertical synchronization pattern stored in a memory. And a memory in which the reference vertical synchronization pattern is stored, and a vertical reset signal and a horizontal synchronization signal output from the pattern comparison circuit when the compared patterns match. A horizontal synchronizing pulse counter circuit for outputting a vertical synchronizing signal therefrom. Playback circuit.