JP2604424B2 - Sync separation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit installed in a television receiver.

(Prior Art) In a color television broadcasting system, in order to match the resolution scanning of the camera on the broadcasting station side and the assembly scanning on the receiver side, the video signal for one horizontal scanning line and the video signal for one frame are respectively set. The horizontal synchronization signal and the vertical synchronization signal are superimposed,
A sync separation circuit for separating the horizontal and vertical sync signals from the video signal is provided in the receiver.

Conventionally, the above-mentioned sync separation circuit first separates a composite sync signal including a horizontal / vertical sync signal and a video signal by using an amplitude difference between the two, and then, separates the horizontal sync in the separated composite sync signal. / Vertical synchronization signal is configured to be separated using the frequency difference between the two. Each separated sync signal is
In order to establish phase stabilization under detection errors that may occur intermittently, a configuration is supplied to the subsequent display circuit etc. as a timing signal for display scanning via each phase locked loop It has become.

(Problems to be Solved by the Invention) Recently, along with the development of a high-definition television system which has been progressing at a rapid pace, the development of a ghost removal system for making it effective has been progressing at a rapid pace. In a typical ghost removal method, a broadcast side transmits a television signal in which a predetermined reference waveform is inserted at a predetermined position in a television signal, and the receiver side determines a ghost occurrence state from the degree of distortion of the reference waveform. It is configured to detect.

In order to detect this reference waveform from a predetermined position in a received television signal with high accuracy, it is necessary to perform high-precision synchronization separation and create a timing signal based on the separation. Typically, it requires one digit or more higher precision than a display timing signal created by a conventional synchronous separable circuit.

As described above, it is difficult to realize a timing accuracy higher than that of the related art by one digit or more under a situation where the erroneous detection of the synchronization signal caused by the ghost occurs frequently by simply extending the related art.

In particular, in the synchronization protection unit of the conventional synchronization separation circuit, if the detection of the synchronization signal fails, the synchronization processing by hunting is started immediately, so that the responsiveness is high, but frequent occurrence of erroneous detection of the synchronization signal due to the effect of ghost is high. Therefore, it is considered that the timing is likely to be unstable and high timing accuracy cannot be obtained.

(Means for Solving the Problems) The sync separation circuit according to the first aspect of the present invention comprises a dot having a frequency four times (4f sc) the color subcarrier frequency created based on the color burst signal extracted from the received television signal. A dot counter for counting frequency clock signals,
Selects a dot decoder that decodes the count value of the dot counter and outputs various timing signals, and a signal indicating the last dot position of one line output from the dot decoder or a horizontal synchronization detection signal detected in the preceding stage. Clearing means for clearing the dot counter with any of the masked horizontal synchronization detection signals, which has been masked, a leak integration circuit receiving the logical product of the window pulse output from the dot decoder and the horizontal synchronization detection signal, and a leak integration circuit A horizontal synchronization protection circuit having mask control means for validating the mask of the horizontal synchronization detection signal when the integrated value of the circuit is equal to or greater than a predetermined value.

The synchronization separation circuit according to the second invention includes a line counter that counts a clock signal of a line frequency created based on a synchronization signal extracted from a received television signal, and a line counter that decodes a count value of the line counter to perform various operations. And a masked frame pulse which selectively masks a signal indicating the last line position for one frame output from the line decoder or a frame pulse supplied from the preceding vertical synchronization detection unit. Clearing means for clearing the line counter in any one of the above, a leaky integration circuit for receiving the logical product of the frame pulse output from the line decoder and the frame pulse supplied from the preceding vertical synchronization detector, Supplied from the preceding vertical synchronization detector when the integral value is equal to or greater than the predetermined value A mask to Remuparusu includes a frame synchronization protection unit and a mask control unit to enable.

(Operation) According to the synchronization separation circuit of the present invention, even if some erroneous detection of the synchronization signal occurs, the synchronization processing by the hunting of the synchronization protection circuit is not started within the period determined by the time constant of the leaky integrator. Effectively avoid a decrease in accuracy due to ghost effects.

 Hereinafter, the operation of the present invention will be described in detail with examples.

(Embodiment) FIG. 1 is a block diagram showing a configuration of an embodiment of a sync separation circuit of the present invention.

This synchronization separation circuit includes an analog synchronization separation unit 1, a clock generation unit 2, an A / D conversion unit 3, a color burst removal unit 4,
It comprises a horizontal synchronization detection section 5, a vertical synchronization detection section 6, a horizontal synchronization protection section and a frame synchronization protection section 8.

As shown in FIG. 2, the analog sync separation section 1 includes a low-pass filter circuit 11, a composite sync signal separation circuit 12, an AFC circuit 1
3, vertical synchronization signal separation circuit 14 and timing generation circuit 15
It is composed of This analog sync separation circuit 1
The horizontal synchronizing signal H and the vertical synchronizing signal V are separated from the analog composite video signal supplied from the input terminal IN and supplied to a subsequent display unit for display control, and a timing generator composed of a monostable multivibrator or the like is provided. The circuit 15 generates a burst flag and a clamp pulse, and supplies them to the clock generator 2 and the A / D converter 3 shown in FIG.

The clock generation unit 2 shown in FIG.
The color burst signal is extracted from the analog video signal on the input terminal IN using the burst flag generated in step 4
Generate a clock signal with double frequency (4f sc)
It is supplied to the / D conversion unit 3 and other circuit parts.

The A / D converter 3 performs pedestal clamping on the analog composite video signal on the input terminal IN using the clamp pulse generated by the analog sync separation unit 1, and generates the 4f sc generated by the clock generator 2 while performing pedestal clamping. It is converted into a digital composite video signal using the clock signal.

The color burst removing section 4 includes a one-line delay circuit 4a and an adder circuit 4b. The color burst elimination unit 4 outputs the output of the A / D conversion unit 3 including the color burst CB as shown in FIG.
The digital composite video signal from which the color burst signal has been removed as shown in FIG. 3 (B) is generated by adding the one delayed by I do.

A horizontal synchronization detecting unit 5 for binarizing the digital composite video signal from which the color burst has been removed;
A falling detection circuit 5b detects the falling point of the output of the binarization circuit in synchronization with a clock signal having a frequency of 4fsc. The binarizing circuit 5a compares the composite video signal from which the color burst has been removed as illustrated in FIG. 3 (B) with a predetermined reference value Lref, and generates a binary signal according to the magnitude relationship. By setting the reference Lref near the pedestal level of the composite video signal, a signal having a width substantially equal to the horizontal synchronization signal is detected as illustrated in FIG. 3 (C). This signal falls in synchronism with the horizontal synchronizing signal as shown in FIG. 3 (D) by detecting the falling in synchronism with the clock signal having the frequency of 4fsc in the falling detecting circuit 5b. The signal is converted into a horizontal synchronization detection signal having a width of one clock signal and supplied to the horizontal synchronization protection circuit 7.

The output of the binarization circuit 5a of the horizontal synchronization detector 5 includes information indicating the position of the vertical synchronization signal in addition to the information indicating the position of the horizontal synchronization signal described above. However, if the output of the binarization circuit 5a is used to detect a vertical synchronization signal, the output of the original signal and the one-line delay signal is performed in the color burst removal unit 4 in the preceding stage. Synchronization may be disrupted during the vertical flyback period.

That is, as shown in FIG. 4, the appearance of the vertical synchronizing signal and the equalizing pulse in the vertical blanking period is the waveform (A), and the waveform obtained by delaying this by one line becomes the waveform (B). Accordingly, the output of the color burst removing unit 4 obtained by adding the waveforms (A) and (B) and dividing by 2 becomes a waveform (C),
An intermediate level portion appears at the head of the equalization pulse.
If the intermediate level portion of the waveform (C) is to be binarized by the binarization circuit 5a of the horizontal synchronization detector 5, the binarized signal will vary between "1" and "0". It causes false detection of falling.

Therefore, as will be described later, the output during the vertical retrace period from the horizontal synchronization detection unit 5 is invalidated by the horizontal synchronization protection unit 7 at the subsequent stage, and the position detection of the vertical synchronization signal is performed by the horizontal synchronization detection unit 5 Is performed in the vertical synchronization detection unit 6 separately provided.

The vertical synchronization detector 6 includes a binarizing circuit 6a, a low-pass filtering circuit 6b, a latch circuit 6c, and a selection latch circuit 6d.

The binarizing circuit 6a binarizes the digital composite video signal output from the A / D converter 3 by comparing it with a predetermined reference level Lref near the pedestal level. The binarized signal is supplied to the latch circuit 6c while high-frequency components caused by a color burst signal and the like are removed by the low-pass filtering circuit 6b. A clock signal 2Hck having a frequency twice the horizontal synchronization frequency is supplied to a clock input terminal of the latch circuit 6c. The phase of the clock signal 2Hck is set so that it appears in the first half and the second half of each line, as shown in FIG. 5 (A). Therefore, during the appearance period of the video signal, the latch circuit 6c keeps latching the high signal.

On the other hand, as shown in FIG. 5B, when an equalizing pulse appears at the start of the vertical blanking period, the latch circuit 6c starts latching the low signal. As a result, the output of the latch circuit 6c falls to low in synchronization with the start of the vertical blanking period as shown in FIG. 5 (C). The line width immediately before the start of the vertical retrace period is one line as shown in FIG. 5B for an even field, but is half as shown in FIG. 5D for an odd field. The width of the line.

As a result, when the output of the latch circuit 6c falls to low, a time difference of a half line is generated depending on whether the field is an odd field or an even field. Select latch circuit 6d
Outputs a frame detection signal generated in a frame cycle by selectively latching only one of the outputs (of an odd field) using the fact that the output of the preceding latch circuit 6c is alternately shifted by one clock cycle. I do. Such a selection latch circuit 6d includes a counter section of the clock signal Hck and a latch circuit of a preceding stage when the count value reaches a predetermined value.
And a latch section for latching the output of 6c.

FIG. 6 is a block diagram showing the configuration of the horizontal synchronization protection section 7 of FIG.

The horizontal synchronization protection unit 7 includes various logic gates such as an inverter 21 and an AND gate 22, a dot counter 24, a decoder 25, a flip-flop 26, a leaky integrator 28, and a binarization circuit 29, and operates with positive logic. I do.

The horizontal synchronization detection signal output from the horizontal synchronization detection section 5 is supplied to one input terminal of AND gates 22 and 27 via the input terminal 11 and the inverter 21. The dot counter 24 counts the clock signal of the dot (pixel) frequency of 4fsc supplied from the input terminal I2 while being cleared by the high signal supplied from the OR gate 23.
The decoder 25 decodes the count value of the dot counter 24 and outputs various timing signals. 909 which is one of various timing signals output from this decoder
The decode signal is sent to the dot counter via the OR gate 23.
It is supplied to the clear terminal 24 and the count value of the dot counter 24 is returned from the maximum value 909 to 0. That is, the dot counter 24 is cleared at a cycle of one line.

Another timing signal output from the decoder 26 is 4f
It is held in the flip-flop 26 in synchronization with the clock signal of the sc, and is supplied to the corresponding output terminal as the H timing signal, the clock signal 2Hck, and the clock signal Hck. One of the timing signals is supplied to the other input terminal of the AND gate 27 as a window pulse W for the horizontal synchronization detection signal supplied to one input terminal of the AND gate 27 via the input terminal I1. The width of the window pulse W is set to about 5 times the width of the horizontal synchronization detection signal in order to absorb fluctuations of the horizontal synchronization detection signal due to ghosts and the like.

Therefore, when the horizontal synchronization detection signal appears almost simultaneously with the window pulse W output from the flip-flop 26 in one line cycle, a high signal is output from the AND gate 27. This high output is supplied to the leakage integrator 28 to supplement the integrated voltage value reduced by the leakage. Binarization circuit 29
Compares the voltage value of leaky integrator 28 with a predetermined value, and raises the output to high when the former falls below the latter. With the rise of this output, the AND gate 22 is opened and hunting is started. In the hunting mode, the dot counter 24 is cleared in synchronization with the horizontal synchronization detection signal supplied from the input terminal I1 through the AND gate 22 and the OR gate 23.

With the signal in the hunting mode, a high signal starts to be output again from the AND gate 27, and when the leakage integration voltage exceeds a predetermined value, the output of the binarization circuit 29 falls to low. As a result, the horizontal synchronization detection signal is blocked by the AND gate 22, the dot counter 24 is cleared by the 909 decode signal from the decoder 25, and the horizontal synchronization protection unit 7 shifts to the free running mode.

As described above, even when a high signal is not output from the AND gate 27 due to erroneous detection or failure of detection of the horizontal synchronization signal, the hunting of the horizontal synchronization protection circuit is performed during the period determined by the time constant of the leaky integrator 28 and the like. Is not started. Therefore, the problem that the operation becomes unstable due to the frequent start of the hunting based on the erroneous detection of the synchronization signal and the timing accuracy is reduced is solved.

It should be noted that the vertical synchronization detector 8 shown in FIG.
The signal VBLK supplied to one of the input terminals falls low during the vertical blanking period. As a result, the transition to the hunting mode is prohibited during the vertical flyback period, and the already started hunting mode is interrupted. This is because, as already described with reference to FIG. 4, erroneous detection of the horizontal synchronizing signal occurs within the vertical blanking period due to the signal processing for removing the color burst. Is to be prevented from being disturbed.

FIG. 7 is a block diagram showing the configuration of the vertical synchronization protection section 8 of FIG.

This vertical synchronization protection unit 8 is the same as the horizontal synchronization protection unit 7 in FIG.
Similarly, includes various logic gates such as an inverter 31 and an AND gate 32, a line counter 34, a decoder 35, a flip-flop 36, a leaky integrator 38, and a binarization circuit 39,
Operates with positive logic.

The frame pulse output from the above-mentioned vertical synchronization detection unit 6 is AND gated through the input terminal I1 and the inverter 31.
One of the input terminals 32 and 37 is supplied as an external frame pulse. The line counter 34 receives the input signal I2 while being cleared by the high signal supplied from the OR gate 33.
The clock signal Hck of the line frequency supplied from is counted. The decoder 35 decodes the count value of the line counter 34 and outputs various timing signals. A 524 decode signal corresponding to one of various timing signals output from the decoder 35 is supplied to the clear terminal of the line counter 34 via the OR gate 33, and returns the count value of the line counter 34 from the maximum value 524 to 0. . That is, the line counter 34 is cleared in synchronization with one frame.

Other timing signals output from the decoder 36 are held in the flip-flop 36 in synchronization with the clock signal Hck, and are supplied to the horizontal synchronization protection unit 7 or the VBLK signal, the frame timing signal, and the field timing signal. Is supplied to the corresponding output terminal. One of the timing signals is supplied to one input terminal of the AND gate 37 as an internal frame pulse. The other input terminal of the AND gate 37 is connected to the input terminal 11 and the inverter 31.
The external frame pulse is supplied from the vertical synchronization detecting unit 6 through the above.

Therefore, if the internal frame pulse output from the flip-flop 36 and the external frame pulse are synchronized in one frame period, a high signal is output from the AND gate 37, and the voltage value of the leakage integrator 38 reduced by the leakage is reduced. Be replenished. When the leakage integration voltage value falls below a predetermined value due to the loss of synchronization between the two frame pulses, the output of the binarization circuit 39 rises to high, the AND gate 32 is opened, and hunting is started. In this hunting mode, the input terminal
The line counter 34 is cleared in synchronization with an external frame pulse supplied from I1 through the gates 32 and 33.

With the signal in the hunting mode, a high signal is again output from the AND gate 37, and when the leakage integration voltage value exceeds a predetermined value, the output of the binarization circuit 39 falls to low. As a result, the external frame pulse is blocked by the AND gate 32, and the line counter 34 is cleared by the decoder.
This is performed only by the 524 decode signal from 35, and the vertical synchronization protection section 8 shifts from the hunting mode to the free running mode.

As described above, even when a high signal is not output from the AND gate 37 due to erroneous detection or detection failure of the vertical synchronization signal, the hunting of the vertical synchronization protection circuit is performed during the period determined by the time constant of the leaky integrator 38 and the like. Is not started. Therefore, the problem that the operation becomes unstable due to the frequent start of the hunting based on the erroneous detection of the synchronization signal and the timing accuracy is reduced is solved.

FIG. 8 is a block diagram showing a configuration of another embodiment of the sync separation circuit of the present invention.

The sync separation circuit of this embodiment uses a clamp pulse supplied to the A / D converter 3 of the sync separation circuit of FIG. 'Shows the configuration created. Therefore, the same reference numerals as in FIG. 1 denote the same components in the circuit in FIG. 2 as those in the circuit in FIG. 1, and a duplicate description of these common components will be omitted.

The horizontal synchronization protection section 7 'in FIG. 8 adds a function of outputting a clamp pulse to the decoder 25 in the horizontal synchronization protection section 7 of the previous embodiment shown in FIGS. At the same time, the configuration is such that the output of the binarization circuit 29 is output to the outside as a mode display signal. Also, the vertical synchronization protection section 8 'in FIG. 8 outputs the output of the binarization circuit 39 in the vertical synchronization protection section 8 of the previous embodiment shown in FIGS. 1 and 7 as a mode display signal to the outside. The configuration has been changed to output.

The clamp pulse output from the horizontal synchronization protection section 7 'and the VBLK signal output from the frame synchronization protection section 8' are
The input is supplied to each of two non-inverting input terminals of the AND gate 9. The mode display signals output from the horizontal synchronization protection section 7 'and the vertical synchronization protection section 8' are supplied to the two inverting input terminals of the 4-input AND gate 9, respectively. As a result, the clamp generated by the horizontal synchronization protection unit 7 'under the condition that neither the horizontal synchronization protection unit 7' nor the vertical synchronization protection unit 8 'is in the hunting mode and within the vertical retrace period. The pulse is supplied to the A / D converter 3, and the pedestal clamp is performed. As described above, the pedestal clamp is prohibited during the vertical flyback period.
This is because the ghost component disappears with the disappearance of the video signal during the vertical blanking period, and as a result, the pedestal level may greatly change.

FIG. 9 is a block diagram showing the configuration of still another embodiment of the synchronization separation circuit of the present invention, wherein 41 is an analog synchronization separation section, 42 is a clock generation section, 45 is a horizontal synchronization detection section, and 46 is a vertical synchronization section. A detection unit, 47 is a horizontal synchronization protection unit, and 48 is a vertical synchronization protection unit.

The analog sync separation unit 41 slices the analog composite video signal supplied to the input terminal IN while passing the waveform through a low-pass filtering circuit to dull the waveform and then clamping the tip of the horizontal sync signal. By performing SYNC chip slice processing, a composite synchronization signal is separated from the video signal, and supplied to the horizontal synchronization detection unit 45 and the vertical synchronization detection unit 46. The analog sync separation unit 41 generates a burst flag used for extracting a color burst from the composite video signal in parallel with the sync separation process, and generates a clock flag.
Supply 42.

The horizontal synchronization detection section 45 has a configuration in which the same function as the digital horizontal synchronization detection section 5 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, the analog-type horizontal synchronization detection unit 45 binarizes the analog composite synchronization signal supplied from the analog synchronization separation unit 41, and detects the falling point in synchronization with the 4fsc clock signal to detect the clock. A horizontal synchronization detection signal having a width of one cycle of the signal is generated and output to a horizontal synchronization protection circuit 47 at a subsequent stage.

The vertical synchronization detector 46 has a configuration in which the same function as the digital vertical synchronization detector 6 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, the analog horizontal synchronization detection unit 46 binarizes the analog composite synchronization signal supplied from the analog synchronization separation unit 41, passes it through a low-pass filtering circuit, latches it in synchronization with the clock signal 2Hck,
The latch output is selectively latched in one jump in synchronization with the clock signal Hck to generate a vertical synchronization detection peripheral signal having a frame period, and supplies this to the subsequent frame synchronization protection circuit 48 as an external frame pulse.

The horizontal synchronization protection circuit 47 has substantially the same configuration as the horizontal synchronization protection circuit 7 shown in FIGS. 1 and 6, and performs almost the same operation. The vertical synchronization protection circuit 48 has substantially the same configuration as the vertical synchronization protection circuit 8 shown in FIGS. 1 and 7, and performs almost the same operation. However,
A frame synchronization protection circuit different from the synchronization separation circuit of FIG.
At 48, no VBLK signal is created, and at the horizontal synchronization protection circuit 47, a hunting operation is performed even during the vertical retrace period.

FIG. 10 is a block diagram showing the configuration of another embodiment of the sync separation circuit of the present invention.
Is a clock generation unit, 55 is a horizontal synchronization detection unit, 56 is a vertical synchronization detection unit, 57 is a horizontal synchronization protection unit, and 58 is a vertical synchronization protection unit.

The analog sync separation unit 51 slices the analog composite video signal supplied to the input terminal IN by passing it through a low-pass filtering circuit, dulling the waveform, and then clamping the tip of the horizontal sync signal. By performing the SYNC chip slice processing, the composite synchronization signal is separated from the video signal and supplied to the horizontal synchronization detection unit 55. The analog sync separation unit 15 detects a vertical retrace period by passing the composite sync signal separated from the video signal through a low-pass filter circuit, and detects a vertical sync period within the detected vertical retrace period. Feed to separation 56. The analog sync separation unit 51
In parallel with the synchronization separation processing, a burst flag used for extracting a color burst from the composite video signal is generated and supplied to the clock generation unit 52.

The horizontal synchronization detecting section 55 has a configuration in which the same function as that of the digital horizontal synchronization detecting section 5 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, the analog horizontal synchronizing detection section 55 binarizes the analog composite synchronizing signal supplied from the analog synchronizing / separating section 51, and detects the falling point in synchronization with the 4fs clock signal to thereby generate a clock. A horizontal synchronization detection signal having a width of one cycle of the signal is generated and output to the horizontal synchronization protection circuit 57 at the subsequent stage.

The vertical synchronization detecting section 56 has a configuration in which the same function as the digital vertical synchronization detecting section 6 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, the analog horizontal synchronization detection unit 56 binarizes the synchronization detection signal supplied from the analog synchronization separation unit 51, latches it in synchronization with the clock signal 2Hck, and outputs the latched output to the clock signal Hck.
By selectively latching one jump at a time in synchronism with the frame synchronization, a vertical synchronization detection peripheral signal of frame synchronization is generated, and this signal is supplied to the subsequent frame synchronization protection circuit 58 as an external frame pulse.

The horizontal synchronization protection circuit 57 has almost the same configuration as the horizontal synchronization protection circuit 7 shown in FIGS. 1 and 6, and performs almost the same operation. The vertical synchronization protection circuit 58 has substantially the same configuration as the vertical synchronization protection circuit 8 shown in FIGS. 1 and 7, and performs almost the same operation. However,
A frame synchronization protection circuit different from the synchronization separation circuit of FIG.
At 58, no VBLK signal is created, and at the horizontal synchronization protection circuit 57, a hunting operation is performed even during the vertical retrace period.

FIG. 11 is a block diagram showing the configuration of still another embodiment of the sync separation circuit of the present invention. In this sync separation circuit, the components denoted by the same reference numerals as those of the sync separation circuit of FIG. 10 have the same configuration as the corresponding portions of the sync separation circuit shown in FIG. Therefore, a duplicate description thereof will be omitted.

In this synchronization separation circuit, a burst flag for extracting a color burst used in the clock generation unit 52 is output from the burst timing signal created by the horizontal synchronization protection unit 57 and the water-time synchronization protection unit 58 in the AND circuit 59. To
It is created from the logical product with the VBLK signal.

As described above, a configuration has been described in which hunting does not immediately start even if detection of a synchronization signal fails in both the horizontal and vertical synchronization protection circuits. However, in consideration of the timing accuracy and the pull-in speed at the time of out-of-synchronization, a conventional configuration in which hunting is started immediately in one of the horizontal and vertical directions can be adopted.

(Effects of the Invention) Since the synchronization separation circuit of the present invention has the above-described configuration, even if erroneous detection of a synchronization signal occurs to some extent, the hunting of the synchronization protection circuit occurs within a period determined by the time constant of the leaky integrator. Synchronization process has not started. As a result, the instability of the operation based on the erroneous detection of the synchronization signal due to the influence of ghost or the like can be effectively prevented, and the value of the timing which is higher by one digit or more than the timing accuracy for display created by the conventional synchronization separation circuit can be prevented. Timing accuracy has been achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the sync separation circuit of the present invention, FIG. 2 is a block diagram showing the configuration of the analog sync separation circuit of FIG. 1, FIG. 3, FIG. 6 is a waveform diagram for explaining the operation of the sync separation circuit of FIG. 1, FIG. 6 is a block diagram showing the configuration of the horizontal sync protection unit 7 of FIG. 1, and FIG. 7 is the vertical sync protection of FIG. FIG. 8 is a block diagram showing the configuration of another embodiment of the synchronization separation circuit of the present invention, and FIG. 9 is a block diagram showing the configuration of another embodiment of the synchronization separation circuit of the present invention. FIG. 10 is a block diagram showing a configuration of another embodiment of the sync separation circuit of the present invention, and FIG. 11 is a block diagram showing a configuration of still another embodiment of the sync separation circuit of the present invention. . 1, 41, 51 ... Analog sync separation section, 2, 42, 52 ... Clock generation section, 3 ... A / D conversion section, 4 ... Color burst removal section, 5, 45, 55 ... Horizontal sync detection Division, 6, 46, 56
…… Vertical sync detector, 7, 47, 57… Horizontal sync protector,
8, 48, 58 ... frame synchronization protection unit, 24 ... dot counter, 25 ... dot decoder, 28 ... leaky integrator, 34 ...
... Line counter, 35 ... Line decoder, 38 ... Leakage integrator.

Claims (2)

(57) [Claims] 1. A dot counter for counting a clock signal having a dot frequency four times the color subcarrier frequency generated based on a color burst signal extracted from a received television signal, and decoding a count value of the dot counter. A dot decoder that outputs various timing signals, and a masked horizontal synchronization detection that selectively masks a signal indicating the final dot position of one line output from the dot decoder or a horizontal synchronization detection signal detected in a preceding stage. Clear means for clearing the dot counter with any of the signals; a leak integration circuit receiving a logical product of the window pulse output from the dot decoder and the horizontal synchronization detection signal; Mask control means for enabling the mask of the horizontal synchronization detection signal when the value is equal to or greater than A synchronization separation circuit comprising a horizontal synchronization protection circuit having: 2. A line counter for counting a clock signal having a line frequency generated based on a synchronization signal extracted from a received television signal, and a line for decoding a count value of the line counter and outputting various timing signals. A line decoder which outputs a signal indicating a final line position of one frame output from the line decoder or a masked frame pulse which selectively masks a frame pulse supplied from a preceding vertical synchronization detection unit. A leak integration circuit that receives a logical product of a frame pulse output from the line decoder and a frame pulse supplied from the vertical synchronization detection unit, wherein the integration value of the leakage integration circuit is equal to or greater than a predetermined value. At the time of the frame pulse supplied from the vertical synchronization detection unit. A synchronization separation circuit, comprising: a frame synchronization protection unit having mask control means for enabling a mask.