JPH01300691A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To avoid the deterioration of the accuracy due to the effect of ghost by avoiding the synchronizing processing due to hunting of a synchronizing protection circuit for a period depending on the time constant of a leakage integration device even if more or less mis-detection of the synchronizing signal takes place. CONSTITUTION:The title circuit consists of an analog synchronizing separator section 1, a clock generating section 2, an A/D conversion section 3, a color burst eliminating section 4, a horizontal synchronizing detection section 5, a vertical synchronizing detection section 6, a horizontal synchronizing protection section 7 and a frame synchronization protection section 8. Even if a state of no high level signal outputted from an AND gate 27 due to a failure of detection or a mis-detection of a horizontal synchronizing signal takes place, the synchronizing processing due to hunting of the horizontal synchronization protection section 7 is not started within a period depending on the time constant or the like of a leakage integration device 28. Thus, unstable operation based on the mis-detection of the synchronizing signal due to the effect of ghost is prevented and the timing accuracy higher by the order of one digit or over than the timing accuracy for display formed by a conventional circuit is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization separation circuit installed in a television receiver.

(Prior Art) In a color television broadcasting system, in order to match the disassembly scanning of the camera on the broadcasting station side and the assembly scanning on the receiver side, each horizontal scanning line segment and one frame worth of video signal are A horizontal synchronization signal and a vertical synchronization signal are superimposed, and a synchronization separation circuit is installed in the receiver to separate these horizontal and vertical synchronization signals and a video signal.

Conventionally, the above-mentioned synchronization separation circuit first separates a composite synchronization signal including horizontal/vertical synchronization signals and a video signal by using the amplitude difference between the two, and then separates the horizontal and vertical synchronization signals in the separated composite synchronization signal. /Vertical synchronization signal is configured to be separated using the frequency difference between the two. Each separated synchronization signal is passed through a respective phase-locked loop to the subsequent stage as a timing signal for display scanning in order to establish phase stabilization in case of intermittent detection errors. It is configured to be supplied to display circuits, etc.

(Problems to be Solved by the Invention) Recently, as the development of high-definition television systems has progressed at a rapid pace, the development of ghost removal methods to make them effective has also progressed at a rapid pace. In a typical ghost removal method, the broadcasting side inserts a predetermined reference waveform at a predetermined point in the television signal and transmits it, and the receiver side detects the occurrence of ghosts based on the degree of distortion of this reference waveform. It is configured to detect.

In order to detect this reference waveform with high precision from a predetermined location in the received television signal, it is necessary to perform high-precision synchronization separation and create a timing signal based on this.Typically, conventional synchronization This requires more than an order of magnitude higher precision than the display timing signal created by a separation circuit.

As described above, it is difficult to achieve timing precision that is one order of magnitude higher than the conventional technique under the circumstances where erroneous detection of synchronization signals due to ghosts occurs frequently by simply extending the conventional technique.

In particular, in the synchronization protection section of a conventional synchronization separation circuit, synchronization processing by hunting is started immediately when a synchronization signal detection fails, so while the responsiveness is high, it also suffers from frequent false detection of synchronization signals due to the influence of ghosts. It is thought that it tends to become unstable and high timing accuracy cannot be obtained.

(Means for Solving the Problem) The synchronization separation circuit according to the invention of youngest brother 1 has a dot frequency that is four times the color subcarrier frequency (4fsc) created based on a color burst signal extracted from a received television signal. A dot counter that counts clock signals,
Select a dot decoder that decodes the count value of this dot counter and outputs various timing signals, a signal output from this dot decoder that indicates the final dot position for one line, or a horizontal synchronization detection signal detected at the previous stage. clearing means for clearing a dot counter with one of the masked horizontal synchronization detection signals; a leakage integrator circuit that receives the AND of the window pulse output from the dot decoder and the horizontal synchronization detection signal; The horizontal synchronization protection circuit includes mask control means for validating the masking of the horizontal synchronization detection signal when the integral value of the circuit is equal to or greater than a predetermined value.

The synchronization separation circuit according to the invention of youngest brother 2 includes a line counter that counts a line frequency clock signal created based on a synchronization signal extracted from a received television signal, and a line counter that decodes the count value of this line counter to perform various calculations. A line decoder that outputs a timing signal, and a signal indicating the final line position for one frame output from this line decoder, or a masked frame pulse that selectively masks the frame pulse supplied from the vertical synchronization detector in the previous stage. A clearing means for clearing the line counter in either one, a leakage integration circuit that receives the logical product of the frame pulse output from the line decoder and the frame pulse supplied from the previous stage vertical synchronization detection section, and the integration of this leakage integration circuit. The frame synchronization protection section includes a mask control means for validating a mask for the frame pulse supplied from the vertical synchronization detection section at the previous stage when the value is equal to or greater than a predetermined value.

(Function) According to the synchronization separation circuit of the present invention, even if some erroneous detection of synchronization signals occurs, synchronization processing by hunting of the synchronization protection circuit is not started within the period determined by the time constant of the leaky integrator. To effectively avoid deterioration in accuracy due to the influence of ghosts.

The operation of the present invention will be explained in detail below along with examples.

(Embodiment) FIG. 1 is a block diagram showing the configuration of an embodiment of the synchronous separation circuit of the present invention.

This synchronization separation circuit includes an analog synchronization separation section 1, a blackout generation section 2, an A/D conversion section 3, a color burst removal section 4,
It is composed of a horizontal synchronization detection section 5, a vertical synchronization detection section 6, a horizontal synchronization protection section, and a frame synchronization protection section 8.

As shown in FIG. 2, the analog synchronization separation section 1 includes a low-pass filter circuit 11, a composite synchronization signal separation circuit 12, an AFC circuit 13, a vertical synchronization signal separation circuit 14, and a timing generation circuit 15.

This analog synchronization separation circuit 1 separates a horizontal synchronization signal H and a vertical synchronization signal V from an analog composite video signal supplied from an input terminal IN, and supplies them to a subsequent display section for display control. A timing generation circuit 15 composed of a pipe rake or the like generates a burst flag and a clamp pulse, and supplies them to the clock generation section 2 and A/D conversion section 3 in FIG. 1, respectively.

The clock generation unit 2 in FIG. 1 uses the burst flag generated by the analog synchronization separation unit 1 to extract a color burst signal from the analog video signal on the input terminal IN.
A clock signal of twice the frequency (4 fsc) is generated and supplied to the A/D converter 3 and other circuit parts.

The A/D converter 3 performs pedestal clamping on the analog composite video signal on the input terminal IN using the clamp pulse generated by the analog synchronization separator 1, and generates the 4fsc clock generated by the clock generator 2. The signal is used to convert it into a digital composite video signal.

The color burst removal section 4 is composed of a one-line delay circuit 4a and an adder circuit 4b. This color burst removal section 4 outputs the output of the A/D conversion section 3 including the color burst CB as shown in FIG. Addition circuit 4
By adding at b, a digital composite video signal from which the color burst signal has been removed as shown in FIG. 3(B) is generated and supplied to the horizontal synchronization detection section 5.

The horizontal synchronization detection unit 5 includes a binarization circuit 5a that binarizes the color burst-removed digital composite video signal;
It is comprised of a fall detection circuit 5b that detects the fall point of the output of this binarization circuit in synchronization with a clock signal having a frequency of 4 fsc.

The binarization circuit 5a converts the color burst-removed composite video signal illustrated in FIG. 3(B) to a predetermined reference value Lref.
A binary signal is generated according to the magnitude relationship.

By setting the reference Lref near the pedestal level of the composite video signal, a signal having a width approximately equal to that of the horizontal synchronizing signal is detected, as illustrated in FIG. 3(C).

This signal falls in synchronization with the horizontal synchronization signal as shown in FIG. The signal is converted into a horizontal synchronization detection signal having a clock signal width, and is supplied to the horizontal synchronization protection circuit 7.

The output of the binarization circuit 5a of the horizontal synchronization detection section 5 includes information indicating the position of the vertical synchronization signal in addition to the information indicating the position of the horizontal synchronization signal described above. However, when trying to use the output of this binarization circuit 5a for detecting a vertical synchronizing signal, the problem occurs because the original signal and the one-line delayed signal are added in the color burst removal section 4 at the previous stage. Therefore, there is a risk that synchronization may be disrupted during the vertical retrace period.

That is, as shown in FIG. 4, the vertical synchronizing signal and equalization pulse appear in the waveform (A) during the vertical retrace period,
Waveform (B) is obtained by delaying this by one line. Therefore, the output of the color burst removal section 4, which adds waveforms (A) and (B) and divides by 2, becomes waveform (C), and an intermediate level portion appears at the beginning of the equalized pulse. If an attempt is made to binarize the intermediate level portion of this waveform (C) in the binarization circuit 5a of the horizontal synchronization detection section 5, the binarized signal will vary between "1" and 0", and This may cause false detection of a decline.

Therefore, as will be described later, the output from the horizontal synchronization detection section 5 during the vertical retrace period is invalidated by the horizontal synchronization protection section 7 in the subsequent stage, and the position detection of the vertical synchronization signal is performed by the horizontal synchronization detection section 5. is performed in a separately installed vertical synchronization detection section 6.

The vertical synchronization detection section 6 includes a binarization circuit 6a, a low-pass filter circuit 6b, a latch circuit 6c, and a selection latch circuit 6d.

The binarization circuit 6a binarizes the digital composite video signal output from the A/D converter 3 by comparing it with a predetermined reference level L ref near the pedestal level.

This binary signal is supplied to the latch circuit 6C while high frequency components caused by the color burst signal and the like are removed by the low-pass filter circuit 6b. A clock signal 2Hck having a frequency twice the horizontal synchronization frequency is supplied to the clock input terminal of the latch circuit 6C. This clock signal 2Hck
The phase of is set so that it appears in the first half and the second half of each line, as shown in FIG. 5(A). Therefore, the latch circuit 6C continues to latch the high signal during the appearance period of the video signal.

On the other hand, as shown in FIG. 5(B), when an equalization pulse appears with the start of the vertical retrace period, the lie circuit 6C begins to latch the low signal. As a result, the output of the latch circuit 6C falls to a low level in synchronization with the start of the vertical retrace period, as shown in FIG. 5(C). The line width immediately before the start of this vertical retrace period is as shown in Fig. 5 (B) for even fields.
), the width is one line, but for odd fields, the width is half a line as shown in FIG. 5(D).

As a result, at the time when the output of the latch circuit 6c falls to low, a time difference of half a line occurs depending on whether it is an odd field or an even field. Selection latch circuit 6
d uses the fact that the outputs of the preceding latch circuit 6C are alternately shifted by one clock cycle to selectively latch only one of them (the odd field), thereby detecting the frame detection signal generated in the frame cycle. Output. The selection latch circuit 6d includes a counter section for the clock signal Hck, and a latch section that latches the output of the preceding latch circuit 6c when the count value reaches a predetermined value.

FIG. 6 is a block diagram showing the configuration of the horizontal synchronization protection section 7 of FIG. 1.

This horizontal synchronization protection section 7 includes various logic gates such as an inverter 21 and an AND gate 22, a dot counter 24,
Decoder 25, flip-flop 26, leaky integrator 2
8 and a binarization circuit 29, and operates with positive logic.

The horizontal synchronization detection signal output from the horizontal synchronization detection section 5 described above is supplied to one input terminal of AND gates 22 and 27 via input terminal 11 and inverter 21 . The dot counter 24 counts the clock signal having a dot (pixel) frequency of 4 fsc supplied from the input terminal 2 while being cleared by the high signal supplied from the OR gate 23. The decoder 25 decodes the count value of the dot counter 24 and outputs various timing signals. The 909 decoded signal, which is one of the various timing signals output from this decoder, is sent to the OR gate 23.
is supplied to the clear terminal of the dot counter 24 via
The count value of the dot counter 24 is changed from the maximum value 909 to O.
Return to That is, this dot counter 24 is cleared at the cycle of one line.

Other timing signals output from the decoder 26 are 4
Flip flop 2 in synchronization with the clock signal of fsc
6, H timing signal, clock signal 2Hc
k is supplied to the corresponding output terminal as the clock signal Hck. One of the timing signals is supplied to the other input terminal of the AND gate 27 as a window pulse W for the horizontal synchronization detection signal supplied to one input terminal of the AND gate 27 via the input terminal 1. The width of this window pulse W is set to a value approximately five times the width of the horizontal synchronization detection signal in order to absorb fluctuations in the horizontal synchronization detection signal due to ghosts and the like.

Therefore, when the horizontal synchronization detection signal appears almost at the same time as the window pulse W output from the flip-flop 26 at the {circle around (2)} line period, the AND gate 27 outputs a high signal. This high output is provided to the leakage integrator 28 to supplement the integrated voltage value reduced due to leakage. The binarization circuit 29 compares the voltage value of the leakage integrator 28 with a predetermined value, and raises the output to high when the former becomes less than or equal to the latter. The rise of this output opens the AND gate 22 and starts hunting. In this hunting mode, input terminal I
The dot counter 24 is synchronized with the horizontal synchronization detection signal supplied from f through the AND gate 22 and the OR gate 23.
is cleared.

As the hunting mode progresses, the AND gate 27 starts outputting a high signal again, and when the leakage integrated voltage exceeds a predetermined value, the output of the binarization circuit 29 falls to low.

As a result, the horizontal synchronization detection signal is blocked by the AND gate 22, the dot counter 24 is cleared by the 909 decoding signal from the decoder 25, and the horizontal synchronization protection section 7 shifts to the free running mode.

In this way, even if a situation occurs in which a high signal is not output from the AND gate 27 due to erroneous detection or detection failure of the horizontal synchronization signal, the hunting of the horizontal synchronization protection circuit is prevented during the period determined by the time constant of the leakage integrator 28, etc. synchronization processing is not started. Therefore, the problem that the operation becomes unstable due to the erroneous detection of the synchronization signal (frequent hunting starts) and the timing accuracy decreases is solved.

In addition, the AND gate 22 is connected from the vertical synchronization detection section 8 in FIG.
The signal VBLK supplied to one of the input terminals falls to low during the vertical retrace period.

As a result, transition to the hunting mode is prohibited during the vertical retrace period, and the already started hunting mode is interrupted. This is because, as already explained with reference to FIG. This is to prevent it from being disturbed.

FIG. 7 is a block diagram showing the configuration of the vertical synchronization protection section 8 of FIG. 1.

This vertical synchronization protection section 8, like the horizontal synchronization protection section 7 in FIG. and a binarization circuit 39, and operates with positive logic.

The frame pulse output from the vertical synchronization detection section 6 described above is supplied as an external frame pulse to one input terminal of AND gates 32 and 37 via the input terminal 11 and the inverter 31. The line counter 34 is the or gate 3
While being cleared by the high signal supplied from 3,
The line frequency clock signal Hck supplied from the input terminal 2 is counted. The decoder 35 decodes the count value of the line counter 34 and outputs various timing signals. The 524 decode signal, which corresponds to one of the various timing signals output from the decoder 35, is supplied to the clear terminal of the line counter 34 via the OR gate 33, and changes the count value of the line counter 34 from the maximum value 524 to 0. Return to That is, this line counter 34 is cleared at the cycle of one frame.

Other timing signals output from the decoder 36 are a VBLK signal, a frame timing signal, a field timing signal, a VBLK signal held in the flip-flop 36 in synchronization with the clock signal Hck, and supplied to the horizontal synchronization protection section 7.
A timing signal is supplied to the corresponding output terminal. One of the timing signals is supplied to one input terminal of the AND gate 37 as an internal frame pulse. The other input terminal of this AND gate 37 has an input terminal ■1
An external frame pulse is supplied from the vertical synchronization detection section 6 via the inverter 31 and the inverter 31 .

Therefore, if the internal frame pulse and external frame pulse output from the flip-flop 36 in one frame period are synchronized, a high signal is output from the AND gate 37, and the voltage value of the leakage integrator 38, which has decreased due to leakage, is will be replenished. When this leakage integrated voltage value becomes less than a predetermined value due to loss of synchronization between both frame pulses, the binarization circuit 3
The output of 9 rises to high, and the AND gate 32 is opened.
Hunting begins. In this hunting mode,
Line counter 34 is cleared in synchronization with an external frame pulse supplied from input terminal 11 through gates 32 and 33.

As the hunting mode progresses, a high signal is again output from the AND gate 37, and when the leakage integrated voltage value exceeds a predetermined value, the output of the binarization circuit 39 falls to low. As a result, the external frame pulse is blocked by the AND gate 32, the line counter 34 is cleared only by the 524 decode signal from the decoder 35, and the vertical synchronization protection unit 8 shifts from hunting mode to free running mode. .

In this way, even if a situation occurs in which a high signal is not output from the AND date 37 due to erroneous detection or detection failure of the vertical synchronization signal, the hunting of the vertical synchronization protection circuit will continue within the period determined by the time constant of the leakage integrator 38, etc. synchronization processing is not started. Therefore, the problem that the operation becomes unstable due to the start of frequent hunting based on the erroneous detection of the synchronization signal, and the timing accuracy decreases, is solved.

FIG. 8 is a block diagram showing the configuration of another embodiment of the synchronous separation circuit of the present invention.

In the sync separation circuit of this embodiment, the clamp pulse supplied to the A/D converter 3 of the sync separation circuit shown in FIG. It shows the configuration created by . Therefore, the same reference numerals as in FIG. 1 are given to the components common to the circuit in the circuit shown in FIG. 2 and the circuit shown in FIG.

The horizontal synchronization protection section 7° in FIG. 8 adds a function of outputting a clamp pulse to instruct the clamp timing to the decoder 25 in the horizontal synchronization protection section 7 of the previous embodiment shown in FIGS. 1 and 6. In addition, the configuration has been changed so that the output of the binarization circuit 29 is outputted to the outside as a mode display signal. In addition, the vertical synchronization protection section 8'' in FIG. 8 outputs the output of the binarization circuit 39 in the vertical synchronization protection section 8 of the previous embodiment shown in FIGS. 1 and 7 to the outside as a mode display signal. The configuration has been changed to output.

The clamp pulse output from the horizontal synchronization protection section 7° and the ■BLK signal output from the frame synchronization protection section 8 are as follows:
It is supplied to each of the two non-inverting input terminals of the four-person gate 9. Further, the mode display signals output from the horizontal synchronization protection section 7' and the vertical synchronization protection section 8 are supplied to each of the two inverting input terminals of the four-person gate 9. As a result, the clamp created by the horizontal synchronization protection section 7'' under the condition that neither the horizontal synchronization protection section 7'' nor the vertical synchronization protection section 8゜ is in hunting mode and not within the vertical retrace period. The pulse is supplied to the A/D converter 3, and pedestal clamping is performed.In this way,
The reason why pedestal clamping is prohibited during the vertical retrace period is that as the video signal disappears during the vertical retrace period, its ghost component disappears, and as a result, the pedestal level may change significantly.

FIG. 9 is a block diagram showing the configuration of still another embodiment of the synchronous separation circuit of the present invention, in which 41 is an analog synchronous separation section, 42 is a clock generation section, and 45 is a horizontal opening! tII detection section 1, 46 is a vertical synchronization detection section, 47 is a horizontal synchronization protection section, 4
8 is a vertical synchronization protection section.

The analog synchronization separator 41 passes the analog composite video signal supplied to the input terminal IN through a low-pass filter circuit to blunt the waveform, and then slices the horizontal synchronization signal while clamping the leading end of the signal. By performing 5YNC chip slicing processing, a composite synchronization signal is separated from the video signal and is supplied to a horizontal synchronization detection section 45 and a vertical synchronization detection section 46. In parallel with the above synchronization separation process, the analog synchronization separation section 41 generates a burst flag used for extracting a color burst from the composite video signal, and supplies it to the clock generation section 42.

The horizontal synchronization detection section 45 has a configuration in which the same function as the digital horizontal synchronization detection section 5 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, this analog-format horizontal synchronization detection section 45 binarizes the analog composite synchronization signal supplied from the analog synchronization separation section 41, and detects the falling point of the signal in synchronization with the 4fsc clock signal, thereby generating a clock signal. A horizontal synchronization detection signal having a width of one cycle is generated and outputted to the horizontal synchronization protection circuit 47 at the subsequent stage.

The vertical synchronization detection section 46 has a configuration in which the same function as the digital vertical synchronization detection section 6 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, this analog-format horizontal synchronization detection section 46 binarizes the analog composite synchronization signal supplied from the analog synchronization separation section 41, passes it through a low-pass filter circuit, latches it in synchronization with the clock signal 2Hck, and converts it into a binary form. By selectively latching the latch output in one jump in synchronization with the clock signal Hck, a frame period vertical synchronization detection station signal is generated, and this is supplied as an external frame pulse to the frame synchronization protection circuit 48 at the subsequent stage.

The horizontal synchronization protection circuit 47 has substantially the same configuration as the horizontal synchronization protection circuit 7 shown in FIGS. 1 and 6, and performs substantially the same operation. The vertical synchronization protection circuit 48
It has almost the same configuration as the vertical synchronization protection circuit 8 shown in FIG. 7 and FIG. 7, and performs almost the same operation. However, unlike the synchronization separation circuit shown in FIG. 1, the frame synchronization protection circuit 48 does not generate a VBLK signal, and the horizontal synchronization protection circuit 47 performs a hunting operation even during the vertical retrace period.

FIG. 10 is a block diagram showing the configuration of another embodiment of the synchronous separation circuit of the present invention, in which 51 is an analog synchronous separation section;
52 is a clock generation section, 55 is a horizontal synchronization detection section, 56 is a vertical synchronization detection section, 57 is a horizontal synchronization protection section, and 58 is a vertical synchronization protection section.

The analog synchronization separation unit 51 passes the analog composite video signal supplied to the input terminal IN through a low-pass filter circuit to blunt the waveform, and then slices the horizontal synchronization signal while applying a clamp to the leading edge of the horizontal synchronization signal. By performing 5YNC chip slicing processing, the composite synchronization signal is separated from the video signal and supplied to the horizontal synchronization detection section 55. The analog synchronization separator 51 detects a vertical blanking period by passing the composite synchronizing signal separated from the video signal through a low-pass filter circuit, and detects the composite synchronizing signal within the detected vertical blanking period for vertical synchronization detection. Separation 56 is fed. In parallel with the above synchronization separation process, the analog synchronization separation section 51 generates a burst flag used for extracting a color burst from the composite video signal, and supplies it to the clock generation section 52.

The horizontal synchronization detection section 55 has a configuration in which the same function as the digital horizontal synchronization detection section 5 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, this analog horizontal synchronization detection section 55 binarizes the analog composite synchronization signal supplied from the analog synchronization separation section 51, and detects the falling point of the signal in synchronization with the 4fsc clock signal, thereby generating a clock signal. A horizontal synchronization detection signal having a width of one cycle is generated and outputted to the horizontal synchronization protection circuit 57 at the subsequent stage.

The vertical synchronization detection section 56 has a configuration in which the same function as the digital vertical synchronization detection section 6 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, this analog-format horizontal synchronization detection section 56 binarizes the synchronization detection signal supplied from the analog synchronization separation section 51 and converts it into a clock signal 2.
By latching this latch output in synchronization with Hck and selectively latching it in one jump in synchronization with the black signal Hck, a vertical synchronization detection station signal with a frame period is generated, and this is used as an external frame pulse in the subsequent stage. It is supplied to the frame synchronization protection circuit 58 of.

The horizontal synchronization protection circuit 57 has substantially the same configuration as the horizontal synchronization protection circuit 7 shown in FIGS. 1 and 6, and performs substantially the same operation. The vertical synchronization protection circuit 58
It has almost the same configuration as the vertical synchronization protection circuit 8 shown in FIG. 7 and FIG. 7, and performs almost the same operation. However, unlike the synchronization separation circuit shown in FIG. 1, the frame synchronization protection circuit 58 does not generate a VBLK signal, and the horizontal synchronization protection circuit 57 performs a hunting operation even during the vertical retrace period.

FIG. 11 is a block diagram showing the configuration of still another embodiment of the synchronous separation circuit of the present invention. In this synchronous separation circuit, each part designated by the same reference numeral as the synchronous separation circuit in FIG. 10 has the same structure as the corresponding part in the synchronous separation circuit shown in FIG. Therefore, redundant explanations regarding these will be omitted.

In this synchronization separation circuit, the burst flag for color burst extraction used in the clock generation section 52 is outputted from the vertical synchronization protection section 58 and the burst timing signal created by the horizontal synchronization protection section 57 in the AND circuit 59. It is created from the AND with the VBLK signal.

In the above, a configuration has been shown in which hunting does not start immediately even if synchronization signal detection fails for both the horizontal and vertical synchronization protection circuits. However, in consideration of timing accuracy and pull-in speed when out of synchronization, it is also possible to adopt a conventional configuration in which hunting is started immediately in either the horizontal or vertical direction.

(Effects of the Invention) Since the synchronization separation circuit of the present invention has the above-described configuration, even if some erroneous detection of the synchronization signal occurs, within the period determined by the time constant of the leaky integrator, the synchronization separation circuit will not be affected by hunting of the synchronization protection circuit. Synchronization process is not started.

As a result, instability of operation due to incorrect detection of synchronization signals due to effects such as ghosting is effectively prevented, and the display timing accuracy is more than an order of magnitude higher than that produced by conventional synchronization separation circuits. Timing accuracy was achieved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing the configuration of an embodiment of the synchronous separation circuit of the present invention, FIG. 2 is a block diagram showing the configuration of the analog synchronous separation circuit of FIG. 1, and FIG. 3 , FIG. 4 and FIG. 5 are waveform diagrams for explaining the operation of the synchronization separation circuit of FIG. 1, FIG. 6 is a block diagram showing the configuration of the horizontal synchronization protection section 7 of FIG. 1, and FIG. FIG. 1 is a block diagram showing the configuration of the vertical synchronization protection unit 8, FIG. 8 is a block diagram showing the configuration of another embodiment of the synchronization separation circuit of the present invention, and FIG. 9 is a block diagram showing the configuration of another embodiment of the synchronization separation circuit of the present invention. FIG. 10 is a block diagram showing the structure of another embodiment of the synchronous separation circuit of the present invention. FIG. 11 is a block diagram showing the structure of another embodiment of the synchronous separation circuit of the present invention. FIG. 2 is a block diagram showing the configuration. 1141.51...Analog synchronization separation unit, 2.42.
52... Clock generation section, 3... A/D conversion section, 4
...Color burst removal section, 5.45.55...Horizontal synchronization detection section, 6.46.56...Vertical synchronization detection section,
7.47.57...Horizontal synchronization protection section, 8.48.58
... Frame synchronization protection unit, 24... Dot counter, 25... Dot decoder, 28... Leakage integrator,
34... Line counter, 35... Line decoder, 38... Leakage integrator. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (2)

[Claims] (1) A dot counter that counts a clock signal with a dot frequency four times the color subcarrier frequency created based on the color burst signal extracted from the received television signal, and a dot counter that decodes the count value of this dot counter and performs various functions. a dot decoder that outputs a timing signal, and a signal indicating the final dot position for one line output from this dot decoder, or a masked horizontal synchronization detection signal that selectively masks the horizontal synchronization detection signal detected in the previous stage. clearing means for clearing the dot counter in either case; a leakage integration circuit that receives an AND of the window pulse output from the dot decoder and the horizontal synchronization detection signal; and an integral value of the leakage integration circuit that is greater than or equal to a predetermined value. A synchronization separation circuit comprising: a horizontal synchronization protection circuit having mask control means for validating the masking of the horizontal synchronization detection signal when: (2) A line counter that counts a line frequency clock signal created based on a synchronization signal extracted from a received television signal, and a line decoder that decodes the count value of this line counter and outputs various timing signals. , Clear the line counter using either a signal indicating the final line position for one frame output from this line decoder or a masked frame pulse obtained by selectively masking the frame pulse supplied from the vertical synchronization detection section in the previous stage. a leakage integrator circuit that receives an AND of the frame pulse output from the line decoder and the frame pulse supplied from the vertical synchronization detection section; and when the integral value of the leakage integrator circuit is greater than or equal to a predetermined value. A synchronization separation circuit comprising a frame synchronization protection section having a mask control means for validating a mask for a frame pulse supplied from the vertical synchronization detection section.