JP3024726B2 - Half killer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a half killer circuit, and more particularly, to a skew remarkable in a video signal of a VTR in order to improve the accuracy of a system clock used for digital processing of a television video signal. Regarding accurate detection of pulses.

[0002]

2. Description of the Related Art A sync signal in a video signal reproduced by a VTR may include a skew (discontinuity in a horizontal cycle). On the other hand, the horizontal synchronization signal of the reproduced video signal becomes a reference signal of a PLL circuit (phase synchronization circuit) that generates a system clock. Therefore, it is necessary to separate a composite synchronization signal (consisting of horizontal and vertical synchronization signals and equivalent pulses) from the reproduced video signal, and to extract a horizontal synchronization signal from the composite synchronization signal. Conventionally, as a method of obtaining a horizontal synchronizing signal from the composite synchronizing signal, "half killer processing (1/2 H
Killer processing) circuit is often used. The conventional half-killer processing circuit obtains only the horizontal synchronizing signal by removing the vertical synchronizing signal and the equivalent pulse by half-killing the entire composite synchronizing signal. However, if the composite video signal contains a skew component (pulse), the half-killer processing circuit may cancel this skew pulse and erroneously recognize the next horizontal synchronization pulse as a skew pulse. If this erroneous recognition occurs, the stability of the PLL circuit as a reference signal is impaired, which causes a delay to a stable convergence of the system clock which becomes unstable for a certain period.

[0003]

Therefore, in order to stably converge an unstable system clock in a short time, it is necessary to accurately detect a skew pulse. The present invention has been made in view of such a demand, and has as its object to provide a half-killer circuit that accurately detects a skew pulse in order to stably converge a system clock in a short time.

[0004]

According to the present invention, a horizontal synchronizing signal, a vertical synchronizing signal, and an equivalent pulse are generated by using a horizontal cycle comparison signal obtained by dividing a system clock generated by a voltage controlled oscillator in a PLL circuit. Blank pulse generating means for generating a blank pulse corresponding to a period in which the vertical synchronizing signal and the equivalent pulse of the included composite synchronizing signal are present; and a horizontal synchronizing signal, a vertical synchronizing signal and an equivalent pulse relating to the composite synchronizing signal. Edge detecting means for detecting an edge of the blank pulse, and a vertical synchronizing signal and an equivalent pulse in a blank pulse period are eliminated from the blank pulse generated by the blank pulse generating means and the edge signal detected by the edge detecting means, and the horizontal First horizontal synchronizing signal extracting means for extracting only an edge signal of the signal; A second horizontal synchronizing signal extraction means for detecting an edge signal of the horizontal synchronizing signal period except blank pulse period and a blanking pulse by means of the first
And an adding means for adding the respective edge signals of the horizontal synchronizing signal extracting means and the second horizontal synchronizing signal extracting means for detecting the skew pulse generated in a predetermined range outside the blank pulse period without disappearing. A half killer circuit is provided.

[0005]

A blank pulse is generated by using a horizontal cycle comparison signal obtained by dividing the system clock generated by the voltage controlled oscillator of the PLL circuit. This blank pulse is a pulse whose phase matches the period of the equivalent pulse and the vertical synchronizing pulse in the vertical blanking period.
Performs two processes. One process is a half killer process (1 /
2 H killer process) is performed only for this blank pulse period. By this processing, a horizontal synchronizing signal (edge signal) within the vertical blanking period is obtained, and the equivalent pulse and the vertical synchronizing signal disappear. Also, the skew pulse does not disappear because it is outside the vertical flyback period. In other processing, the composite sync signal is masked with the blank pulse, and a horizontal sync signal (edge signal) other than the masked period is obtained. By combining the signals subjected to the above two processes, a horizontal synchronizing signal (edge signal) for the entire period is finally obtained.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A half killer circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a main block diagram showing an embodiment of a half killer circuit according to the present invention, and FIG. 2 is a timing chart for explaining FIG.
It is a principle waveform diagram of the part which attached | subjected the code | symbol. In FIG. 1, reference numeral 1 denotes a synchronization separation unit, which separates a composite synchronization signal S2 and a vertical synchronization signal S3 from a composite video signal S1. As shown in FIG. 2A, the composite synchronizing signal S2 is the same when a horizontal synchronizing signal (a), a vertical synchronizing signal (b), an equivalent pulse (c), and a skew pulse (d) are included. This is a signal including a pulse. The skew pulse is generally generated within the range of 5 to 8H (horizontal cycle) of the vertical synchronizing signal as shown.

The blank pulse generator 2 compares the vertical synchronizing signal S3 and a system clock generated by a voltage controlled oscillator (VCO) of a PLL circuit (not shown) by a frequency divider into a horizontal cycle. The signal S4 is input, and a blank pulse having a required phase and width is generated from these signals. A specific configuration example of the blank pulse generation unit 2 is as illustrated. In the blank pulse generator 2, the counter 2a counts the comparison signal S4. This count data is sent to the first comparator 2e and the second comparator 2f. On the other hand, the vertical synchronizing signal S3 is the first flip-flop 2b
Is sent to the D input terminal. This first flip-flop 2b
Hereinafter, the second flip-flop 2c and the first OR gate
2d generates a reset signal (1 clock width) for resetting the counter 2a every vertical cycle. Each flip-flop output and OR gate output are shown in FIGS.

The first comparator 2e and the second comparator 2f determine that the input count data is substantially equal to one of equivalent pulses.
A low level is output before H (the first comparator 2
e) Output a high level approximately 1H after the equivalent pulse (second comparator 2f). Both comparators 2e, 2f
Is ORed by a second OR gate 2g, and the OR output is further output to a third flip-flop 2h (for example, D
2 (F) from the positive output (Q output) end
A pulse having a width equivalent to that of the vertical synchronizing signal shown in FIG. The Q output and the output of the second OR gate 2g are connected to the first
AND is obtained by the AND gate 2i of FIG. This signal is a pulse having a width matching the period T1 during which the vertical synchronizing signal and the equivalent pulse are present in the vertical blanking period.
Hereinafter, the above pulse is referred to as a blank pulse.

On the other hand, the edge detection section 3 detects an edge of the composite synchronization signal S2 separated by the synchronization separation section 1. Edge detection is performed by an edge detection circuit 3a, and the detected edge signal is inverted in polarity in the processing at the next stage (inverter 3b) to obtain an edge signal shown in FIG. The blank pulse (G) and the edge signal (E) are sent to a first horizontal synchronizing signal extracting unit 4 comprising a third OR gate 4a and a half killer processing (1/2 H killer processing) circuit 4b. The third OR gate 4a and the half killer processing circuit 4b perform a half killer process for the period T1 from the blank pulse output from the first AND gate 2i and the edge signal output from the inverter 3b. By this processing, the vertical synchronizing signal and the equivalent pulse in the period T1 disappear, and the edge signal of the horizontal synchronizing signal is obtained. This signal is shown in FIG.

The composite synchronizing signal S2 from the synchronizing separation unit 1 is further sent to a second horizontal synchronizing signal extracting unit 5 comprising an inverter 5a, a second AND gate 5b and an edge detecting circuit 5c. The second horizontal synchronizing signal extractor 5 uses the blank pulse from the first AND gate 2i to obtain an edge signal of the horizontal synchronizing signal in a period excluding the blank pulse period T1. is there. FIG. 2I shows the output of the second horizontal synchronizing signal extraction unit 5. Output of the first horizontal synchronizing signal extractor 4 (output of the half killer processing circuit 4b)
And the output of the second horizontal synchronization detection unit 5 (the edge detection circuit 5c
Output) by a fourth OR gate 6 as an addition circuit.
If R is taken, an edge signal of the horizontal synchronizing signal for the entire period (horizontal scanning period and vertical blanking period) can be obtained. This signal is shown in FIG.
(K). This figure shows that the edge signal corresponding to the horizontal synchronization signal was obtained without eliminating the skew pulse (d) from the composite synchronization signal. Therefore,
By using the signal shown in FIG. 2H as a reference signal for the phase comparison (phase comparison circuit 7a) of the PLL circuit 7 at the subsequent stage, the synchronization disturbance of the system clock signal (VCO 7c) due to the skew pulse can be minimized. .

[0011]

As described above, according to the present invention, V
It is possible to accurately detect a skew pulse generated in a reproduced video signal of the TR or the like. On the other hand, in the conventional half killer circuit (1/2 H killer processing circuit), there is a possibility that the skew pulse is lost because the half killer process is performed on the entire composite synchronization signal. There has been a problem that a certain period of time is required until the system clock returns to a stable operation due to a large disturbance of the synchronization of the system clock of the PLL circuit of the subsequent stage. Therefore, by utilizing the skew pulse accurately detected according to the present invention, it is possible to converge the synchronization disorder of the system clock of the PLL circuit in a shorter time than in the past, and to obtain a stable system clock. . The system clock used herein is used for digital processing of a video signal. Stabilization of the system clock means stabilization of the digital processing, and means stabilization of image quality. . Therefore, the present invention can ultimately contribute to image quality stability of a video device that performs digital processing.

[Brief description of the drawings]

FIG. 1 is a main block diagram of an embodiment of a half killer circuit according to the present invention.

FIG. 2 is a timing chart for explaining FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization separation part 2 Blank pulse generation part 2a Counter 2b First flip-flop 2c Second flip-flop 2d First OR gate 2e First comparator 2f Second comparator 2g Second OR gate 2h Third flip-flop 2i first AND gate 3 edge detector 3a edge detector 3b inverter 4 first horizontal synchronization signal extractor 4a third OR gate 4b half killer processing circuit (1/2 H killer processing circuit) 5 second Horizontal synchronization signal extraction unit 5a Inverter 5b Second AND gate 5c Edge detection circuit 6 OR gate

Claims (5)

(57) [Claims] 1. A composite synchronizing signal including a horizontal synchronizing signal, a vertical synchronizing signal, and an equivalent pulse, using a horizontal cycle comparison signal obtained by dividing a system clock generated by a voltage controlled oscillator in a PLL circuit. Blank pulse generating means for generating a blank pulse coincident with the period in which the vertical synchronizing signal and the equivalent pulse exist, and edge detecting means for detecting edges of the horizontal synchronizing signal, the vertical synchronizing signal and the equivalent pulse relating to the composite synchronizing signal And, from the blank pulse generated by the blank pulse generating means and the edge signal detected by the edge detecting means, eliminate the vertical synchronizing signal and the equivalent pulse in the blank pulse period, and extract only the edge signal of the horizontal synchronizing signal within the period. A first horizontal synchronizing signal extracting unit, and a blank pulse generated by the composite synchronizing signal and a blank pulse generating unit. A second horizontal synchronizing signal extracting means for detecting an edge signal of the horizontal synchronizing signal during a period other than the blank pulse period from the first and second horizontal synchronizing signal extracting means, and respective edges by the first and second horizontal synchronizing signal extracting means. A skew pulse generated in a predetermined range outside the blank pulse period without erasing the skew pulse. 2. The method according to claim 1, wherein the blank pulse generating means is a PLL.
A counter that counts the comparison signal from the circuit and outputs count data; a first flip-flop having a vertical synchronization signal input to a D input terminal and a clock terminal to which the system clock signal is applied; The inverted output signal of the flip-flop is input to the D input terminal,
A logical sum operation is performed between a second flip-flop to which the system clock signal is applied to a clock terminal, a positive output signal of the first flip-flop, and a positive output signal of the second flip-flop, and outputs the same operation. A first OR gate that resets the counter with the signal according to the above, a first comparator whose count data by the counter becomes a low-level output approximately one horizontal cycle before the equivalent pulse, and a counter data whose count data is approximately the equivalent pulse. A second comparator that outputs a high level after one horizontal cycle, a second OR gate that performs an OR operation of the first comparator and the second comparator, and a signal from the second OR gate is D. A third flip-flop input to an input terminal and having a clock terminal to which an edge signal is applied by the edge detection means; Serial third half killer circuit according to claim 1, characterized in that is constituted by a first AND gate which forms a positive output signal of the flip-flop and the logical AND operation of the second signal from the OR gate of the. 3. A third OR gate for performing a logical OR operation between the blank pulse and the edge signal by an edge detecting means, the third horizontal synchronizing signal extracting means comprising: a third OR gate;
The output of the R gate is constituted by a half killer processing circuit for eliminating a vertical synchronizing signal and an equivalent pulse during a blank pulse period and extracting only an edge signal of a horizontal synchronizing signal within the synchronizing period. 2. The half killer circuit according to 1. 4. The second horizontal synchronizing signal extracting means includes a second AND gate which performs a logical product operation of the composite synchronizing signal having a predetermined phase and the blank pulse, and a second AND gate.
2. The half killer circuit according to claim 1, comprising an edge detection circuit for detecting an edge of the output of the D gate. 5. The half killer circuit according to claim 1, wherein said adding means is constituted by a fourth OR gate.