JP2604420B2 - Sync separation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit installed in a television receiver.

(Prior Art) In a color television broadcasting system, in order to match the resolution scanning of the camera on the broadcasting station side and the assembly scanning on the receiver side, the video signal for one horizontal scanning line and the video signal for one frame are respectively set. The horizontal synchronization signal and the vertical synchronization signal are superimposed,
A sync separation circuit for separating the horizontal and vertical sync signals from the video signal is provided in the receiver.

Conventionally, the above-mentioned sync separation circuit first separates a composite sync signal including a horizontal / vertical sync signal and a video signal by using an amplitude difference between the two, and then, separates the horizontal sync in the separated composite sync signal. / Vertical synchronization signal is configured to be separated using the frequency difference between the two. Each separated sync signal is
In order to establish phase stabilization under detection errors that may occur intermittently, a configuration is supplied to the subsequent display circuit etc. as a timing signal for display scanning via each phase locked loop It has become.

(Problems to be Solved by the Invention) Recently, along with the development of a high-definition television system which has been progressing at a rapid pace, the development of a ghost removal system for making it effective has been progressing at a rapid pace. A typical ghost elimination system transmits a television signal in which a predetermined reference waveform is inserted at a predetermined position in a television signal, and the receiver detects a ghost occurrence state from the degree of distortion of the reference waveform. Configuration. In order to detect this reference waveform from a predetermined location in a received television signal with high accuracy, a high-precision timing signal is required. This timing accuracy requires a timing accuracy of a value that is higher by about one digit than the timing accuracy for display created by the above-described conventional synchronization separation circuit.

As described above, it is difficult to improve the timing accuracy by almost one digit by simply extending the conventional sync separation technique.

(Means for Solving the Problems) A sync separation circuit according to the first and the present invention includes an analog sync separation unit that generates a burst flag and a clamp pulse while separating a sync signal from an analog composite video signal, and an analog sync separation unit. A clock generation unit that extracts a color burst signal from the analog video signal based on the burst flag generated by the unit and generates a clock signal having a frequency four times that of the color burst signal, and generates the analog video signal by the analog synchronization separation unit An A / D converter that converts a digital composite video signal using a clock signal having a frequency four times that of the color burst signal generated by the clock generator while performing pedestal clamping using the clamp pulse thus obtained; D
A color burst eliminator for removing the color burst signal included in the digital composite video signal by adding the output of the conversion unit and a signal obtained by delaying the output by one line; A horizontal sync detector that binarizes and generates a horizontal sync detection signal indicating the position of the horizontal sync signal included therein, a dot counter that counts a clock signal with a dot frequency of 4 fsc, and counts the value of this dot counter A dot decoder that decodes and outputs various timing signals, a signal that indicates the last dot position of one line output from the dot decoder, or a masked horizontal synchronization detection signal that selectively masks the horizontal synchronization detection signal Clearing means for clearing the dot counter, output from the dot decoder Horizontal synchronization protection comprising a leakage integration circuit receiving a logical product of a window pulse and the horizontal synchronization detection signal, and mask control means for validating a mask of the horizontal synchronization detection signal when an integrated value of the leakage integration circuit is equal to or greater than a predetermined value. Unit, a vertical synchronization detection unit that binarizes the output of the A / D conversion unit, detects the position of the vertical synchronization signal included in the output, and creates a frame pulse of one frame period, and counts the clock signal of the line frequency. Line counter,
A line decoder that decodes the count value of the line counter and outputs various timing signals, a signal indicating the last line position for one frame output from the line decoder or a frame pulse supplied from the vertical synchronization detection unit. Clearing means for clearing the line counter with any of the masked frame pulses selectively masked; leak receiving a logical table of a frame pulse output from the line decoder and a frame pulse supplied from the vertical synchronization detection unit; An integration circuit and a frame synchronization protection unit comprising mask control means for enabling masking of a frame pulse supplied from the vertical synchronization detection unit when the integration value of the leakage integration circuit is equal to or greater than a predetermined value.

The synchronization separation circuit according to the second aspect of the present invention includes: an analog synchronization separation unit configured to generate a burst flag while separating a synchronization signal from an analog composite video signal; A clock generation unit that extracts a color burst signal from the analog video signal and generates a clock signal having a frequency four times that of the color burst signal; and a clock generation unit that generates the clock signal while pedestal-clamping the analog video signal using a predetermined clamp pulse. An A / D converter for converting to a digital composite video signal using a clock signal having a frequency four times the frequency of the color burst signal, the output of the A / D converter and a signal obtained by delaying the output by one line are added. A color burst removing section for removing a color burst signal contained in the digital composite video signal; A horizontal synchronizing detector for creating a horizontal synchronizing detection signal indicating the position of the horizontal synchronizing signal of the pre-digital composite video signal by binarizing contained therein, 4f
a dot counter that counts a clock signal having a dot frequency of sc, a dot decoder that decodes the count value of the dot counter and outputs various timing signals, a signal that indicates the last dot position of one line output from the dot decoder or Clearing means for clearing the dot counter with one of masked horizontal synchronization detection signals obtained by selectively masking the horizontal synchronization detection signal; leakage receiving a logical product of a window pulse output from the dot decoder and the horizontal synchronization detection signal; A horizontal synchronization protection section comprising an integration circuit and mask control means for enabling the mask of the horizontal synchronization detection signal within a range where the integration value of the leakage integration circuit is equal to or greater than a predetermined value; And detects the position of the vertical synchronizing signal contained in the frame pulse to generate a frame pulse having a one-frame period. A vertical synchronization detector, a line counter that counts a clock signal of a line frequency, a line decoder that decodes a count value of the line counter and outputs various timing signals, and a final line of one frame output from the line decoder Clearing means for clearing the line counter with either a signal indicating a position or a masked frame pulse obtained by selectively masking a frame pulse supplied from the vertical synchronization detecting unit; a frame pulse output from the line decoder; A leaky integration circuit that receives a logical product of the frame pulse supplied from the vertical synchronization detection unit and a mask for the frame pulse supplied from the vertical synchronization detection unit when the integration value of the leakage integration circuit is equal to or greater than a predetermined value. A frame synchronization protection unit comprising mask control means for The clamp pulse generated by the synchronization decoder of the horizontal synchronization protection unit is converted into a vertical pulse detected by the vertical synchronization protection unit when the mask is valid in both the horizontal synchronization protection unit and the vertical synchronization protection unit. Means for supplying to the A / D converter only when not within the line period.

The synchronization separation circuit according to the third aspect of the invention separates a composite synchronization signal from an analog composite video signal, creates a burst flag, and outputs the separated composite synchronization signal and the created burst flag. A clock generation unit that extracts a color burst signal from the analog composite video signal under the burst flag output from the analog synchronization separation unit and generates a clock signal having a frequency four times as high as that of the burst signal; A horizontal synchronization detection unit that binarizes the output composite synchronization signal to generate a horizontal synchronization detection signal indicating the position of the horizontal synchronization signal included in the output composite synchronization signal; and a dot counter that counts a clock signal having a dot frequency of 4 fsc. This dot decoder decodes the count value of the dot counter and outputs various timings. Clearing means for clearing the dot counter with either a signal indicating the last duck position of one line output from the horizontal sync detection signal or a horizontal sync detection signal in which the horizontal sync detection signal is selectively masked, output from the dot decoder A leakage integration circuit for receiving the logical product of the window pulse and the horizontal synchronization detection signal, and mask control means for enabling the masking of the horizontal synchronization detection signal when the integrated value of the leakage integration circuit is equal to or greater than a predetermined value. A synchronization protection unit, a vertical synchronization detection unit that binarizes the composite synchronization signal output from the analog synchronization separation unit, detects the position of the vertical synchronization signal included in the composite synchronization signal, and generates a frame pulse of one frame period, A line counter that counts clock signals of a frequency. Either a line decoder that outputs a timing signal, a signal that indicates the last line position for one frame output from the line decoder, or a masked frame pulse that selectively masks a frame pulse supplied from the vertical synchronization detection unit. Clearing means for clearing the line counter, a leaky integrating circuit receiving the logical product of the frame pulse output from the line decoder and the frame pulse supplied from the vertical synchronization detecting section, and an integrated value of the leaky integrating circuit being not less than a predetermined value. A frame synchronization protection unit comprising mask control means for validating a mask for a frame pulse supplied from the vertical synchronization detection unit.

The synchronization separation circuit according to the fourth aspect of the present invention creates a burst flag while separating a horizontal synchronization signal and a vertical synchronization signal from an analog composite video signal, and generates the burst flag.
An analog sync separation section for outputting a vertical sync signal and a generated burst flag; and a clock having a frequency four times as high as that of the color burst signal extracted from the analog composite video signal under the burst flag output from the analog sync separation section. A clock generation unit that generates a signal, a horizontal synchronization detection unit that binarizes the horizontal synchronization signal output from the analog synchronization separation unit and creates a horizontal synchronization detection signal indicating the position of the horizontal synchronization signal included therein, A dot counter that counts a clock signal having a dot frequency of 4 fsc, a dot decoder that decodes the count value of the dot counter and outputs various timing signals, a signal indicating the last dot position of one line output from the dot decoder or Masked horizontal sync detection by selectively masking the horizontal sync detection signal Clear means for clearing the dot counter with any of the signals, a leak integrating circuit receiving a logical product of a window pulse output from the dot decoder and the horizontal synchronization detection signal, and an integrated value of the leak integrating circuit being equal to or more than a predetermined value In this case, the horizontal synchronization protection section comprising mask control means for validating the mask of the horizontal synchronization detection signal, and the vertical synchronization signal output from the analog synchronization separation section are binarized and the position of the vertical synchronization signal contained therein A vertical synchronization detection unit for detecting a frame pulse of one frame period, a line counter for counting a clock signal of a line frequency, a line decoder for decoding the count value of the line counter and outputting various timing signals, A signal indicating the last line position for one frame output from the line decoder or Clearing means for clearing the line counter with one of masked frame pulses obtained by selectively masking the frame pulse supplied from the direct synchronization detecting section, a frame pulse output from the line decoder and supplied from the vertical synchronization detecting section Frame synchronization comprising a leaky integration circuit receiving a logical product of the frame pulse and a frame pulse supplied from the vertical synchronization detection unit when the integrated value of the leaky integration circuit is equal to or greater than a predetermined value. And a protection unit.

The synchronizing separation circuit according to the fifth aspect of the present invention uses an analog synchronizing separation unit that separates and outputs a horizontal synchronizing signal and a vertical synchronizing signal from an analog composite video signal, and uses a predetermined burst flag from the analog composite video signal. A clock generation unit for extracting a color burst signal and generating a clock signal having a frequency four times as high as that of the color burst signal; and binarizing the horizontal synchronization signal output from the analog synchronization separation unit to determine the position of the horizontal synchronization signal included in the horizontal synchronization signal. A horizontal sync detection unit that generates a horizontal sync detection signal shown in the figure, a dot counter that quants a clock signal having a dot frequency of 4 fsc, a dot decoder that decodes the count value of this dot counter and outputs various timing signals, A signal indicating the final dot position for one line output from the decoder or the horizontal synchronization detection signal is selectively selected. Clearing means for clearing the dot counter with any of the masked horizontal synchronization detection signals, a leak integration circuit receiving the logical product of the window pulse output from the dot decoder and the horizontal synchronization detection signal, and integration of the leakage integration circuit When the value is equal to or more than a predetermined value, a horizontal synchronization protection unit comprising mask control means for validating the mask of the horizontal synchronization detection signal, and a vertical synchronization signal output from the analog synchronization separation unit are binarized and the vertical synchronization signal A vertical synchronization detector for detecting the position of the synchronization signal and generating a frame pulse of one frame period; a line counter for counting the clock signal of the line frequency; decoding the count value of the line counter to output various timing signals Line decoder, the last line position for one frame output from this line decoder Clearing means for clearing the line counter with either a signal indicating the frame pulse or a masked frame pulse obtained by selectively masking the frame pulse supplied from the vertical synchronization detector, a frame pulse output from the line decoder and the vertical synchronization detector And a mask control means for validating a mask for the frame pulse supplied from the vertical synchronization detection unit when the integrated value of the leakage integration circuit is equal to or greater than a predetermined value. And the burst flag created by the dot decoder of the horizontal synchronization protection unit is supplied to the clock generation unit on condition that the burst flag is outside the vertical retrace period detected by the line decoder of the vertical synchronization protection unit. And a burst flag supply unit.

(Embodiment) FIG. 1 is a block diagram showing a configuration of a sync separation circuit according to the first invention.

This synchronization separation circuit includes an analog synchronization separation unit 1, a clock generation unit 2, an A / D conversion unit 3, a color burst removal unit 4,
It comprises a horizontal synchronization detection section 5, a vertical synchronization detection section 6, a horizontal synchronization protection section and a frame synchronization protection section 8.

As shown in FIG. 2, the analog sync separation section 1 includes a low-pass filter circuit 11, a composite sync signal separation circuit 12, an AFC circuit 1
3, vertical synchronization signal separation circuit 14 and timing generation circuit 15
It is composed of This analog sync separation circuit 1
The horizontal synchronizing signal H and the vertical synchronizing signal V are separated from the analog composite video signal supplied from the input terminal IN and supplied to a subsequent display unit for display control, and a timing generator composed of a monostable multivibrator or the like is provided. The circuit 15 generates a burst flag and a clamp pulse, and supplies them to the clock generator 2 and the A / D converter 3 shown in FIG.

The clock generation unit 2 shown in FIG.
A color burst signal is extracted from the analog video signal on the input terminal IN using the burst flag generated in the step (a), and a clock signal having a frequency four times as high as that of the color burst signal (4f sc) is generated.
It is supplied to the conversion unit 3 and other circuit parts.

The A / D converter 3 performs pedestal clamping on the analog composite video signal on the input terminal IN using the clamp pulse generated by the analog sync separation unit 1, and generates the 4f sc generated by the clock generator 2 while performing pedestal clamping. It is converted into a digital composite video signal using the clock signal.

The color burst elimination unit 4 includes a one-line delay circuit 4a and an adder circuit 4bb. The color burst elimination unit 4 is provided with a color burst CV as shown in FIG.
And the output of the A / D conversion unit 3 and the one-line delay circuit 4
By adding the signal delayed by one line in a by the adder circuit 4b, a digital composite video signal from which the color burst signal is removed as shown in FIG.
It is supplied to the horizontal synchronization detection unit 5.

A horizontal synchronization detecting unit 5 for binarizing the digital composite video signal from which the color burst has been removed;
A falling detection circuit 5b detects the falling point of the output of the binarization circuit in synchronization with a clock signal having a frequency of 4fsc. The binarization circuit 5a compares the composite video signal from which the color burst is removed as exemplified in FIG. 3 (B) with a predetermined reference value Lref, and generates a binary signal according to the magnitude relation. By setting the reference Lref near the pedestal level of the composite video signal, a signal having a width substantially equal to the horizontal synchronization signal is detected as illustrated in FIG. 3 (C). The falling of the signal is detected in synchronization with the clock signal having a frequency of 4 fsc in the falling detection circuit 5b, so that the signal falls in synchronization with the horizontal synchronization signal, as shown in FIG. 3 (D). The signal is converted to a horizontal synchronization detection signal having a clock signal width and supplied to the horizontal synchronization protection circuit 7.

The output of the binarization circuit 5a of the horizontal synchronization detector 5 includes information indicating the position of the vertical synchronization signal in addition to the information indicating the position of the horizontal synchronization signal described above. However, if the output of the binarization circuit 5a is used to detect a vertical synchronization signal, the output of the original signal and the one-line delay signal is performed in the color burst removal unit 4 in the preceding stage. Synchronization may be disrupted during the vertical flyback period.

That is, as shown in FIG. 4, the appearance of the vertical synchronizing signal and the equalizing pulse in the vertical blanking period is the waveform (A), and the waveform obtained by delaying this by one line becomes the waveform (B). Therefore, the output of the color burst elimination unit 4 obtained by adding the waveforms (A) and (B) and dividing by 2 becomes a wave meter (C),
An intermediate level portion appears at the head of the equalization pulse.
If the intermediate level portion of the waveform (C) is to be binarized by the binarization circuit 5a of the horizontal synchronization detector 5, the binarized signal will vary between "1" and "0". This may cause false detection of falling.

Therefore, as will be described later, the output during the vertical retrace period from the horizontal synchronization detection unit 5 is invalidated by the horizontal synchronization protection unit 7 at the subsequent stage, and the position detection of the vertical synchronization signal is performed by the horizontal synchronization detection unit 5 This is performed in the vertical synchronization detecting unit 6 which is separately provided.

The vertical synchronization detector 6 includes a binarizing circuit 6a, a low-pass filtering circuit 6b, a latch circuit 6c, and a selection latch circuit 6d.

The binarizing circuit 6a binarizes the digital composite video signal output from the A / D converter 3 by comparing it with a predetermined reference level Lref near the pedestal level. The binarized signal is supplied to the latch circuit 6c while high-frequency components caused by a color burst signal and the like are removed by the low-pass filtering circuit 6b. A clock signal 2Hck having a frequency twice the horizontal synchronization frequency is supplied to a clock input terminal of the latch circuit 6c. The phase of the clock signal 2Hck is set so that it appears in the first half and the second half of each line, as shown in FIG. 5 (A). Therefore, during the appearance period of the video signal, the latch circuit 6c keeps latching the high signal.

On the other hand, as shown in FIG. 5B, when an equalizing pulse appears at the start of the vertical blanking period, the latch circuit 6c starts latching the low signal. As a result, the output of the latch circuit 6c falls to low in synchronization with the start of the vertical blanking period as shown in FIG. 5 (C). The line width immediately before the start of the vertical retrace period is one line as shown in FIG. 5B for an even field, but is half as shown in FIG. 5D for an odd field. The width of the line.

As a result, when the output of the latch circuit 6c falls to low, a time difference of a half line is generated depending on whether the field is an odd field or an even field. Select latch circuit 6d
Outputs a frame detection signal generated in a frame cycle by selectively latching only one of the outputs (of an odd field) using the fact that the output of the preceding latch circuit 6c is alternately shifted by one clock cycle. I do. Such a selection latch circuit 6d includes a counter section of the clock signal Hck and a latch circuit of a preceding stage when the count value reaches a predetermined value.
And a latch section for latching the output of 6c.

FIG. 6 is a block diagram showing the configuration of the horizontal synchronization protection section 7 of FIG.

The horizontal synchronization protection unit 7 includes various logic gates such as an inverter 21 and an AND gate 22, a dot counter 24, a decoder 25, a flip-flop 26, a leaky integrator 28, and a binarization circuit 29, and operates with positive logic. I do.

The horizontal synchronization detection signal output from the horizontal synchronization detection unit 5 is supplied to one input terminal of AND gates 22 and 27 via an input terminal I1 and an inverter 21. The dot counter 24 counts the clock signal of the dot (pixel) frequency of 4fsc supplied from the input terminal I2 while being cleared by the high signal supplied from the OR gate 23.
The decoder 25 decodes the count value of the dot counter 24 and outputs various timing signals. 910 which is one of various timing signals output from this decoder
The decode signal is sent to the dot counter via the OR gate 23.
It is supplied to the clear terminal 24 and returns the count value of the dot counter 24 from the maximum value 910 to 0. That is, the dot counter 24 is cleared at a cycle of one line.

Another timing signal output from the decoder 26 is 4f
It is held in the flip-flop 26 in synchronization with the clock signal of the sc, and is supplied to the corresponding output terminal as the H timing signal, the clock signal 2Hck, and the clock signal Hck. One of the timing signals is supplied to the other input terminal of the AND gate 27 as a window pulse W for the horizontal synchronization detection signal supplied to one input terminal of the AND gate 27 via the input terminal I1. The width of the window pulse W is set to about 5 times the width of the horizontal synchronization detection signal in order to absorb fluctuations of the horizontal synchronization detection signal due to ghosts and the like.

Therefore, when the horizontal synchronization detection signal appears almost simultaneously with the window pulse W output from the flip-flop 26 in one line cycle, a high signal is output from the AND gate 27. This high output is supplied to the leakage integrator 28 to supplement the integrated voltage value reduced by the leakage. Binarization circuit 29
Compares the voltage value of leakage integrator 28 with a predetermined value, and raises the output to high when the former becomes equal to or less than the latter. With the rise of this output, the AND gate 22 is opened and hunting is started. In the hunting mode, the dot counter 24 is cleared in synchronization with the horizontal synchronization detection signal supplied from the input terminal I1 through the AND gate 22 and the OR gate 23.

With the progress of the hunting mode, a high signal starts to be output again from the AND gate 27, and when the leakage integration voltage exceeds a predetermined value, the output of the binarization circuit 29 falls to low. As a result, the horizontal synchronization detection signal is blocked by the AND gate 22, the dot counter 24 is cleared by the decode signals of the decoders 25 to 910, and the horizontal synchronization protection unit 7 shifts to the free running mode.

The signal VBLK supplied from the vertical synchronization detector 8 to one of the input terminals of the AND gate 22 in FIG. 1 falls to low during the vertical blanking period. As a result, the transition to the hunting mode is prohibited during the vertical flyback period, and the already started hunting mode is interrupted. This is the fourth
As already described with reference to the drawing, erroneous detection of the horizontal synchronization signal occurs in the vertical blanking period due to the signal processing for removing the color burst, which disturbs the operation of the horizontal synchronization protection unit 7. It is to prevent.

FIG. 7 is a block diagram showing the configuration of the vertical synchronization protection section 8 of FIG.

This horizontal synchronization protection unit 8 is the same as the horizontal synchronization protection unit 7 in FIG.
Similarly, includes various logic gates such as an inverter 31 and an AND gate 32, a dot counter 34, a decoder 35, a flip-flop 36, a leaky integrator 38, and a binarization circuit 39.
Operates with positive logic.

The frame pulse output from the above-mentioned vertical synchronization detection unit 6 is AND gated through the input terminal I1 and the inverter 31.
One of the input terminals 32 and 37 is supplied as an external frame pulse. The line counter 34 receives the input signal Id while being cleared by the high signal supplied from the OR gate 33.
The clock signal Hck of the line frequency supplied from is counted. The decoder 35 decodes the count value of the line counter 34 and outputs various timing signals. A 525 decode signal corresponding to one of various timing signals output from the decoder 35 is supplied to the clear terminal of the line counter 34 via the OR gate 33, and the count value of the line counter 34 is returned from the maximum value 525 to 0. . That is, the line counter 34 is cleared at a cycle of one frame.

Other timing signals output from the decoder 36 are held in the flip-flop 36 in synchronization with the clock signal Hck, and are supplied to the horizontal synchronization protection unit 7 or the VBLK signal, the frame timing signal, and the field timing signal. Is supplied to the corresponding output terminal. One of the timing signals is supplied to one input terminal of the AND gate 37 as an internal frame pulse. The other input terminal of the AND gate 37 has an input terminal I1 and an inverter 31.
The external frame pulse is supplied from the vertical synchronization detecting unit 6 through the above.

Therefore, if the internal frame pulse output from the flip-flop 36 and the external frame pulse are synchronized in one frame period, a high signal is output from the AND gate 37, and the voltage value of the leakage integrator 38 reduced by the leakage is reduced. Be replenished. When the leakage integration voltage value falls below a predetermined value due to the loss of synchronization between the two frame pulses, the output of the binarization circuit 39 rises to high, the AND gate 32 is opened, and hunting is started. In this hunting mode, input terminal I1
, The line counter 34 is cleared in synchronization with the external frame pulse supplied through the gates 32 and 33.

With the signal in the hunting mode, a high signal is again output from the AND gate 37, and when the leakage integration voltage value exceeds a predetermined value, the output of the binarization circuit 39 falls to low. As a result, the external frame pulse is blocked by the AND gate 32, and the line counter 34 is cleared by the decoder.
The vertical synchronization protection unit 8 shifts from the hunting mode to the free-running mode by performing only the 525 decode signal from 35.

FIG. 8 is a block diagram showing a configuration of the sync separation circuit according to the second invention.

The sync separation circuit of this embodiment uses a clamp pulse to be supplied to the A / D converter 3 of the sync separation circuit of FIG. 1 instead of the analog sync separation section, instead of the horizontal sync protection section 7 'and the frame sync protection section 8'. And shows the configuration created. Therefore,
Components in the circuit of FIG. 2 that are the same as those in the circuit of FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and overlapping descriptions of these common components will be omitted.

The horizontal synchronization protection section 7 'in FIG. 8 adds a function of outputting a clamp pulse to the decoder 25 in the horizontal synchronization protection section 7 of the previous embodiment shown in FIGS. At the same time, the configuration is such that the output of the binarization circuit 29 is output to the outside as a mode display signal. Also, the vertical synchronization protection section 8 'in FIG. 8 outputs the output of the binarization circuit 39 in the vertical synchronization protection section 8 of the previous embodiment shown in FIGS. 1 and 7 as a mode display signal to the outside. The configuration has been changed to output.

The clamp pulse output from the horizontal synchronization protection section 7 'and the VBLK signal output from the frame synchronization protection section 8' are
The input is supplied to each of two non-inverting input terminals of the AND gate 9. The mode display signals output from the horizontal synchronization protection section 7 'and the vertical synchronization protection section 8' are supplied to the two inverting input terminals of the 4-input AND gate 9, respectively. As a result, the clamp generated by the horizontal synchronization protection unit 7 'under the condition that neither the horizontal synchronization protection unit 7' nor the vertical synchronization protection unit 8 'is in the hunting mode and within the vertical retrace period. The pulse is supplied to the A / D converter 3, and the pedestal clamp is performed. As described above, the pedestal clamp is prohibited during the vertical flyback period.
This is because the ghost component disappears with the disappearance of the video signal during the vertical blanking period, and as a result, the pedestal level may greatly change.

FIG. 9 is a block diagram showing a configuration of a sync separation circuit according to the third invention.
Is a clock generation unit, 45 is a horizontal synchronization detection unit, 46 is a vertical synchronization detection unit, 47 is a horizontal synchronization protection unit, and 48 is a vertical synchronization protection unit.

The analog sync separation unit 41 slices the analog composite video signal supplied to the input terminal IN while passing the waveform through a low-pass filtering circuit to dull the waveform and then clamping the tip of the horizontal sync signal. By performing SYNC chip slice processing, a composite synchronization signal is separated from the video signal, and supplied to the horizontal synchronization detection unit 45 and the vertical synchronization detection unit 46. The analog sync separation unit 41 generates a burst flag used for extracting a color burst from the composite video signal in parallel with the sync separation process, and generates a clock flag.
Supply 42.

The horizontal synchronization detection section 45 has a configuration in which the same function as the digital horizontal synchronization detection section 5 described in the embodiment of FIG. 1 is realized by an analog circuit. In other words, the analog horizontal synchronization detection unit 45 binarizes the analog composite synchronization signal supplied from the analog synchronization separation unit 41, and detects the falling point in synchronization with the 4fsc clock signal, thereby detecting the clock signal. The horizontal synchronization detection signal having a width of one cycle is generated and output to the horizontal synchronization protection circuit 47 at the subsequent stage.

The vertical synchronization detector 46 has a configuration in which the same function as the digital vertical synchronization detector 6 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, the analog horizontal synchronization detection unit 46 binarizes the analog composite synchronization signal supplied from the analog synchronization separation unit 41, passes it through a low-pass filtering circuit, latches it in synchronization with the clock signal 2Hck,
The latch output is selectively latched in one jump in synchronization with the clock signal Hck, thereby generating a vertical synchronization detection peripheral signal having a frame period, and supplying the signal as an external frame pulse to the subsequent frame synchronization protection circuit 48.

The horizontal synchronization protection circuit 47 has substantially the same configuration as the horizontal synchronization protection circuit 7 shown in FIGS. 1 and 6, and performs almost the same operation. The vertical synchronization protection circuit 48 has substantially the same configuration as the vertical synchronization protection circuit 8 shown in FIGS. 1 and 7, and performs almost the same operation. However,
A frame synchronization protection circuit different from the synchronization separation circuit of FIG.
At 48, the VBLK signal is not created, and the hunting operation is performed by the horizontal synchronization protection circuit 47 even during the vertical retrace period.

FIG. 10 is a block diagram showing a configuration of a sync separation circuit according to the fourth invention.
Is a clock generation unit, 55 is a horizontal synchronization detection unit, 56 is a vertical synchronization detection unit, 57 is a horizontal synchronization protection unit, and 58 is a vertical synchronization protection unit.

The analog sync separation unit 51 slices the analog composite video signal supplied to the input terminal IN by passing it through a low-pass filtering circuit, dulling the waveform, and then clamping the tip of the horizontal sync signal. By performing the SYNC chip slice processing, the composite synchronization signal is separated from the video signal and supplied to the horizontal synchronization detection unit 55. The analog sync separation unit 51 detects a vertical retrace period by passing the composite sync signal separated from the video signal through a low-pass filtering circuit, and detects a vertical sync period within the detected vertical retrace period. Feed to separation 56. The analog sync separation unit 51
In parallel with the synchronization separation processing, a burst flag used for extracting a color burst from the composite video signal is generated and supplied to the clock generation unit 52.

The horizontal synchronization detecting section 55 has a configuration in which the same function as that of the digital horizontal synchronization detecting section 5 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, the analog horizontal synchronization detection unit 55 binarizes the analog composite synchronization signal supplied from the analog synchronization separation unit 51, and detects the falling point in synchronization with the 4fsc clock signal, thereby detecting the clock signal. The horizontal synchronization detection signal having a width of one cycle is generated and output to the horizontal synchronization protection circuit 57 at the subsequent stage.

The vertical synchronization detecting section 56 has a configuration in which the same function as the digital vertical synchronization detecting section 6 described in the embodiment of FIG. 1 is realized by an analog circuit. That is, the analog horizontal synchronization detection unit 56 binarizes the synchronization detection signal supplied from the analog synchronization separation unit 51, latches it in synchronization with the clock signal 2Hck, and outputs the latched output to the clock signal Hck.
By selectively latching one jump at a time in synchronism with the above, a vertical synchronization detection peripheral signal having a frame cycle is generated, and this is supplied to the subsequent frame synchronization protection circuit 58 as an external frame pulse.

The horizontal synchronization protection circuit 57 has almost the same configuration as the horizontal synchronization protection circuit 7 shown in FIGS. 1 and 6, and performs almost the same operation. The vertical synchronization protection circuit 58 has substantially the same configuration as the vertical synchronization protection circuit 8 shown in FIGS. 1 and 7, and performs almost the same operation. However,
A frame synchronization protection circuit different from the synchronization separation circuit of FIG.
At 58, no VBLK signal is created, and at the horizontal synchronization protection circuit 57, a hunting operation is performed even during the vertical retrace period.

FIG. 11 is a block diagram showing a configuration of a sync separation circuit of an embodiment according to the fifth invention. In this sync separation circuit, the components denoted by the same reference numerals as those of the sync separation circuit of FIG. 10 have the same configuration as the corresponding portions of the sync separation circuit shown in FIG. Therefore, a duplicate description thereof will be omitted.

In this synchronization separation circuit, a burst flag for extracting a color burst used in the clock generation unit 52 is output from the vertical synchronization protection unit 58 and a burst timing signal generated by the horizontal synchronization protection unit 57 in the AND circuit 59.
It is created from the logical product with the VBLK signal.

(Effect of the Invention) Since the sync separation circuit of the present invention has the above-described configuration, the timing accuracy of a value approximately one digit higher than the display timing accuracy created by the conventional sync separation circuit can be obtained. There is an effect that it can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a sync separation circuit according to the first invention, FIG. 2 is a block diagram showing a configuration of an analog sync separation circuit of FIG. 1, FIG. 3, FIG. FIG. 3 is a waveform diagram for explaining the operation of the sync separation circuit of FIG.
FIG. 6 is a block diagram showing the configuration of the horizontal synchronization protection unit 7 of FIG. 1, FIG. 7 is a block diagram showing the configuration of the vertical synchronization protection unit 8 of FIG. 1, and FIG. FIG. 9 is a block diagram showing a configuration of a sync separation circuit according to the third aspect of the present invention, and FIG. 10 is a block diagram showing a configuration of a sync separation circuit according to the fourth aspect of the present invention. FIG. 11 is a block diagram showing the configuration of the synchronization separating circuit according to the fifth invention. 1, 41, 51 ... Analog sync separation section, 2, 42, 52 ... Clock generation section, 3 ... A / D conversion section, 4 ... Color burst removal section, 5, 45, 55 ... Horizontal sync detection Division, 6, 46, 56
…… Vertical sync detector, 7, 47, 57… Horizontal sync protector,
8, 48, 58 ... Frame synchronization protection unit.

Claims (5)

(57) [Claims] An analog synchronizing separation section for generating a burst flag and a clamp pulse while separating a synchronizing signal from an analog composite video signal; and A clock generation unit that extracts a color burst signal and generates a clock signal having a frequency four times that of the color burst signal; and the clock generation unit performs pedestal clamping on the analog video signal using a clamp pulse generated by the analog synchronization separation unit. An A / D conversion unit for converting to a digital composite video signal using a clock signal having a frequency four times the frequency of the generated color burst signal; and an output of the A / D conversion unit and a signal obtained by delaying the output by one line. A color burst removing section for adding and removing a color burst signal included in the digital composite video signal A horizontal sync detection section that binarizes the digital composite video signal from which the color burst has been removed and generates a horizontal sync detection signal indicating the position of the horizontal sync signal included in the digital composite video signal, and counts a clock signal having a dot frequency of 4fsc Dot decoder, a dot decoder that decodes the count value of the dot counter and outputs various timing signals, a signal indicating the last dot position of one line output from the dot decoder, or the horizontal synchronization detection signal. Clearing means for clearing the dot counter with one of the masked horizontal synchronization detection signals masked, a leak integration circuit receiving a logical product of a window pulse output from the dot decoder and the horizontal synchronization detection signal, and the leakage integration Masking the horizontal synchronization detection signal when the integrated value of the circuit is equal to or greater than a predetermined value; A horizontal synchronization protection section comprising mask control means for enabling the signal; and a vertical synchronization section for binarizing the output of the A / D conversion section, detecting the position of a vertical synchronization signal included in the output, and generating a frame pulse of one frame period. A detection unit, a line counter that counts a clock signal of a line frequency, a line decoder that decodes a count value of the line counter and outputs various timing signals, and a final line position of one frame output from the line decoder. Clear means for clearing the line counter with either a signal indicating the frame counter or a masked frame pulse selectively masking a frame pulse supplied from the vertical synchronization detection unit, a frame pulse output from the line decoder and the vertical synchronization Leakage integration circuit that receives logical AND with the frame pulse supplied from the detector And a frame synchronization protection unit comprising mask control means for validating a mask for a frame pulse supplied from the vertical synchronization detection unit when the integration value of the leaky integration circuit is equal to or more than a predetermined value. Synchronization separation circuit. 2. An analog sync separation unit for generating a burst flag while separating a synchronization signal from an analog composite video signal, and a color burst signal from the analog video signal under the burst flag generated by the analog sync separation unit. A clock generation unit for generating a clock signal having a frequency four times as high as that of the color burst signal generated by the clock generation unit while pedestal-clamping the analog video signal using a predetermined clamp pulse. An A / D converter for converting the digital composite video signal into a digital composite video signal using a clock signal of a frequency; and adding the output of the A / D converter and a signal obtained by delaying the output by one line to the digital composite video signal. A color burst elimination unit that eliminates the contained color burst signal, and a digital composite with the color burst eliminated A horizontal sync detection section that binarizes the video signal and creates a horizontal sync detection signal indicating the position of the horizontal sync signal included in the video signal; a dot counter that counts a clock signal having a dot frequency of 4 fsc; a count of this dot counter A dot decoder for decoding values and outputting various timing signals; a signal indicating the last dot position for one line output from the dot decoder; or a masked horizontal synchronization detection signal selectively masking the horizontal synchronization detection signal Clear means for clearing the dot counter, a leak integration circuit receiving the logical product of the window pulse output from the dot decoder and the horizontal synchronization detection signal, and an integrated value of the leak integration circuit being equal to or greater than a predetermined value. Horizontal synchronization maintaining means comprising mask control means for enabling masking of the horizontal synchronization detection signal in a range. A vertical synchronization detection unit that binarizes the output of the A / D conversion unit, detects the position of the vertical synchronization signal included in the output, and creates a frame pulse of one frame cycle, and counts the clock signal of the line frequency A line counter, a line decoder that decodes the count value of the line counter and outputs various timing signals, a signal indicating the last line position for one frame output from the line decoder, or supplied from the vertical synchronization detection unit. Clearing means for clearing the line counter with one of masked frame pulses selectively masking a frame pulse to be output, and a logic between a frame pulse output from the line decoder and a frame pulse supplied from the vertical synchronization detection unit. A leaky integration circuit that receives the product and an integrated value of the leaky integration circuit is equal to or greater than a predetermined value. A frame synchronization protection unit comprising mask control means for enabling masking of a frame pulse supplied from the vertical synchronization detection unit within a range; and a clamp pulse generated by a synchronization decoder of the horizontal synchronization protection unit. Means for supplying the A / D converter only when the mask is valid in both the protection unit and the vertical synchronization protection unit and is not within the vertical retrace period detected by the vertical synchronization protection unit. A sync separation circuit. 3. An analog sync separation section for generating a burst flag while separating a composite synchronization signal from an analog composite video signal, and outputting the separated composite synchronization signal and the generated burst flag. A clock generation unit that extracts a color burst signal from the analog composite video signal based on the output burst flag and generates a clock signal having a frequency four times that of the color burst signal; and a composite synchronization signal output from the analog synchronization separation unit. A horizontal synchronization detection unit that generates a horizontal synchronization detection signal indicating the position of the horizontal synchronization signal included in the value, a dot counter that counts a clock signal with a dot frequency of 4 fsc, and decodes the count value of this dot counter Dot decoder for outputting various timing signals, and 1 Clear means for clearing the dot counter with either a signal indicating the final dot position of the IN portion or a masked horizontal synchronization detection signal obtained by selectively masking the horizontal synchronization detection signal, a window pulse output from the dot decoder; A horizontal synchronizing protection unit comprising a leaky integrating circuit receiving a logical product of the horizontal synchronizing detection signal and mask control means for validating a mask of the horizontal synchronizing detection signal when an integrated value of the leaky integrating circuit is a predetermined value or more; A vertical synchronization detection section for binarizing the composite synchronization signal output from the analog synchronization separation section, detecting the position of the vertical synchronization signal included in the composite synchronization signal and generating a frame pulse of one frame cycle, A line counter that counts, decodes the count value of this line counter, and outputs various timing signals. A line decoder, a signal indicating the last line position of one frame output from the line decoder, or a masked frame pulse selectively masking a frame pulse supplied from the vertical synchronization signal detection unit. Clearing means for clearing a counter, a leaky integration circuit receiving a logical product of a frame pulse output from the line decoder and a frame pulse supplied from the vertical synchronization detection unit, and an integrated value of the leaky integration circuit being not less than a predetermined value And a frame synchronization protection unit comprising mask control means for validating a mask for a frame pulse supplied from the vertical synchronization detection unit. 4. An analog sync separation unit for generating a burst flag while separating a horizontal sync signal and a vertical sync signal from an analog composite video signal, and outputting the separated horizontal sync signal, vertical sync signal, and the generated burst flag. A clock generation unit that extracts a color burst signal from the analog composite video signal based on the burst flag output from the analog sync separation unit and generates a clock signal having a frequency four times the color burst signal; A horizontal synchronization detection unit that generates a horizontal synchronization detection signal indicating the position of the horizontal synchronization signal included in the horizontal synchronization signal, and a dot counter that counts a clock signal having a dot frequency of 4 fsc. This dot decoder decodes the count value of the counter and outputs various timing signals. Clearing means for clearing the dot counter with either a signal indicating the last dot position of one line output from a decoder or a masked horizontal synchronization detection signal obtained by selectively masking the horizontal synchronization detection signal, the dot decoder And a mask control means for enabling the mask of the horizontal synchronization detection signal when the integrated value of the leakage integration circuit is greater than or equal to a predetermined value. A horizontal synchronization protection unit, and a vertical synchronization detection unit that binarizes a vertical synchronization signal output from the analog synchronization separation unit, detects a position of the vertical synchronization signal included in the binary synchronization signal, and creates a frame pulse of one frame period. , Line counter that counts the clock signal of the line frequency, decodes the count value of this line counter A line decoder that outputs various timing signals, a signal indicating the last line position for one frame output from the line decoder, or a masked frame pulse that selectively masks a frame pulse supplied from the vertical synchronization detection unit. Clearing means for clearing the line counter in any one of the above, a leaky integration circuit receiving a logical product of a frame pulse output from the line decoder and a frame pulse supplied from the vertical synchronization detecting section, and integration of the leaky integration circuit And a frame synchronization protection unit comprising mask control means for enabling masking of a frame pulse supplied from the vertical synchronization detection unit when the value is equal to or greater than a predetermined value. 5. An analog synchronizing separator for separating a horizontal synchronizing signal from a vertical synchronizing signal from an analog composite video signal and outputting the same, and extracting a color burst signal from the analog composite video signal using a predetermined burst flag. A clock generation unit for generating a clock signal having a frequency four times as high as the above; a horizontal synchronization signal output from the analog synchronization separation unit is binarized to generate a horizontal synchronization detection signal indicating the position of the horizontal synchronization signal included in the horizontal synchronization signal A horizontal synchronization detector, a dot counter that counts a clock signal having a dot frequency of 4 fsc, a dot decoder that decodes the count value of the dot counter and outputs various timing signals, and one line output from the dot decoder Masked water selectively masking the signal indicating the final dot position of Clearing means for clearing the dot counter with one of the synchronization detection signals, a leaky integration circuit receiving the logical product of the window pulse output from the dot decoder and the horizontal synchronization detection signal, and an integrated value of the leaky integration circuit being predetermined. A horizontal synchronization protection unit comprising mask control means for validating the mask of the horizontal synchronization detection signal when the value is equal to or more than a value; a vertical synchronization signal included in the binary synchronization signal output from the analog synchronization separation unit by binarization; A vertical synchronization detector for detecting the position of the frame and generating a frame pulse of one frame period, a line counter for counting a clock signal of a line frequency, and a line decoder for decoding the count value of the line counter and outputting various timing signals , A signal indicating the last line position of one frame output from this line decoder. Clear means for clearing the line counter with one of masked frame pulses obtained by selectively masking a frame pulse supplied from the vertical synchronization detection unit, a frame pulse output from the line decoder and the vertical synchronization detection unit And a mask control means for enabling masking of a frame pulse supplied from the vertical synchronization detecting section when an integrated value of the leakage integration circuit is equal to or greater than a predetermined value. A clock synchronization unit provided that the burst flag generated by the dot decoder of the horizontal synchronization protection unit is outside the vertical retrace period detected by the line decoder of the vertical synchronization protection unit. And a burst flag supply unit for supplying the burst flag to the synchronization separation circuit.