JP2953402B2 - Vertical sync detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vertical synchronization detection circuit, and more particularly to a vertical synchronization detection circuit for detecting a vertical synchronization signal from a digitized video signal.

[0002]

2. Description of the Related Art In broadcasting stations and the like, connections between devices have been made through digital interfaces.
A video signal digitized by a clock having a frequency four times the color subcarrier frequency is used. A vertical synchronization detection circuit for detecting a vertical synchronization signal from a digital video signal includes a filter for attenuating a color subcarrier component, a level comparator for performing synchronization separation, and an integration circuit, as in the case of an analog video signal. I have.

FIG. 3 shows a conventional example of a vertical synchronization detecting circuit for detecting a vertical synchronization signal from a digital video signal. A digital filter 21 for attenuating the color subcarrier component of the digital video signal S1, a comparator 22 for comparing the digital filter output with a comparison reference level Ds to detect a synchronization signal and output a 1-bit level comparison result, An integration circuit 23 that integrates the output of the comparator to generate a vertical synchronization output S3. In addition,
The frequency of the clock CS is four times the color subcarrier frequency.

The digital video signal S1 is subjected to chrominance sub-carrier component attenuation by the digital filter 21, and
The comparator 22 compares the reference level with the reference level for detecting the synchronization signal, and the level comparison result indicating the detection of the synchronization signal is integrated by the integration circuit 23 to obtain a vertical synchronization output as shown in FIG.

When the digital filter 21 is not provided, when an excessive color signal component is inputted, as shown in FIG. 4B, the excessive color signal component is erroneously detected as a vertical synchronizing signal. . In order to prevent erroneous detection due to such an excessive color signal component, a digital filter 21 is provided to attenuate the color subcarrier component.

[0006]

As described above, the conventional vertical synchronization detection circuit uses a digital filter for attenuating the color subcarrier component in order to prevent an erroneous detection of an excessive color signal component as vertical synchronization. doing. However, such a digital filter is configured by a register, an adder circuit, and the like, and the circuit scale becomes large, which is an obstacle to miniaturization and cost reduction of the circuit.

An object of the present invention is to provide a vertical synchronization detecting circuit which can reduce erroneous detection due to excessive color signal components without using a digital filter for attenuating color subcarrier components.

[0008]

According to the vertical synchronization detection circuit of the present invention, the output of the comparator for detecting the synchronization signal by comparing the levels of the digital video signals indicates the detection of the synchronization signal continuously for a predetermined number of times or more. Only when detected as a synchronization signal, erroneous detection of vertical synchronization due to an excessive color signal component being detected as a synchronization signal by a comparator is reduced. Specifically, the color subcarrier frequency 2
A vertical synchronization detection circuit for detecting a vertical synchronization signal from a digital video signal digitized by a clock having a frequency of twice or more, and synchronizing with a level of the digital video signal ;
The level of the synchronization signal is compared with a preset reference level for detecting a signal in accordance with the clock.
And a comparator that outputs a 1-bit level comparison result when it is determined that
A continuity detecting circuit that outputs a 1-bit continuous detection signal when the level comparison result of the bit is continuously output a predetermined number of times or more, and integrates the 1-bit continuous detection signal to generate a vertical synchronization signal. An integration circuit for generating the continuity detection circuit
Means that the clock frequency is 2N times the color subcarrier frequency
(N is a positive integer), the 1-bit level ratio
When the comparison result is received at least (N + 1) times consecutively
The 1-bit continuous detection signal is output .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The digital signal S1 is compared with the reference level to detect the synchronization signal by comparing the digital level with the reference level.
Comparator 1 that outputs bit level comparison result D1
1, a continuity detecting circuit 12 for detecting the continuity of the level comparison result of the comparator and outputting a 1-bit continuous detection signal D2, and a vertical synchronization output S by integrating the continuous detection signal D2.
And an integrating circuit 13 for generating the second signal. The digital video signal S1 is a video signal digitized by a clock having a frequency four times the color subcarrier frequency, and the same clock is used as the clock Cs for the comparator 1
1 is input.

When the digital video signal is, for example, 8
In the case of bits, the specified level value of the digital video signal is
For example, as shown in FIG. 2A, the sync signal level is "4", the sync signal pedestal level is "60", the color burst is "32", and the white level is "200". In this case, if the set value of the comparison reference level Ds of the comparator 11 is, for example, “8”, the vertical synchronization signal can be detected without being affected by a color burst or a normal color signal component.

The comparator 11 compares the level of the digital video signal S1 with a comparison reference level Ds in synchronization with the clock Cs. When the digital video signal level is lower than the comparison reference level, the level comparison result D1 is set to "1" to indicate the detection of the synchronization signal.

Assume that an excessively large color signal component as shown in FIG. Since the chrominance signal component is a signal obtained by modulating a chrominance subcarrier with a chrominance signal, for example, as shown in FIG. It becomes smaller than the level, and is detected as a synchronization signal by the comparator 11. That is, when an excessive color signal component is input, the level comparison result D1 is “1”.
It runs twice but never more than three times.

The continuity detecting circuit 12 includes a register and an AND
A continuous detection signal D2 is set to "1" when the level comparison result D1 of the comparator 11 is "1" three or more consecutive times, and otherwise "0" is output. By providing such a continuity detection circuit 12, even if an excessive color signal component is erroneously detected as a synchronization signal by the comparator 11, this erroneous detection can be eliminated. Then, as for the vertical synchronizing signal, the level comparison result of the comparator 11 becomes "1" three or more consecutive times, so that the vertical synchronizing signal can be reliably detected.
Integrator circuit 13 generates a vertical synchronization output S2 integrates the continuous detection signal D2. By the way, for the horizontal sync signal
Also, the level comparison result of the comparator 11 is continuous three times or more.
To “1”, but during the horizontal synchronization signal period, the vertical synchronization signal
Since the period is sufficiently shorter than the period, the time constant of the integrating circuit 13 is selected.
The horizontal sync signal and the vertical sync signal.
Can be detected separately.

In the continuity detection circuit 12 described above,
Although it is detected that the level comparison result “1” of the comparator is repeated three times or more, the number of times the “1” is continuously repeated may be four or more times. By increasing the number of times, it is possible to reduce erroneous detection due to an excessive input of not only an excessive color signal component but also a frequency component lower than the color subcarrier frequency.

Although the sampling frequency for digitization is set to four times the color subcarrier frequency, there is no particular limitation as long as it is twice or more. Now, let the sampling frequency be 2N times the color subcarrier frequency (N is a positive integer)
In this case, when the level comparison result “1” of the comparator is continuous at least (N + 1) times or more, the continuity detection circuit 12 may detect it as the original synchronization signal.

[0017]

As described above, according to the present invention, when the output of the comparator for detecting the synchronizing signal by comparing the levels indicates that the synchronizing signal has been detected continuously for a predetermined number of times or more, this is used as the original synchronizing signal. By judging that, erroneous detection due to excessive color signal components can be removed,
It is not necessary to use a digital filter having a large circuit scale as in the related art, and therefore, it is possible to reduce the size and cost of the circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2A is a diagram showing a specified level value of a digital video signal, and FIG. 2B shows an example of a level comparison sampling point when an excessive color signal component is input.

FIG. 3 is a block diagram showing a conventional example of a vertical synchronization detection circuit.

FIG. 4 is a waveform diagram showing vertical synchronization detection, and FIG.
Shows normal vertical synchronization detection, and FIG. 4B shows a state where an excessive color signal component is erroneously detected.

[Explanation of symbols]

 11 Comparator 12 Continuity detection circuit 13 Integrator circuit D1 Level comparison result D2 Continuous detection signal Ds Comparison reference level S1 Digital video signal S2 Vertical synchronization output

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-229778 (JP, A) JP-A-3-216076 (JP, A) JP-A-63-305673 (JP, A) JP-A-2- 43876 (JP, A) JP-A-8-223447 (JP, A) JP-A-4-255173 (JP, A) JP-A-6-62272 (JP, A) JP-A-63-557 (JP, U) Japanese Patent Publication No. 7-83436 (JP, B2) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 5/10

Claims (1)

(57) [Claims] 1. A vertical synchronization detecting circuit for detecting a vertical synchronizing signal from a digital video signal digitized by a clock having a frequency of at least twice the frequency of a color subcarrier frequency, the level and the synchronizing signal of the digital video signal being detected. Was
A comparator that outputs a 1-bit level comparison result when it is determined that the signal is a synchronization signal by comparing the level with a preset reference level in accordance with the clock.
And this comparator compares the 1-bit level
A continuity detection circuit for outputting a 1-bit continuous detection signal when the output continuously fruit more than a predetermined number of times, the 1 bit
Integration of continuous detection signals integrated to the generating a vertical synchronizing signal
A continuity detection circuit, wherein
When the frequency is 2N times the color subcarrier frequency (N is a positive integer)
In some cases, the 1-bit level comparison result is at least
(N + 1) consecutive reception of the 1 bit
Vertical sync detection circuit, wherein also be output from the detection signal.