JPS6151831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data signal reproducing device for television teletext broadcasting.

Recently, television teletext broadcasting, which is used for data signal transmission, facsimile transmission, program identification code transmission, and software transmission to home computers, usually converts image data into binary NRZ format.
The image data is superimposed on the vertical retrace period of the video signal in the form of a signal, and in this case, the image data is transmitted in the form of a data packet in units of one horizontal scanning section. This data packet consists of a header section and an information data section. In the header section, a clock run-in signal and a framing signal, which are binary (0.1) signals for digital signal synchronization (bit synchronization and frame synchronization), are transmitted. In the data part, a binary (0.1) encoded pixel data signal is transmitted.

However, on the receiving side, these clock run-in signals, framing signals, and pixel data signals are affected by level fluctuations, S/N ratio deterioration, waveform distortion due to multiple propagation, etc., resulting in erroneous level judgments of these signals. Something happened.

The purpose of the present invention is to minimize the above-mentioned misperception of the level judgment, and to
By using the clock run-in signal that is always provided at the beginning of the pixel data signal, which is a digital signal superimposed during the horizontal scanning period, it is possible to eliminate the effects of level fluctuations, S/N ratio deterioration, waveform distortion due to multiple propagation, etc. The purpose of the present invention is to generate an optimal reference voltage for level determination, and use this reference voltage to determine the level of a pixel data signal.

First, a block diagram of a first embodiment of the present invention is shown in FIG.

In FIG. 1, 10 is a delay circuit to which a data input signal _S1 , which is a signal, is input, and outputs a data delay signal _S5 in which the data input signal _S1 is delayed by a time T _R . 20 is a monostable multivibrator circuit, which receives the horizontal synchronizing pulse _S2 and outputs a multivibrator output signal _S3 , which is a binary signal that remains at a high level for a time T _S from the falling edge of the horizontal synchronizing pulse _S2 . do. 30 is a monostable multivibrator circuit, and the multivibrator output signal
The multivibrator output signal is a binary signal that remains at a high level for T _R time from the time when _{S3 is input and the multivibrator output signal S3 falls} .
Output S ₄ . 40 is an analog switch,
A data input signal S ₁ is input, a multivibrator output signal S ₄ is input as a control signal, and the switch is turned on only while the multivibrator output signal S ₄ is at a high level, and the data input signal S ₁ is output. 50 is an integrating circuit, which receives the data input signal S ₁
is input to one end of the resistor _R1 , and the other end is grounded via the capacitor _C1 and outputs an integrated output signal _S6 . 60 is a comparator circuit, to which the data delay signal _S5 is input to the non-inverting input terminal (+);
The integral output signal S ₆ is input to the inverting input terminal (-), and the data output signal S ₇ is a binary signal that becomes high level when the level of the data delay signal S ₅ is higher than the level of the integral output signal S ₆ . Output. 70 is an analog switch, the integrated output signal S ₆ is input to one end, the other end is grounded, and the horizontal synchronization pulse S ₂ is input as a control signal, and the horizontal synchronization pulse S ₂ is switched only during the period from the falling point to the rising point. The switch turns on and shunts the integral output signal _S6 to ground.

The operation of this first embodiment will now be explained with reference to the operational waveform diagram of FIG. 2.

The data input signal S ₁ includes a clock run-in signal (period TC _RI ), a framing signal (period T _FRC ), and a data signal (period T _D ) within one horizontal scanning period (1H).
_C ), and each signal has an amplitude of Vp (Vp=
2Vm), which is a binary (0.1) signal.

First, the level of the integrated output signal _S6 , which is the reference voltage for level determination, will be explained.

Period T _S of the multivibrator output signal _S3 output from the monostable multivibrator circuit 20
is set to the period from the time when the horizontal synchronizing pulse in the data input signal _S1 falls to the time when the clock run-in signal appears, and is the period T of the multivibrator output signal _S4 output from the monostable multivibrator circuit 30. Since _R is set to the period T _CRI during which the clock run-in signal exists, the analog switch 40 turns on coincides with the time when the clock run-in signal exists. Further, when the analog switch 70 is turned on, it is a certain period of time from the time when the multivibrator output signal _S3 becomes high level. Therefore, at the time when the horizontal synchronizing pulse _S2 falls, the output of the integrating circuit 50 is grounded, so that the level of the integrated output signal _S6 becomes zero, and until the time A when the clock run-in signal appears, the analog switch 40 is Since it is off, no signal is input to the integrating circuit 50, and the level of the integrated output signal _S6 is zero. During the period from point A to point B when the analog switch 40 is turned on, the capacitor _C1 is charged every time the clock run-in signal becomes high level.
At the end point when the clock run-in signal is output, that is, at point B, the level of the integral output signal _S6 is Vm.
The time constant (t=
R ₁ C ₁ ) is determined. Note that during this period from point A to point B, ripples occur in the integral output signal _S6 . Next horizontal sync pulse from point B
Since the capacitor _C1 is not charged or discharged until the analog switch 70 is turned on by the fall of _S2 , the level of the integrated output signal _S6 becomes Vm, and this level Vm becomes the reference voltage for level determination.

The integrated output signal _S6 , which is the reference voltage for level determination determined in this way, is input to the inverting input terminal (-) of the comparator circuit 60, and the data input signal _S1 is input to the non-inverting input terminal (+). The period T _CRI during which the clock run-in signal is present by the circuit 10
A data delay signal delayed by the same period T _R as
_S5 is input, and the level of the data input signal _S1 , that is, the data delay signal, is substantially determined after point B. Therefore, when the level of the data delay signal S ₅ is high (high level) with respect to the level of the integrated output signal S ₆ , the data output signal S 7 becomes a high level, and when it is low (low level), the data output signal S ₇ becomes a low level. Output.

Second, a block diagram of a second embodiment of the present invention is shown in FIG.

In this second embodiment, the signal input to the analog switch 40 is changed from the signal input to the analog switch 40 in order to eliminate the error caused by ripples in the period from point A to point B in the integral output signal _S6 in the first embodiment. In the example data input signal S ₁ and without data input signal S ₁
The ripples mentioned above are removed by using a signal that has been subjected to arithmetic processing.

In FIG. 3, the block configuration is the same as the second embodiment except for the signal input to the analog switch 40.

The block configuration for obtaining the signal input to the analog switch 40 is shown below.

11 is a delay circuit which receives the data input signal S ₁ and outputs a data delay signal S ₁₀ delayed by TC, which is one half of one period of the clock run-in signal with a duty ratio of 50%. . 12 is an adder to which the data input signal S ₁ and the data delay signal S ₁₀ are input, and the signal level is one half of the signal level obtained by adding the data input signal S ₁ and the data delay signal S ₁₀ .
outputs the summed signal _S11 at the level of . This addition signal _S11 is then input to the analog switch 40.

The operation of this second embodiment will now be explained with reference to the operational waveform diagram of FIG. 4.

The level of the integral output signal _S6 is zero during the period from the time when the horizontal synchronizing pulse _S2 falls to the time when the clock run-in signal in the data input signal _S1 appears (point A). After point A, analog switch 40
is turned on, the addition signal S ₁₁ at the level of Vm is input to the integrating circuit 50, and the capacitor C ₁ is charged according to the time constant (t=R ₁ C ₁ ), thereby increasing the level of the integrated output signal S ₆ . increases exponentially from zero to Vm. Then, from point B onward, the integral output signal S ₆ continues until the falling edge of the next horizontal synchronizing pulse S ₂
The level of is maintained at Vm. This integral output signal
_S6 serves as a reference voltage for level determination, and is compared with the data delay signal _S5 in the comparator circuit 60, and a data output signal _S7 is output.

In other words, the difference between the first and second embodiments is that in the first embodiment, the signal input to the integrating circuit 50 that produces the integrated output signal _S6 , which is the reference voltage for level determination, is input to the clock line input. As a signal, the second
In this embodiment, the addition signal _S11 always has a level (Vm) that is half the level (Vp=2Vm) of the clock run-in signal.

As described above, according to the present invention, level fluctuation, S/N
The optimum reference voltage for level judgment, which is not affected by ratio deterioration, waveform distortion due to multiple propagation, etc.
A pixel data signal with an accurate level can be reproduced without being affected by level determination of a data input signal, that is, a character signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention;
2 is an operating waveform diagram of the first embodiment, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. 4 is a diagram of the second embodiment of the present invention.
FIG. 3 is an operational waveform diagram of the embodiment. 10.11: Delay circuit, 12: Adder, 20.
30: Monostable multivibrator circuit, 40.7
0: Analog switch, 50: Integrating circuit, 60:
Comparator circuit, S ₁ : Data input signal, S ₂ : Horizontal sync pulse, S ₃ , S ₄ : Multivibrator output signal, S ₅ , S ₁₀ : Data delay signal, S ₆ : Integral output signal, S ₇ : Data output Signal, S ₁₁ : Addition signal.

Claims (1)

[Claims] 1. A television in which a data packet signal in which a binary encoded clock run-in signal and a pixel data signal representing characters, figures, etc. are successively formed is transmitted in units of one horizontal scanning section. A device applied to digital teletext broadcasting, which detects a horizontal synchronization pulse transmitted before the data packet signal, and detects the end point of the period in which the clock run-in signal exists from the falling point of this horizontal synchronization pulse. The capacitor in the integrating circuit is charged by the data packet signal only during the period when the first circuit delays and outputs the data packet signal and the clock run-in signal of the data packet signal exists, and the time constant of the integrating circuit is The potential of the capacitor is set to be half the amplitude level of the clock run-in signal at the end of the period in which the clock run-in signal exists, and the potential of the capacitor is set to be one half of the amplitude level of the clock run-in signal, and the capacitor is a second circuit that draws out the potential of the capacitor, the circuit being discharged to , and a third circuit that passes only the data packet signal having a level exceeding the extracted potential. 2 Applicable to television teletext multiplexing in which a data packet signal consisting of a binary encoded clock run-in signal and a pixel data signal representing characters, figures, etc. is successively transmitted in units of one horizontal scanning section. A device that detects a horizontal synchronizing pulse transmitted before the data packet signal, and detects the time from the falling edge of the horizontal synchronizing pulse to the end of the period in which the clock run-in signal exists, and detects the data packet. a first circuit that outputs a first signal that is a delayed signal; and a second circuit that outputs a first signal that is a delayed signal;
a second circuit that outputs a second signal obtained by delaying the data packet signal by a time obtained by subtracting one half of the time, and adding the second signal and the data packet signal to delay the data packet signal. 2 of the level of this signal from the rising point of
a third signal that outputs a third signal having a level of
A capacitor in the circuit and an integrating circuit having a predetermined time constant only during the period when the clock run-in signal exists is charged by the third signal, and the capacitor is abruptly discharged by the falling edge of the horizontal synchronization pulse. a fourth circuit that extracts the potential of the capacitor as a fourth signal; a first signal outputted from the first circuit and a fourth signal outputted from the fourth circuit are compared; and a fifth circuit that passes only the first signal exceeding the potential of the four signals.