JP3329149B2 - Clamp pulse generation method and circuit thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp pulse generating method used in, for example, a television receiver and the like and a circuit therefor.

[0002]

2. Description of the Related Art Generally, television signals such as NTS
TV signals such as C and PAL (hereinafter referred to as SD signals)
, A so-called sync-tip clamp pulse is generated at the tip of the synchronizing signal of the television signal.

FIG. 7 is a block diagram of a circuit for generating such a sync tip clamp pulse. As shown in FIG. 7, this clamp pulse generation circuit is a synchronous separation circuit 2
And a pulse generation circuit 4. 7, reference numeral 1 denotes an input terminal of the circuit, 3 denotes an output terminal of the sync separation circuit, and 5 denotes an output terminal of the pulse generation circuit 4.

Hereinafter, a conventional sync-tip clamp pulse generation circuit will be described with reference to a block diagram of FIG. 7 and a waveform diagram of FIG. As shown in FIG. 7, a composite signal including a television video signal, a synchronization signal, and the like is input to the input terminal 1. The synchronizing separation circuit 2 allows the composite synchronizing signal including only the horizontal synchronizing signal and the vertical synchronizing signal, the so-called composite sync signal CS
YNC is taken out. FIG. 8A shows the waveform of such a composite sync signal CSYNC.

A composite synchronizing signal, ie, a composite sync signal CSYNC generally indicates a horizontal / vertical synchronizing signal as well as a horizontal / vertical blanking signal and a color / burst signal. The vertical blanking signal and the color burst signal are irrelevant to the present invention, and therefore will not be described.

The composite sync signal CSY shown in FIG.
The NC is inverted, and an S_SEP pulse shown in FIG. 8B is generated and output to the output terminal 3 of the separation circuit 2.

S_SE obtained by the sync separation circuit 2
The P pulse is, as shown in FIG. 8B, a horizontal synchronizing signal (H
-SYNC) and a vertical synchronizing signal (V-SYNC). This S_SEP pulse is output to the output terminal 3 of the synchronization separation circuit 2 and is input to the pulse generation circuit 4 at the next stage of the synchronization separation circuit 2. The pulse generation circuit 4 generates a clamp pulse as shown in FIG. 8C and outputs it to the output terminal 5.

In the pulse generation circuit 4, S_SEP
When the ramp signal RAMP is generated by the rise of the pulse, a clamp pulse is generated at the position of the sync chip in both the horizontal synchronization signal (H-SYNC) and the vertical synchronization signal (V-SYNC). Less than,
The operation of the pulse generation circuit 4 will be specifically described with reference to FIG.

FIG. 9 shows a vertical synchronizing signal (V-SYN) shown in FIG.
C) is an enlarged view of the portion. 9A is a vertical synchronization pulse, FIG. 9B is an S_SEP pulse, and FIG.
(C) shows each of the clamp pulses. In the pulse generation circuit 4, as shown in FIG.
The ramp signal RAMP is generated by the rising edge of the EP pulse. Then, two thresholds of a low level threshold V _SON and a high level threshold V _SOFF are provided,
When the level of the ramp signal RAMP is the low level threshold V
_When reaching _SON , a clamp pulse is generated, and when the level of the ramp signal RAMP reaches the high level threshold V _SOFF , generation of the clamp pulse is terminated. As a result, in the vertical synchronization signal (V-SYNC),
A clamp pulse can be generated at the chip position.

[0010]

By the way, the above-described conventional clamp pulse generating circuit can effectively generate a clamp pulse for an SD signal, but it is required to provide a high definition television signal (hereinafter, referred to as an HD signal). May not work properly. One of the reasons is that the width of the synchronization pulse of the HD signal is narrow, and the accuracy of the generated clamp pulse is poor. Another is that the signal reference level of the HD signal becomes the pedestal level, and the clamp pulse is placed at the pedestal position. That is what needs to happen.

For the above-mentioned reason, the circuit similar to the clamp pulse generating circuit for the SD signal causes the H level at the pedestal position.
When the clamp pulse of the D signal is generated, there is no problem in the normal horizontal synchronization signal (H-SYNC),
In the vertical synchronization signal (V-SYNC), there is a problem that a pulse is generated at a position other than the pedestal position.

As another method, there is a method of generating a diode clamp which can be used even for an HD signal. Clamps requiring accuracy such as insertion of a character include temperature characteristics and a shrinkage of a sync signal sync. There is a problem in using it as it is because it is affected by such factors.

The present invention has been made in view of the above circumstances, and has as its object to be applicable to two types of television signals, an SD signal and an HD signal, and to be able to generate a sync-chip synchronous clamp pulse in an SD signal. In addition, it is an object of the present invention to provide a clamp pulse generation method and a circuit thereof capable of accurately generating a clamp pulse at a pedestal position in an HD signal.

[0014]

In order to solve the above-mentioned object, according to the present invention, both a standard television composite video signal and a high-resolution television composite video signal are supported, and a clamp is performed based on any of the composite video signals. A method of generating a clamp pulse for generating a pulse, comprising: separating a synchronization signal from the input composite video signal; inverting the separated synchronization signal; and receiving the standard television composite video signal. Selecting the separated synchronization signal, when the high-resolution television composite video signal is being input, selecting the inverted inverted synchronization signal; and Generating a ramp signal in response to the inversion signal; and, when the standard television composite video signal is being input, a first start threshold value and a first start threshold value. A first set of thresholds consisting of an end threshold is set, and when the high-resolution television composite video signal is input, a second set of thresholds consisting of a second start threshold and a second end threshold is set. Setting a set of thresholds and generating a clamp pulse for the ramp signal based on the set thresholds.

Further, the present invention is a clamp pulse generating circuit which supports both a standard television composite video signal and a high-resolution television composite video signal and generates a clamp pulse based on any of the composite video signals. A synchronizing signal separating circuit for separating a synchronizing signal from the input composite video signal, an inverting circuit for inverting the synchronizing signal separated by the synchronizing signal separating circuit, and the standard television composite video signal. When the synchronizing signal separated by the separating circuit is selected, and when the high-resolution television composite video signal is input, a selecting circuit for selecting an inverted synchronizing signal inverted by the inverting circuit, A ramp signal is generated in response to a synchronizing signal or its inverted signal, and the first start is performed when the standard television composite video signal is input. A first set of threshold values comprising a threshold value and a first end threshold value. When the high-resolution television composite video signal is input, a second start threshold value and a second end threshold value are set. Set a second set of thresholds consisting of thresholds,
A pulse generation circuit for generating a clamp pulse based on the set threshold value for the ramp signal.

Further, in the present invention, the second start threshold value is set to be larger than a maximum value of the ramp signal generated during an equalization pulse period included in the high-resolution television composite video signal. I have.

[0017]

According to the clamp pulse generation method of the present invention, after the composite synchronizing signal is separated from the composite video signal, the level of the composite synchronizing signal is inverted. Then, based on the predetermined threshold, a clamp pulse is generated from the level-inverted composite synchronization signal.

Further, according to the clamp pulse generating circuit of the present invention, a composite synchronizing signal including a horizontal synchronizing signal and a vertical synchronizing signal is generated from the composite video signal by the synchronizing separation circuit, and is inverted by the inverting circuit. A synchronization signal is generated and input to a subsequent pulse generation circuit. In the pulse generation circuit, a clamp pulse is generated by the inverted composite synchronization signal based on a predetermined threshold. Thus, when receiving an HD signal, a clamp pulse can be generated at a predetermined position in both the horizontal synchronization signal and the vertical synchronization signal.

Further, according to the present invention, the composite synchronizing signal inverted by the inverting circuit or the signal output by the synchronizing separation circuit is selectively switched by the switch circuit according to the type of the received signal in the subsequent pulse generation. Connected to the circuit. As a result, a clamp pulse generation circuit that can handle two types of television signals, that is, an SD signal and an HD signal, can be realized.

[0020]

Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of a clamp pulse generating circuit to which a clamp pulse generating method according to the present invention is applied. In FIG. 1, 1 is an input terminal, 2 is a synchronization separation circuit, 3 is an output terminal of the synchronization separation circuit 2, 4 is a pulse generation circuit, 5 is an output terminal of the pulse generation circuit, 6 is an inversion circuit, 7 is SD and HD. Each shows a signal changeover switch. As shown in FIG. 1, the clamp pulse generating circuit of this embodiment is different from the conventional SD signal clamp pulse generating circuit shown in FIG.
Between the pulse generating circuit 4 and the inverting circuit 6 and SD,
The difference is that a changeover switch 7 that operates according to the HD signal is added.

Hereinafter, the configuration of the clamp pulse generating circuit of the present embodiment will be described with reference to FIG. As shown in FIG. 1, a composite television signal including a video signal, a synchronization signal, and the like is input to the input terminal 1. Sync separation circuit 2
Of the composite television signal, the composite sync signal CS including only the horizontal synchronization signal and the vertical synchronization signal.
YNC is extracted and the composite sync signal C
An S_SEP pulse is output to the output terminal 3 of the sync separation circuit 2 as an inverted SYNC signal.

The S_SEP pulse output to the output terminal 3 of the sync separation circuit 2 is divided into two, one is connected to the terminal N _HD of the changeover switch 7 through the inversion circuit 6, and the other is used as it is. It is connected to the 7 terminals N _SD of. S_SEP by the changeover switch 7
The inverted signal of the pulse or the S_SEP pulse is sent as it is to the next-stage pulse generation circuit 4 to generate a clamp pulse.

FIG. 2 is a waveform diagram showing the composite sync signal CSYNC of the HD signal. Hereinafter, the operation of the clamp pulse generating circuit when receiving an HD signal in the above circuit configuration will be described with reference to the waveform diagram of FIG.
As described above, the input terminal 1 receives a composite television signal including a video signal, a synchronization signal, and the like. The composite sync signal CSYNC of the HD signal including the horizontal synchronizing signal (H-SYNC) and the vertical synchronizing signal (V-SYNC) as shown in FIG. The composite sync signal CSYNC is taken out, and the level of the composite sync signal CSYNC is limited and inverted by an inverting circuit in the sync separation circuit 2 to generate an S_SEP pulse as shown in FIG. Output to terminal 3.

When receiving an HD signal, the switch N 7 connects the terminal N _HD to the input terminal of the next-stage pulse generation circuit 4. At this time, the S_SEP pulse shown in FIG. 2B is output to the output terminal 3 of the synchronization separation circuit 2 and input to the inversion circuit 6. By the inverting circuit 6, the inverted S_SEP pulse as shown in FIG. 2 (c) is generated and outputted to the terminal N _HD of the switch 7. At this time, the changeover switch 7 is connected to the terminal N _HD side, S_SEP pulse of the HD signal through the changeover switch 7 is input to the subsequent stage of the pulse generating circuit 4.

Here, the operation of the pulse generation circuit 4 at the time of receiving an HD signal will be specifically described with reference to FIG. FIG. 3 is an enlarged view of a vertical synchronization signal (V-SYNC) of the composite sync signal CSYNC of the HD signal in FIG.

As shown in FIG. 3A, the vertical synchronizing signal portion of the HD signal is composed of an equalizing pulse EPULSE and a vertical synchronizing signal (V-SYNC). In the pulse generation circuit 4, as shown in FIG. 3C, a low-level threshold V _HON and a high-level threshold V _HOFF
Are provided. The ramp signal RAMP is generated by the rising edge of the inverted S_SEP pulse. When the level of the ramp signal RAMP reaches the low level threshold value V _HON , a clamp pulse is generated. When the level of the ramp signal RAMP reaches the high level threshold value V _HOFF , the generation of the clamp pulse is terminated. You. Thus, a clamp pulse can be generated at the pedestal position in the vertical synchronization signal (V-SYNC).

As shown in FIG. 3C, the inverted S_SEP
When the ramp signal RAMP is generated at the rise of the pulse, the ramp signal RAP is generated even during the equalization pulse EPULSE.
MP is generated, and unless this is suppressed in an appropriate manner, a clamp pulse may be generated in an erroneous place. As shown in FIG. 3, suppose that the width of the equalization pulse EPULSE is a, the interval between the equalization pulse EPULSE and the vertical synchronization pulse is b, and the width of the vertical synchronization pulse is composed of two parts, c and d. , A: b: c: d = 1:
A 1: 1: 2 relationship holds. That is, the equalizing pulse E
It can be seen that the width of the vertical synchronization pulse is sufficiently wider than the width of PULSE. Utilizing the difference between the width of the equalizing pulse EPULSE and the width of the vertical synchronization pulse, the threshold level V
_By setting the values of _HON and V _HOFF appropriately
The occurrence of an erroneous clamp pulse can be suppressed by the ramp signal RAMP generated during the equalization pulse EPULSE.

For example, as shown in FIG.
If the level threshold value V _HON is set slightly higher than the upper limit level of the ramp signal RAMP during the equalization pulse EPULSE, the level of the ramp signal RAMP generated during the equalization pulse EPULSE becomes the low level threshold. V
_HON is not reached, and the generation of a clamp pulse by mistake is prevented. On the other hand, during the vertical synchronizing signal period, since the width of the vertical synchronizing signal is wider than the equalizing pulse width, the ramp signal RAMP generated by the rising can reach the low level threshold value V _HON , thereby the clamp pulse Is generated and when the high level threshold value V _HOFF is reached, the clamp pulse is terminated. Thus, a clamp pulse can be generated at a predetermined pedestal position in the vertical synchronization signal.

The horizontal synchronizing signal (H-SY) of the HD signal
It is needless to say that a clamp pulse can be generated at the pedestal position in the section (NC) in the same manner as described above.

The operation of the clamp pulse generation circuit shown in FIG. 1 when receiving an HD signal has been described above. S
When receiving the D signal, the sync separation circuit 2
The composite sync signal CSYNC of the D signal is separated, an S_SEP pulse is generated, and output to the output terminal 3 of the sync separation circuit 2. Then, the terminal N _SD is connected to the input terminal of the pulse generation circuit 4 of the next stage by the changeover switch 7,
The signal S_SEP pulse is input to the pulse generation circuit 4. As already described in the description of the prior art, in the pulse generation circuit 4, a clamp pulse is generated in the sync chip by the composite sync signal CSYNC of the SD signal, and is output to the output terminal 5.

Since both the SD signal and the HD signal can be _handled , the level of the low-level thresholds V _SON and V _HON and the level of the high-level thresholds V _SOFF and V _HOFF are _{changed when} the switch 7 is switched. Need to be switched. Also, the ramp signal RA of the SD signal and the HD signal
Since the slope of MP is different, it is necessary in the ramp signal generation circuit to switch the ramp signal generation current with the switching of the signal. These detailed control circuits are constituted by well-known circuits, and descriptions thereof are omitted.

As described above, such a clamp pulse generation circuit can generate a clamp pulse at a predetermined sync tip position when receiving an SD signal, and a predetermined pulse when receiving an HD signal. Can generate a clamp pulse at the pedestal position. Thus, by adding the inverting circuit 6 and the changeover switch 7, a clamp pulse can be generated at a correct position for both the SD signal and the HD signal.

As described above, according to the clamp pulse generation circuit of the present embodiment, the input terminal 1 is connected to the synchronization separation circuit 2.
Connected to the output terminal 3 of the synchronization separation circuit 2
The _SEP pulse is selectively input to the pulse generating circuit 4 through the inverting circuit 6 by the changeover switch 7 or directly to the pulse generating circuit 4 without passing through the inverting circuit 6 to generate a Kump pulse. As a result, one clamp pulse generating circuit 4 can handle both the SD signal and the HD signal, and can generate a clamp pulse at a predetermined position.

Further, by adjusting the gradient of the ramp signal RAMP generated by the ramp signal generation circuit by the ramp signal generation current, there is an advantage that both the 1125/60 and 1250/50 HD signal systems can be handled.

The first embodiment of the clamp pulse generating circuit according to the present invention has been described above. In the above description, the pulse generation circuit 4 generates the ramp signal RAMP at the rising edge of the S_SEP pulse or the inverted S_SEP pulse,
, A clamp pulse is generated. However, it is not always necessary to generate the ramp signal RAMP at the rising edge of the pulse.
Can also be generated. Hereinafter, a second embodiment according to the present invention based on this concept will be described.

[0036]

Embodiment 2 FIG. 4 is a block diagram showing a second embodiment according to the present invention. As shown in FIG. 4, the second embodiment is different from the first embodiment shown in FIG. 1 in that the changeover switch 7a generates the S signal generated by the synchronization separation circuit 2.
When the _SEP pulse receives the SD signal, it is input to the subsequent pulse generation circuit 4a through the inverting circuit 6, and when the HD is received,
That is, it is directly input to the pulse generation circuit 4a. The pulse generator 4a is different from the pulse generator 4 shown in FIG.

In FIG. 4, the S_SEP pulse generated by the sync separation circuit 2 is the same as that of the first embodiment shown in FIG. 1, so that the block diagram of FIG.
With reference to the waveform diagram of FIG. 6, only differences between the second embodiment and the first embodiment will be described.

FIG. 5 is a waveform diagram showing enlarged waveforms of the composite sync signal CSYNC, S_SEP pulse and clamp pulse when an SD signal is received, and FIG. 6 when an HD signal is received in the second embodiment. . In addition,
5 and 6, the composite sync signal CSY
Only during the period of the NC vertical synchronization signal (V-SYNC) is displayed.

As shown in the block diagram of FIG. 4, when the SD signal is received, the S switch of the SD signal is operated by the changeover switch 7a.
The _SEP pulse is input to the pulse generation circuit 4a through the inversion circuit 6. The waveforms of the composite sync signals CSYNC, S_SEP pulse and the output signal of the inversion circuit 6 at this time are shown in FIGS. 5A, 5B and 5C, respectively.
Shown in

That is, the S_SEP pulse generated by the sync separation circuit 2 is inverted by the inversion circuit 6 in FIG.
An inverted S_SEP pulse as shown in (c) is input to the pulse generation circuit 4a.

In the pulse generation circuit 4a, the ramp signal RAMP is output at the falling edge of the inverted S_SEP pulse.
Is generated, and based on the ramp signal RAMP, a low level threshold V _SON and a high level threshold V _SOFF are set in advance, as in the first embodiment.
The clamp pulse shown in FIG. 5D is generated and output to the output terminal 5 of the pulse generation circuit 4a.

Next, at the time of receiving the HD signal, the changeover switch 7a operates the H signal generated by the sync separation circuit 2.
The S_SEP pulse of the D signal is directly input to the pulse generation circuit 4a without passing through the inversion circuit 6. The waveforms of the composite sync signal CSYNC, S_SEP pulse and the output signal of the pulse generation circuit 4a at this time are shown in FIGS. 6A, 6B and 6C, respectively.

That is, the S_SEP pulse generated by the synchronization separation circuit 2 is directly input to the pulse generation circuit 4a. In the pulse generation circuit 4a, S_SEP
A ramp signal RAMP is generated at the falling edge of the pulse,
Based on the ramp signal RAMP, similarly to the first embodiment, a clamp pulse shown in FIG. _5D is _generated by a _preset low-level threshold value V _HON and high-level threshold value V _HOFF . Are output to the output terminal 5 of the pulse generation circuit 4a.

Note that, in the second embodiment as well,
As in the first embodiment, both the SD signal and the HD signal are used.
Switch 7a
The low level threshold V_SONAnd V_HON, Ha
Level threshold V_SOFFAnd V _HOFFSwitch the level of
It is necessary. Also, SD signal and HD signal ramps
Since the slope of the signal RAMP is different, the ramp signal generation circuit
, The lamp signal generation current
Need to be switched. Control times of these details
Description of the road is omitted.

As described above, when the SD signal is received by the clamp pulse generation circuit configured as described above,
A clamp pulse can be generated at a predetermined sync chip, and when an HD signal is received, a clamp pulse can be generated at a predetermined pedestal position. Thus, by adding the inverting circuit 6 and the changeover switch 7, a clamp pulse can be generated at a correct position for both the SD signal and the HD signal.

As described above, according to the clamp pulse generating circuit of this embodiment, the input terminal 1 is connected to the synchronous separation circuit 2.
Connected to the output terminal 3 of the synchronization separation circuit 2
The _SEP pulse is selectively supplied to the pulse generating circuit 4a through the inverting circuit 6 by the changeover switch 7a or to the pulse generating circuit 4a without passing through the inverting circuit 6.
a to generate a pump pulse. As a result, one clamp pulse generating circuit 4 can handle both the SD signal and the HD signal, and can generate a clamp pulse at a predetermined position.

[0047]

As described above, according to the present invention,
The present invention can be applied to two types of television signals, that is, an SD signal and an HD signal. In the SD signal, it is possible to generate a sync-chip synchronous clamp pulse.
A clamp pulse can be generated accurately at the pedestal position.
Further, there is an advantage that a so-called equalizing pulse can be canceled in the vertical synchronizing signal section of the HD signal.

Further, according to the present invention, there is an advantage that a clamp pulse of an HD signal can be generated in an analog signal processing system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a clamp pulse generation circuit according to the present invention.

FIG. 2 is a composite sync signal CSYNC of an HD signal.
FIG.

FIG. 3 is a composite sync signal CSYNC of an HD signal.
FIG.

FIG. 4 is a block diagram showing a clamp pulse generating circuit according to a second embodiment of the present invention.

FIG. 5 is a composite sync signal CSYNC of an SD signal.
FIG.

FIG. 6 is a composite sync signal CSYNC of an HD signal.
FIG.

FIG. 7 is a block diagram showing a conventional clamp pulse generation circuit.

FIG. 8 shows a composite sync signal CSYNC of an SD signal.
FIG.

FIG. 9 shows a composite sync signal CSYNC of an SD signal.
FIG.

[Explanation of symbols]

H-SYNC horizontal synchronization signal V-SYNC vertical synchronization signal 1 input terminal 2 synchronization separation circuit 3 synchronization separation circuit output terminal 4, 4a pulse generation circuit 5 output terminal 6 inversion circuit 7, 7a SD , HD signal changeover switches N _SD , N _HD ... terminals of changeover switches 7, 7a

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/14-5/217

Claims (3)

(57) [Claims] 1. A method of generating a clamp pulse corresponding to both a standard television composite video signal and a high-resolution television composite video signal and generating a clamp pulse based on any one of the composite video signals. Separating a synchronization signal from the composite video signal, inverting the separated synchronization signal, and when the standard television composite video signal is input,
Selecting the separated synchronization signal and, when the high-resolution television composite video signal is being input, selecting the inverted inverted synchronization signal; and according to the selected synchronization signal or its inverted signal. Generating a ramp signal; and when the standard television composite video signal is being input,
A first threshold comprising a first start threshold and a first end threshold;
A second set of thresholds comprising a second start threshold and a second end threshold when the high-resolution television composite video signal is input; Generating a clamp pulse based on the set threshold value for the ramp signal. 2. A clamp pulse generating circuit for generating a clamp pulse based on any one of the composite video signals, corresponding to both a standard television composite video signal and a high-resolution television composite video signal. A synchronizing signal separating circuit for separating a synchronizing signal from the composite video signal, an inverting circuit for inverting the synchronizing signal separated by the synchronizing signal separating circuit, and when the standard television composite video signal is input,
When the synchronization signal separated by the separation circuit is selected and the high-resolution television composite video signal is input,
A selecting circuit for selecting an inverted synchronizing signal inverted by the inverting circuit, and generating a ramp signal in accordance with the selected synchronizing signal or the inverted signal thereof, and when the standard television composite video signal is input, A first set of thresholds consisting of a first start threshold and a first end threshold is set, and when the high-resolution television composite video signal is input, a second start threshold and a second start threshold are set. A pulse generation circuit that sets a second set of thresholds including a second end threshold and generates a clamp pulse based on the set threshold with respect to the ramp signal. circuit. 3. The second start threshold value is set to be larger than a maximum value of the ramp signal generated within an equalization pulse period included in the high-resolution television composite video signal. A clamp pulse generation circuit as described.