JPS6212713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise removal circuit that uses digital technology to remove noise components due to ghost signals, thereby stabilizing synchronization in a television receiver.

Conventionally, in television receivers, in order to perform horizontal and vertical synchronization, the amplitude is separated from the television signal to extract the synchronization pulse, and the synchronization pulse is used for horizontal synchronization to control the AFC (automatic frequency control) circuit. Adjust the horizontal oscillation frequency by
They were in phase. Also, for vertical synchronization, the synchronization pulse is passed through an integrating (low-pass filter) circuit to perform frequency separation, detect the vertical synchronization pulse, and reset the vertical oscillation circuit with this output pulse to match the phase of the oscillation frequency. . However, if the television signal is disturbed by, for example, a ghost signal, the synchronization becomes unstable.

Here, with reference to FIGS. 1 and 2, we will further consider the instability of synchronization. FIG. 1 is a waveform diagram of a television signal when a ghost signal having an opposite phase to a normal signal is input. Further, FIG. 2 shows a synchronization pulse which is an output signal when the separation level is appropriately set by the synchronization separation circuit.

Of these figures 1 and 2, a in figure 1
is an equivalent pulse b is a vertical synchronization pulse c is a horizontal synchronization pulse, d is a video signal, and H indicates horizontal scanning. Further, N in FIG. 2 indicates a noise component due to a ghost.

What can be seen from FIGS. 1 and 2 is that relatively good phase information is obtained in the equivalent pulse a and vertical synchronizing pulse b, but noise components are generated due to the influence of the picture pattern during the horizontal scanning period. The occurrence of this noise component makes synchronization unstable, as described above.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional art, and provides a noise removal circuit that can stabilize synchronization by removing noise components in the horizontal scanning period due to ghost signals. With the goal.

Embodiments of the noise removal circuit of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of one embodiment. In FIG. 3, 1 is a 64fH clock generation circuit (fH is the horizontal scanning frequency). The clock signal generated from this 64fH clock generation circuit 1 is synchronized with the horizontal scanning frequency and sent to the 32-decimal counter 2, the vertical sync pulse detection circuit 3, the horizontal sync pulse detection circuit 4, and the 1/64 frequency divider 5. It's getting old.

Further, 6 is a synchronous separation circuit. When the television signal 7 is introduced into the synchronization separation circuit 6, a synchronization pulse signal 8 is sent to the vertical synchronization pulse detection circuit 3 and the horizontal synchronization pulse detection circuit 4. The vertical synchronization pulse detection circuit 3 detects the pulse width of the synchronization pulse signal 8 using this synchronization pulse signal 8 and the clock signal from the 64fH clock generation circuit 1, and determines whether or not the synchronization pulse signal 8 is a vertical synchronization pulse signal. This is to detect. Similarly, the horizontal synchronization pulse detection circuit 4 detects the pulse width of the synchronization pulse signal 8 using the synchronization pulse signal 8 and the clock signal, and detects whether or not the synchronization pulse signal 8 is a horizontal synchronization pulse signal. It is something.

The vertical synchronization pulse signal detected by the vertical synchronization pulse detection circuit 3 is sent to the 32-decimal counter 2 as a reset signal. This 32-digit counter 2 counts the clock signal from the 64fH clock generating circuit 1 which is synchronized with the horizontal scanning frequency, and also generates a gate signal for gating the horizontal synchronizing pulse signal from this clock signal.
This gate signal is sent to the first input terminals of the 1/2 frequency divider circuit 9 and the AND circuit 10.

On the other hand, the horizontal synchronizing pulse signal detected by the horizontal synchronizing pulse detection circuit 4 is applied to the first input terminal of the AND circuit 11. The output of the 1/2 frequency divider circuit 9 is applied to the second input terminal of the AND circuit 11. The output of this 1/2 frequency divider circuit 9 is also sent to a second input terminal of an AND circuit 10. The output of the AND circuit 11 is sent to the 1/2 frequency divider circuit 9 as a reset signal.

The synchronizing pulse signal 8 is also applied to the third input terminal of the AND circuit 10, and the output of the AND circuit 10 is output to the phase detection circuit 12. The output of this AND circuit 10 serves as a noise-reducing horizontal synchronizing pulse.
The output of the 1/64 frequency dividing circuit 5 is also introduced into the phase detection circuit 12. The phase detection circuit 12
The output of the 1/64 frequency divider 5 and the output of the AND circuit 10 are compared in phase and output to the 64fH clock generation circuit.

Next, the operation of the noise removal circuit of the present invention configured as described above will be explained. First, when the television signal 7 is introduced into the synchronization separation circuit 6,
There, an amplitude-separated synchronization pulse signal 8 is obtained. This synchronizing pulse signal 8 is sent to the vertical synchronizing pulse detecting circuit 3 and the horizontal synchronizing pulse detecting circuit 4, and is also applied to the third input terminal of the AND circuit 10. Further, the clock signal from the 64fH clock generating circuit 1 is simultaneously sent to the 32-decimal counter 2, the vertical synchronizing pulse detecting circuit 3, the horizontal synchronizing pulse detecting circuit 4, and the 1/64 frequency dividing circuit 5.

Thereby, in the vertical synchronization pulse detection circuit 3, based on the synchronization pulse signal 8 and the clock signal from the 64fH clock generation circuit 1, it is determined whether the pulse width of the synchronization pulse signal 8 is a vertical synchronization pulse signal or not. In Figures 1 and 2, the vertical synchronization pulse has solid phase information when viewed in the waveform after synchronization separation, so the vertical synchronization pulse signal is used as the reset signal for the 32-decimal counter 2. are doing. Now, vertical synchronization pulse detection circuit 3
When it is determined that it is a vertical synchronization signal, this vertical synchronization pulse signal is sent to the vertical synchronization pulse detection circuit 3.
It is sent to the 32-decimal counter 2 as a reset signal.

The 32-decimal counter 2 counts the clock signal from the 64fH clock generation circuit 1, and generates a gate signal for gating the synchronization pulse signal 8. It is reset by the vertical synchronization pulse signal from the vertical synchronization pulse detection circuit 3. Based on the phase of the signal and the rising phase of the synchronous pulse signal 8, the 32-digit counter 2
Create a gate pulse with a predetermined phase. This gate pulse is applied to the first input terminal of the AND circuit 10 and is also sent to the 1/2 frequency divider circuit 9. this
Since the gate pulse obtained by the 32-decimal counter 2 is 2fH, only the horizontal synchronizing pulse signal will not be gated from the AND circuit 10. Therefore, in order to gate only this horizontal sync pulse signal, the 32-decimal counter The gate pulse obtained from 2 is frequency-divided by 1/2 by a 1/2 frequency divider circuit 9. The output of this 1/2 frequency divider circuit 9 is simultaneously sent to each second input terminal of AND circuits 10 and 11.

On the other hand, in the horizontal synchronization pulse detection circuit 4,
64fH in the same way as vertical synchronization pulse detection circuit 3
Based on the clock from the clock generation circuit 1 and the synchronization pulse signal 8, it is determined whether the pulse width of the synchronization pulse signal 8 is a horizontal synchronization pulse signal, and when it is detected that it is a horizontal synchronization pulse signal, this horizontal The synchronization pulse signal is sent to the horizontal synchronization pulse detection circuit 4.
is applied to the first input terminal of the AND circuit 11. AND circuit 11 uses this horizontal synchronizing pulse signal
It is ANDed with the output of the 1/2 frequency divider circuit 9 and output. In other words, a horizontal synchronizing pulse signal is output. This horizontal synchronizing pulse signal resets the 1/2 frequency divider circuit 9.

By doing this, in the AND circuit 10, the gate pulse obtained by the 32-decimal counter 2 is added to the first input terminal, the output of the 1/2 frequency divider circuit 9 is added to the second input terminal, Furthermore, the synchronization pulse signal 8
is added to the third input terminal, the AND circuit 10 takes the AND of these and generates the synchronization pulse signal 8.
Therefore, only the vicinity of the horizontal synchronizing pulse signal can be obtained. This signal has completely removed the noise caused by ghosts. That is, the signal taken out from the AND circuit 10 becomes a horizontal synchronizing pulse signal with reduced noise.

This horizontal synchronizing pulse signal with reduced noise is sent to the phase detection circuit 12. The output of the 1/64 frequency divider circuit 5 is also introduced into the phase detection circuit 12. 1/
The 64 frequency divider circuit 5 divides the frequency of the clock signal from the 64fH clock generating circuit 1 to 1/64 and sends it to the phase detection circuit 12. Therefore, the phase detection circuit 12 compares the phase of the horizontal synchronization pulse signal output from the AND circuit 10 using the horizontal synchronization pulse signal divided by 1/64 as a reference, and compares the phase of the horizontal synchronization pulse signal outputted from the AND circuit 10. The frequency of the clock signal generated from the 64fH clock generation circuit 1 is adjusted according to the phase deviation between the output of the 64fH clock generation circuit 1 and the output of the AND circuit 10.

Furthermore, if the noise-reduced horizontal synchronizing pulse signal outputted from the AND circuit 10 is used for synchronizing the television receiver, the noise is reduced, so that the synchronization performance is improved. Furthermore, instead of this, the output signal of the 1/64 frequency divider circuit 5 is also a horizontal synchronization pulse signal from which noise components have been removed, so if horizontal synchronization of the television receiver is performed using this signal, very good You can expect good synchronization performance.

FIG. 4 is a block diagram showing a specific configuration of the noise removal circuit of the present invention shown in FIG. 3. In FIG. 4, parts corresponding to those in FIG. 3 are given the same reference numerals, and their explanations will be omitted. Note that 3.4 in FIG. 4 shows the vertical synchronizing pulse detection circuit 3 and the horizontal synchronizing pulse detection circuit 4 integrally. The 32-decimal counter 2 is composed of flip-flop circuits (hereinafter abbreviated as FF) 2 ₁ to 2 ₅ and an AND circuit 2 ₆ , and the 1/2 frequency divider circuit 9 is an inverter ₉₁ and 1/2 frequency divider circuit. It consists of 9. The vertical synchronization pulse detection circuit 3 and the horizontal synchronization pulse detection circuit 4 are constituted by FFs 34 ₁ to 34 ₅ , AND circuits 34 ₆ to 34 ₈ , and NOR circuits 34 ₉ to 34 ₁₁ . The configuration of other parts is the same as that in FIG. 3.

Next, the above configuration will be explained with reference to the waveform diagram shown in FIG.

During the vertical sync period, the vertical sync pulse
Clearing of FFs ₃₄₁ to ₃₄₅ is released, and the clock signal of 64fH is counted. A pulse is output from the AND circuit ₃₄₇ at the 19th clock. At this time, since the vertical synchronization pulse is "H", this pulse passes through the AND circuit ₂₇ and clears the FFs ₂₁ to ₂₅ , but is gated by the AND circuit 11 to 1/
The divide-by-2 circuit 9 is not cleared. In other words, the above FF2
₁ to ₂₅ are synchronized by a vertical synchronizing pulse, and an AND circuit ₂₆ outputs a gate pulse having a width of 8 clocks with a _2fH cycle.

The above operation is repeated at 2f _H cycles within the vertical synchronization period.

Even during the horizontal sync period, the horizontal sync pulse
_FF341 to _FF345 start counting. Set pulse S is output from the AND circuit ₃₄₈ at the second clock.
is output, and the output of the NOR circuit ₃₄₉ is set to "H". This is to prevent the FFs 34 ₁ to 34 ₅ from being cleared by horizontal synchronizing pulses with narrow pulse widths, and to remove pulse widths of 2 clocks or less as noise. On the 19th clock,
Similar to the vertical synchronization period, a pulse is output from the AND circuit ₃₄₇ , but this time it is gated by the AND circuit ₂₇ , so the FFs ₂₁ to ₂₅ are not cleared, but the 1/2 frequency divider circuit 9 is cleared. However, the frequency divider circuit 9 is cleared when the phase of the frequency division output is in the opposite phase, that is, when it is "H" at the 19th clock, and when it is in positive phase, it is gated by the AND circuit 11 and is not cleared. .

As described above, during the horizontal synchronization period, the AND circuit 10 gates the output of the synchronization separation circuit ₆ using the gate pulse of 2f _H period and 8 clock width output from the AND circuit 26 and the divided output of _fH . It is possible to obtain a horizontal synchronization pulse whose noise is removed and whose phase is synchronized with the vertical synchronization pulse.

Although the 64fH clock generation circuit 1 is shown as a 64fH clock generation circuit in FIGS. 3 and 4, it may be any nfH clock generation circuit, and is not limited to 64fH. Similarly, the 1/64 frequency dividing circuit 5 may be a 1/n frequency dividing circuit.

As described above, according to the noise removal circuit of the present invention, the vertical synchronization pulse signal and the horizontal synchronization pulse signal are detected using the clock signal and the synchronization pulse signal corresponding to the horizontal scanning frequency, and the phase of the vertical synchronization signal and the synchronization pulse signal are detected. A gate pulse is created from the rising phase of the horizontal synchronizing pulse signal synchronized with the horizontal scanning signal, the frequency of this gate pulse is divided by 1/2, and the gate pulse with the frequency divided by 1/2 is ANDed with the above horizontal synchronizing pulse signal. The output resets the 1/2 divider circuit and the above
Since the horizontal sync pulse is obtained by ANDing the gate pulse that is not frequency-divided by 1/2 and the gate pulse and sync pulse signal that are frequency-divided by the 1/2 frequency divider, the horizontal scanning period due to ghosts etc. This has the effect of being able to remove noise components.

Furthermore, since the PLL is configured and the clock signal is tuned to a frequency n times the horizontal scanning frequency, a more accurate phase can be obtained.

[Brief explanation of the drawing]

Figure 1 is a synchronization separation waveform diagram of a television signal when a ghost signal of opposite phase is input, and Figure 2 is a diagram showing a synchronization pulse signal when the separation level is appropriately set by the synchronization separation circuit. , FIG. 3 is a block diagram showing the configuration of an embodiment of the noise removal circuit of the present invention, and FIG. 4 is a block diagram showing the structure of a specific embodiment of the noise removal circuit of the invention based on FIG. FIG. 5 is a waveform diagram illustrating the operation of the embodiment shown in FIG. 4. 1... 64fH clock generation circuit, 2... 32-decimal counter, 3... Vertical synchronization pulse detection circuit, 4...
Horizontal synchronous pulse detection circuit, 5...1/64 frequency division circuit,
6...Synchronization separation circuit, 9...1/2 frequency divider circuit, 1
0, 11...AND circuit.

Claims (1)

[Scope of Claims] 1. A synchronization separation circuit that separates a synchronization pulse signal from a television signal, a clock generation circuit that generates a clock signal synchronized with n times the horizontal scanning frequency, and a clock signal and a synchronization pulse signal that are synchronized with each other. synchronization pulse detection means for detecting a vertical synchronization pulse signal and a horizontal synchronization pulse signal from the pulse width of the synchronization pulse signal, and a vertical synchronization pulse signal supplied with the clock signal and detected by the synchronization pulse detection means; an n/binary counter that is reset based on the clock signal and generates a gate pulse at a predetermined phase from the rising phase of the clock signal; and a 1/2 counter that divides the frequency of the gate pulse into 1/2. a first circuit for resetting the 1/2 frequency dividing circuit by ANDing the horizontal synchronous pulse signal detected by the synchronous pulse detection means and the output of the 1/2 frequency dividing circuit;
and a second AND circuit that ANDs the output of the 1/2 frequency divider circuit, the gate pulse, and the output of the synchronization separation circuit to extract a horizontal synchronization pulse signal from which noise has been removed. A noise removal circuit characterized by comprising: 2. The clock generation circuit includes a second frequency dividing circuit that divides the clock signal into a frequency of 1/n;
Using the output of the second frequency dividing circuit as a reference signal, the phase is compared with the horizontal synchronizing pulse signal output from the second AND circuit, and the frequency of the clock signal is adjusted n times the horizontal scanning frequency according to the deviation. 2. The noise removal circuit according to claim 1, further comprising a phase detection circuit adapted to a frequency of .