JPH09154037A - Digital pll and synchronizing separator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a phase locked loop (PLL) in a digital circuit. SOLUTION: A synchronizing signal extracted from a video signal is gated by an AND gate 3 through a separator circuit 1, and the gated synchronizing signal is supplied to a phase comparator circuit 4. This compared output is inputted through a loop filter 5 to an oscillation circuit 6 composed of a counter and this oscillated output is inputted to the phase comparator circuit 4, so that the PLL can be formed. Further a mask signal generating circuit 10 generates that mask signal from the output of this oscillation circuit 6 and a counter 13 counts how many times the synchronizing signals are continuously absent during the period of this mask signal. When this number of times exceeds a prescribed value, the synchronizing signal from the video signal is extracted and corresponding to this signal, the counter consisting of the oscillation circuit is reset. Thus, the stable and speedy PLL and synchronizing separator circuit are constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a home V
Digital P suitable for use in TRs and television receivers
The present invention relates to an LL and a sync separation circuit.

[0002]

2. Description of the Related Art For example, in a sync separation circuit used for a home VTR or a television receiver, a circuit using a so-called analog PLL has been implemented. That is, in FIG. 7, for example, the input synchronizing signal separated from the video signal is supplied to the phase comparison circuit (φ) 71, and the output of this phase comparison circuit 71 is the loop filter 72.
Is supplied to the variable frequency oscillation circuit (VCO) 73 via.

The output of the oscillating circuit 73 is supplied to the synchronizing pulse generating circuit 74 to extract the synchronizing pulse, and the output synchronizing pulse is supplied to the phase comparing circuit 71 to form a phase locked loop. by this,
Even if the sync signal is missing, a good output sync pulse can be obtained by interpolating the sync signal by the effect of the PLL.

However, in a circuit using such an analog PLL, there is a problem that the circuit does not follow the fluctuations slowly. Therefore, for example, as shown in FIG.
In TR, when the phase of the sync signal fluctuates by about 1/2 horizontal period due to head switching or the like, this fluctuation is not immediately corrected and is finally corrected in the image signal period in synchronization with the equivalent pulse in the vertical sync period. Will start. Therefore, there is a possibility that image distortion (skew) that occurs until the fluctuation is corrected may occur in the display screen.

In analog circuits, for example, C-MO
It is difficult to form an IC using an S element, for example, a C-MO
Many external parts are required when the IC is formed by using the S element. For this reason, many work steps are required for assembling and adjusting the circuit, and external parts used also require high-precision parts due to tolerance and temperature coefficient. Met.

[0006]

This application has been made in view of such a point, and the problem to be solved is that the circuit following the conventional analog PLL is slow to follow. Moreover, it is difficult to make an IC using a C-MOS element, and many external parts are required.
There were various problems.

[0007]

Therefore, in the present invention, the output of the phase comparison circuit is input to the oscillation circuit composed of the counter through the loop filter, and the output of the oscillation circuit is input to the phase comparison circuit. To form a phase-locked loop, whereby a PLL can be formed by a digital circuit, the circuit can be tracked quickly, and an IC using a C-MOS element can be easily obtained. You can

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION That is, according to the present invention, a gate circuit that gates a synchronization signal extracted from a video signal with a mask signal, a phase comparison circuit to which the gated synchronization signal is input, and an output of the phase comparison circuit. Is input to the oscillation circuit composed of a counter through the loop filter, and the output of this oscillation circuit is input to the phase comparison circuit, and the mask signal generation that generates the mask signal from the output of the oscillation circuit A circuit, a counting means for counting the number of consecutive absences of the synchronization signal during the mask signal period from the gate circuit, and an oscillation circuit with the synchronization signal extracted from the video signal when the number exceeds a predetermined value. And a reset means for resetting the constituent counter.

Referring to the drawings, FIG. 1 is a block diagram showing a configuration of an example of a receiver to which a digital PLL and a sync separation circuit according to the present invention are applied.

In FIG. 1, a television broadcast wave from, for example, an antenna (not shown) is supplied to a tuner 100 through a terminal 101 to receive a desired broadcast signal. The video signal in the received broadcast signal is supplied to the sync separation circuit 1. The separated horizontal synchronizing signal is supplied to the edge detecting circuit 2 and the falling edge of the horizontal synchronizing signal is detected.

The falling edge detection signal is supplied to the AND gate 3 together with a mask signal which will be described later. Then, the detection signal of the falling edge of the horizontal synchronizing signal gated by the mask signal is supplied to the phase comparison circuit (φ) 4. Further, the output of the phase comparison circuit 4 is supplied to the reset terminal of the counter which constitutes the oscillation circuit 6 through the loop filter 5.

Here, the oscillation circuit 6 is composed of a counter for counting 910, for example. Then, a clock signal of, for example, 14.318 MHz is supplied to the counter (oscillation circuit 6) from the terminal 7, and the clock signal of 1/91 is supplied.
By dividing by 0, for example, 15.734 kHz
The output signal of the horizontal synchronizing frequency is obtained. The 14.318 MHz clock signal is generally used as a clock for a circuit that digitally processes a video signal.

Further, this output signal is supplied to the pulse generating circuit 8 to form an output horizontal synchronizing pulse, and this output horizontal synchronizing pulse is taken out to the output terminal 9. At the same time, this output horizontal synchronizing pulse is supplied to the phase comparison circuit 4 to form a phase locked loop (PLL). That is, in this circuit, a variable frequency oscillator is configured by changing the frequency division ratio of the counter (oscillation circuit 6). Therefore, a PLL is formed by controlling the frequency division ratio with the output of the phase comparison circuit 4 described above.

Further, the signal from the above-mentioned oscillation circuit 6 is supplied to the mask signal generation circuit 10 to generate a mask signal corresponding to the predicted position of the next horizontal synchronizing signal. That is, in FIG. 2, for example, when a video signal as shown in A of FIG. 2 is input, a sync signal as shown in B of FIG. 2 is taken out from the sync separation circuit 1. Here, in this synchronizing signal, for example, an extra pulse a due to noise in the input video signal and a pulse loss b due to a decrease in signal level occur.

On the other hand, the mask signal generating circuit 10 generates a mask signal predicted from the immediately preceding horizontal synchronizing pulse, for example, as shown in C of FIG. As a result, the synchronizing signal from which the extra pulse a is removed is taken out from the AND gate 3, for example, as shown in D of FIG. Further, when the PLL is formed by this signal, the pulse generation circuit 8 outputs, for example, FIG.
The output horizontal sync pulse obtained by interpolating the missing pulse b is taken out as shown in E of FIG.

Therefore, by the action of the mask signal and the PLL, it is possible to separate the sync signal without being affected by the extra pulse or the lack of the pulse.

Further, the mask signal from the generation circuit 10 is inverted and supplied to the AND gate 11, and the falling edge detection signal from the detection circuit 2 is supplied to the AND gate 11. And gate 11
The signal is taken out from when there is no detection signal of the edge of the horizontal synchronizing signal in the mask signal period.

The mask signal from the generating circuit 10 is supplied to the AND gate 12, and the falling edge detection signal from the detecting circuit 2 is supplied to the AND gate 12. As a result, a signal is extracted from the AND gate 12 when the edge detection signal of the horizontal synchronizing signal is present during the mask signal period.

The signal from the AND gate 11 is supplied to the counting terminal of the counter 13, and the AND gate 1
The signal from 2 is supplied to the reset terminal of the counter 13. As a result, the counter 13 counts the number of consecutive falling edges of the horizontal synchronizing signal when no consecutive falling edges are detected during the mask signal period.

Further, when the number of times exceeds a predetermined value, the output signal of the counter 13 is supplied to the AND gate 14. Further, the falling edge detection signal from the detection circuit 2 is supplied to the AND gate 14. As a result, when the falling edge of the horizontal synchronizing signal is not detected continuously for a predetermined number of times during the mask signal period, the detection signal of the next falling edge is taken out from the AND gate 14.

By supplying the signal from the AND gate 14 to the reset terminal of the oscillation circuit 6,
For example, as shown in FIG. 3, even when the phase of the sync signal changes in about 1/2 horizontal period due to head switching in a home VTR, this change is immediately corrected,
Stable synchronization separation can be performed.

That is, in FIG. 3, for example, when a video signal as shown in FIG. 3A is input, the AND gate 3 extracts a synchronization signal as shown in FIG. 3B, which is gated by the mask signal. Be done. Here, for example, after the head is switched, this synchronization signal cannot be taken out.

On the other hand, the AND gate 11 extracts a signal in a period in which the AND gate 3 does not extract a synchronization signal as shown in FIG. 3C, for example. The signal from the AND gate 11 is transmitted a predetermined number of times (for example, 3
For example, a signal as shown in D of FIG.

By supplying the signal from the counter 13 to the AND gate 14, the AND gate 1
For example, a detection signal of the next falling edge of the synchronizing signal is extracted from 4 as shown in E of FIG. The signal from the AND gate 14 is supplied to the reset terminal of the oscillation circuit 6.

As a result, the oscillation circuit 6 is reset,
An output horizontal synchronizing pulse as shown in F of FIG. 3 is taken out from the pulse generating circuit 8. Further, since the mask signal is generated by the output of the oscillation circuit 6, the synchronizing signal at the correct position is continuously taken out from the AND gate 3, as shown in FIG. 3B, for example.

Therefore, by the operation of the counter 13,
The fluctuation of the phase of the synchronization signal is immediately corrected, and the occurrence of image distortion (skew) on the display screen is prevented.

Further, the signal separated by the sync separation circuit 1 is supplied to the pulse width detection circuit 15. In the detection circuit 15, for example, as shown in A of FIG. 4, a phase comparison stop signal having a low potential is formed in a predetermined period after the lapse of a predetermined time T1 from the falling edge of the input synchronizing signal. It is supplied to the gate 3.

Then, as shown in FIG. 4B, for the noise generated after the synchronization signal, the AND gate 3 eliminates the noise after the elapse of the predetermined time T1 by the action of the phase comparison stop signal. . This eliminates the possibility that the phase comparator circuit 4 may malfunction due to the influence of this noise.

Further, as shown in FIG. 4C, when a thin pulse noise is generated immediately before the sync signal, the phase comparison circuit 4 performs the comparison at the final falling edge, so that the correct sync signal is obtained. Phase comparison is performed at. If the synchronization signal becomes thinner, phase comparison is performed on this pulse.

Therefore, by the operation of the pulse width detection circuit 15, a reliable phase comparison can be always performed even in a noisy environment such as a weak electric field signal.

Further, in this circuit, for example, the circuit can be formed on the same LSI 200 as the signal processing circuit 16. That is, in FIG. 1, the video signal from the tuner 100 is supplied to the signal processing circuit 16, and the output horizontal synchronizing pulse from the pulse generating circuit 8 is supplied to the signal processing circuit 16. Then, the processed video signal is taken out to the output terminal 17.

In this way, the circuit described above can be formed on the same LSI as the signal processing circuit, for example. As a result, the overall circuit scale can be reduced and the cost of the entire device can be reduced. The horizontal sync pulse output to the output terminal 9 is used to identify the horizontal frequency in the CCIR / NTSC system and the identification ID in the EDTV-II.
Used for signal detection. Alternatively, it can be used for driving a deflection system in a television receiver, or driving a servo system in a home VTR.

Therefore, in this circuit, the output of the phase comparison circuit is input to the oscillation circuit composed of a counter via the loop filter, and the output of this oscillation circuit is input to the phase comparison circuit to form a phase locked loop. According to this, a PLL can be formed by a digital circuit.

As a result, in the circuit using the conventional analog PLL, the circuit tracking is slow, and it is difficult to form an IC using the C-MOS element, and many external parts are required. According to the present invention, it is possible to form a PLL with a digital circuit, which has various problems, and the circuit can follow quickly, and an IC using a C-MOS element can be obtained.
It is possible to obtain a circuit that can be easily realized.

That is, in the above-mentioned circuit, since the circuits after the edge detection circuit 2 are all processed digitally, the number of external parts is small even when the circuit is integrated into an IC, and the circuit can be easily integrated into an LSI. You can do no adjustment,
The cost of the entire device can be reduced.

Further, by forming a PLL in the above-mentioned circuit, it is possible to obtain an output with little fluctuation even when a noisy synchronizing signal such as a weak electric field is input. Further, since it is a digitally configured PLL, the output pulse is synchronized with the clock signal, which is suitable for use in a digital circuit.

Further, unlike the conventional analog configuration PLL, the above-described circuit can quickly follow a discontinuous sync signal, and can favorably interpolate a missing sync signal and remove an incorrect sync signal. it can.

Further, in the above-mentioned circuit, the oscillation circuit 6 serving as a variable frequency oscillator can be specifically constructed as shown in FIG. 5, for example.

That is, in FIG. 5, the count value of the counter 60 constituting the oscillation circuit 6 is the changeover switch 6
It is supplied to the latch circuit 40 which constitutes the phase comparison circuit 4 through one fixed contact of 1. The output signal from the AND gate 3 is supplied to the latch terminal of the latch circuit 40.

Further, the count value of the counter 60 is supplied to the subtraction circuit 62, and from this count value, the loop filter 5
The value of the latch circuit 40 via is subtracted. Further, the output value of the subtraction circuit 62 is supplied to the latch circuit 40 through the other fixed contact of the changeover switch 61.

The output value of the subtraction circuit 62 is "-
1 ”is supplied to the detection circuit 63. Then, the detection signal from the detection circuit 63 is supplied to the reset terminal of the counter 60 together with the signal from the AND gate 14 through the OR circuit 64. Further, the changeover switch 61 is changed over according to the count value of the counter 60.

Therefore, in this circuit, the latch circuit 40
, The value from the changeover switch 61 at the time when the output signal from the AND gate 3 is supplied is latched. Then, the latched value is supplied to the loop filter 5. Here, this loop filter 5 is, for example, “910”.
The value obtained by adding and subtracting the latched value from this value is output.

That is, in this circuit, "910" is usually taken out from the loop filter 5 as shown in FIG. In addition, the counter 60 outputs a value that is incremented for each clock signal.
When it becomes "09", the output value of the subtraction circuit 62 becomes "-1", and the detection output is obtained from the detection circuit 63. This resets the counter 60 and continues counting 0 to 909 repeatedly.

The changeover switch 61 selects the output value of the counter 60 when the count value of the counter 60 is from 0 to an arbitrary value, and selects the output value of the subtraction circuit 62 until it is reset thereafter. As a result, a value that changes between positive and negative before and after the reset is taken out from the change-over switch 61. Further, the value from the change-over switch 61 is latched when the output signal from the AND gate 3 is supplied. Others are the same as in FIG. 1 described above.

As a result, "0" is normally latched in the latch circuit 40. On the other hand, when a phase fluctuation occurs, the latched value is changed between positive and negative depending on the fluctuation, and this change is passed through the loop filter 5 to the subtraction circuit 62.
Is supplied to the detection circuit 63, and the detection timing of “−1” in the detection circuit 63 is changed. Therefore, the reset interval of the counter 60 is changed, the frequency division ratio of the counter 60 is changed, and the oscillation circuit 6 serving as a variable frequency oscillator is configured.

In the loop filter 5, "91
The value latched in the latch circuit 40 is added and subtracted with "0" as a reference and output. In this case, the loop filter 5 does not perform the addition / subtraction as it is, but the value latched in the latch circuit 40 is set to, for example, 1/4 to perform the addition / subtraction, so that the integration effect is generated and the low-pass filter function is provided. be able to.

Further, by optionally setting the characteristics of this low-pass filter, for example, a VT for home use can be obtained.
It is possible to form the characteristics of the loop filter 5 that are necessary in each of R and the television receiver.

In this way, according to the digital PLL and the sync separation circuit described above, the gate circuit that gates the sync signal extracted from the video signal with the mask signal, the phase comparison circuit to which the gated sync signal is input, and the phase comparison are performed. The output of the circuit is input to the oscillation circuit composed of the counter via the loop filter, and the output of this oscillation circuit is input to the phase comparison circuit, and the mask signal is generated from the output of the oscillation circuit. A mask signal generation circuit, a counting means for counting the number of consecutive absences of the synchronization signal during the mask signal from the gate circuit, and a synchronization signal extracted from the video signal when the number exceeds a predetermined value. By including a reset means for resetting a counter included in the oscillation circuit, a PLL can be formed with a digital circuit, Tracking fast, also those which can be an IC by C-MOS device obtained an easy circuit.

[0049]

According to the present invention, the output of the phase comparison circuit is input to the oscillation circuit composed of the counter through the loop filter, and the output of the oscillation circuit is input to the phase comparison circuit to obtain the phase locked loop. According to this, it becomes possible to form a PLL with a digital circuit.

As a result, in the circuit using the conventional analog PLL, the circuit tracking is slow, and it is difficult to form an IC using the C-MOS element, and many external parts are required. According to the present invention, it is possible to form a PLL with a digital circuit, which has various problems, and the circuit can follow quickly, and an IC using a C-MOS element can be obtained.
It is possible to obtain a circuit that can be easily implemented.

That is, in the circuit of the present invention, since the circuits after the edge detection circuit are all processed digitally, the number of external parts is small even when this circuit is integrated into an IC, and it can be easily integrated into an LSI. You can do no adjustment,
The cost of the entire device can be reduced.

Further, by forming a PLL in the circuit of the present invention, it is possible to obtain an output with little fluctuation even when a noisy synchronizing signal such as a weak electric field is input. Further, since it is a digitally configured PLL, the output pulse is synchronized with the clock signal, which is suitable for use in a digital circuit.

Further, the circuit of the present invention, unlike the conventional PLL having an analog structure, can quickly follow a discontinuous sync signal, and can favorably interpolate a missing sync signal and remove an incorrect sync signal. Is something that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an example of a receiver to which a digital PLL and a sync separation circuit according to the present invention are applied.

FIG. 2 is a diagram for explaining the operation.

FIG. 3 is a diagram for explaining the operation.

FIG. 4 is a diagram for explaining the operation.

FIG. 5 is a configuration diagram showing a specific circuit example of the present invention.

FIG. 6 is a diagram for explaining the operation.

FIG. 7 is a configuration diagram of a conventional analog PLL.

FIG. 8 is a diagram for explaining this.

[Explanation of symbols]

 1 Sync separation circuit 2 Edge detection circuit 3, 11, 12, 14 AND gate 4 Phase comparison circuit 5 Loop filter 6 Oscillation circuit 7 Clock signal terminal 8 Pulse generation circuit 9, 17 Output terminal 10 Mask signal generation circuit 13 Counter 15 Pulse width Detection circuit 16 Signal processing circuit 100 Tuner 101 Input terminal 200 C-MOS LSI

Front Page Continuation (72) Inventor Shinichiro Miyazaki 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Hidefumi Naito 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation Shares In the company

Claims (4)

[Claims] 1. A gate circuit that gates a synchronization signal extracted from a video signal with a mask signal, a phase comparison circuit to which the gated synchronization signal is input, and an output of the phase comparison circuit via a loop filter. A phase lock loop which is input to an oscillation circuit composed of a counter and the output of this oscillation circuit is input to the phase comparison circuit, and a mask signal generation circuit which generates the mask signal from the output of the oscillation circuit. Counting means for counting the number of consecutive absences of the synchronizing signal during the mask signal period from the gate circuit, and the synchronizing signal extracted from the video signal when the number of times exceeds a predetermined value. A digital PLL circuit, comprising: a reset unit that resets a counter that configures an oscillation circuit. 2. The digital PLL circuit according to claim 1, further comprising, in a preceding stage of the gate circuit, blocking means for blocking a signal after a lapse of a predetermined time after the synchronization signal is detected within the mask signal period. A digital PLL circuit characterized by the above. 3. The digital PLL circuit according to claim 1, wherein the oscillating circuit includes: the counter that counts a predetermined clock signal; and a latch circuit that latches a count output of the counter with the gated synchronization signal. A subtraction circuit that subtracts the latched value from the count output of the counter through the loop filter; reset means that detects a predetermined value from the subtraction circuit and resets the counter; And a switching means for switching and supplying the value of 1 to the latch circuit according to the count output of the counter. 4. A gate circuit that gates a synchronization signal extracted from a video signal received by a tuner unit with a mask signal, a phase comparison circuit to which the gated synchronization signal is input, and an output of the phase comparison circuit. Is input to an oscillation circuit composed of a counter through a loop filter, and the output of this oscillation circuit is input to the phase comparison circuit, and the mask signal is generated from the output of the oscillation circuit. A mask signal generation circuit, a counting means for counting the number of consecutive absences of the synchronizing signal during the mask signal period from the gate circuit, and when the number of times exceeds a predetermined value, it is extracted from the video signal. Reset means for resetting the counter constituting the oscillation circuit by the generated synchronizing signal, and output from the output of the oscillation circuit constituted by the counter And a sync pulse generating circuit for generating a sync pulse.