JP3211685B2 - Horizontal address generation circuit for television video signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a horizontal address of a television video signal, and more particularly to a circuit for performing image processing of a television video signal on which jitter or noise is superimposed due to line distortion or the like as in a frame synchronizer. It relates to a required horizontal address generation circuit.

[0002]

2. Description of the Related Art Conventionally, in a horizontal address generating circuit of this type, as shown in FIG. 9, a monomulti 11, flip-flop circuits (DFF) 12 to 15, an inverter circuit 16, an exclusive OR circuit, 17 and AND circuit 1
8, 19, OR circuit 20, 10-bit counter 21
And decoders 22 and 23.

[0003] The above-mentioned horizontal address circuit uses NTSC (Na).
Tional Television System
FIG. 10 and FIG. 11 (FIG. 11 shows details of a portion C in FIG. 10). The clock signal 102 shown in FIG. 9 is a signal having a cycle four times that of the subcarrier signal 103.

A composite synchronizing signal 101 of an input television image signal is a mono-multi 11 (3/4 H width is a resistor R connected to the mono-multi) having a 3/4 H width (about 47 μS) starting from the leading edge of synchronization. Is determined by the time constant of the horizontal synchronizing signal 15 and the capacitor C).
It becomes 1.

The horizontal synchronizing signal 151 is supplied to the inverter circuit 16
, A horizontal synchronization delay signal 153 delayed by two clocks by the flip-flops 13 and 15, a 2FSC signal 154 having a period twice as long as the subcarrier signal 103, and a count value of the 10-bit counter 21. Is externally cleared by an AND circuit 19 from a decode pulse 155 obtained by decoding
R) Create pulse 156.

[0006] A decode pulse 1 obtained by decoding the count value of the 10-bit counter 21 by the decoder 23 is used.
The internal clear pulse 158 is generated by the AND circuit 18 from the signal 57 and the 2FSC signal 154.

The external clear pulse 156 and the internal clear pulse 158 are supplied to the clear terminal CL of the 10-bit counter 21.
By inputting to R, the counter value of the 10-bit counter 21 becomes a horizontal address 159 of a television video signal that repeats “0” to “909” in the horizontal synchronization cycle.

The decode pulse 155 sets an external clear prohibited area, and its width (in this circuit, "9
The external clear pulse 156 is not output in the range from “06” to “1” for three 2FSC signals). That is, the horizontal address 159 does not change even if there is jitter in the composite synchronization signal 101 in this range.

In the prior art, as described above, an external clear inhibition area having a width of two or more 2FSC signals is provided to prevent disturbance of the horizontal address 159 due to jitter of the composite synchronization signal 101.

[0010]

In the above-described conventional horizontal address generating circuit, an external clear inhibition area having a width of two or more 2FSC signals is required in order to prevent the horizontal address from being disturbed due to the jitter of the composite synchronizing signal. Becomes

However, since the position of the external clear pulse is determined by the 2FSC signal, if the width of the external clear prohibition area is two or more of the 2FSC signals, the start point of the horizontal address 0 is as many as the number of signals. That is, the horizontal address is shifted with respect to the composite synchronization signal.

In addition, the phase relationship between the horizontal address and the subcarrier signal becomes uncertain, and it becomes impossible to determine a color frame (determination of the first frame or the second frame of the television video signal). The phases of three types of horizontal addresses generated when an external clear prohibited area having a width of three 2FSC signals is used are shown in FIG.

That is, in the case, the position of the external clear pulse 156 is in the external clear prohibited area [decoder pulse 1
55 is in the range of H (high) level], the internal clear pulse (decoder pulse 157) is
The case where the signal is generated one FSC signal one time before 56 is shown.

In the case, the external clear pulse 15
6 is in the external clear prohibited area [decoder pulse 155
Is in the range of H (high) level], the internal clear pulse (decoder pulse 157) is
The case where it occurs simultaneously is shown. That is, the case shows that the internal clear pulse is correctly output.

Further, in the case, the external clear pulse 1
The position 56 is in the external clear prohibited area [decoder pulse 15
5 is in the H (high) level range] when the internal clear pulse (decoder pulse 157) is
6 shows a case that occurs after one 2FSC signal than 6. In addition, the wider the external clear prohibited area is, the more
The deviation between the internal clear pulse and the external clear pulse increases, and the number of combinations thereof increases.

If an undershoot of a front porch of a television video signal generated by line distortion is generated as a spike-like pulse in a composite synchronization signal separated in synchronization, a synchronization leading edge is generated. , The start of the horizontal sync signal having a width of 3 / 4H is shifted, and the horizontal address shifts because an external clear pulse is generated based on the shifted horizontal sync signal.

Therefore, an object of the present invention is to solve the above-mentioned problems, and to prevent the composite synchronizing signal from being disturbed even if it does not have a plurality of start points and has a jitter or spike-like pulse in the composite synchronizing signal. An object of the present invention is to provide a horizontal address generation circuit capable of generating a horizontal address.

[0018]

SUMMARY OF THE INVENTION A horizontal address generation circuit according to the present invention includes a counter for generating a horizontal address based on a composite synchronizing signal synchronously separated from a television video signal. A circuit, integrating means for integrating the composite synchronization signal to remove spike-like pulses of the composite synchronization signal;
Horizontal synchronization width detection means for detecting the width from the leading edge to the trailing edge of the composite synchronization signal integrated by the integration means to extract the phase of only the horizontal synchronization signal; and the horizontal synchronization signal extracted by the horizontal synchronization width detection means. An external clear pulse for clearing the counter value of the counter unit when the phase of only the horizontal synchronization signal is biased in a fixed direction by comparing the phase of the signal unit with the phase of the output of the counter unit. Horizontal phase detecting means for outputting the horizontal synchronization width
Outputting means for outputting the composite synchronizing signal integrated by the integrating means;
A counter for detecting the width from the leading edge to the trailing edge of the
The leading edge of one clock width is added to the leading edge of the synchronizing section of the composite synchronization signal.
Generates 1-clock-width trailing-edge pulse at the trailing edge of the pulse and synchronization section
Means for performing the counter, the leading edge pulse and the trailing edge pulse.
Means for outputting the horizontal synchronization signal based on the
The external clear pulse determines a start point of the counter unit by the external clear pulse, and a phase of the external clear pulse is determined by an internal clear pulse generated from a counter value of the counter unit even when the external clear pulse is not given in a horizontal cycle. Is generated to generate a horizontal address.

When a television image signal in which waveform distortion or noise is superimposed due to the influence of the transmission line of the television image signal is synchronously separated, a composite synchronous signal having jitter and spike-like pulses is obtained.

The spike-like pulse of the composite synchronizing signal having such jitter and spike-like pulse is removed by a digital integrator using an up / down counter, and the width of the integrated composite synchronizing signal from the leading edge to the trailing edge is removed. The horizontal sync width detector detects the phase of only the horizontal sync signal using a counter, and the horizontal phase detector detects the phase of the horizontal sync signal only and the phase of the counter output for the horizontal address using the horizontal phase detector. And outputs an external clear pulse to a horizontal address counter when the phase of only the horizontal synchronizing signal is deviated in a certain direction.

The horizontal address counter determines the start point by the external clear pulse, and holds the phase of the external clear pulse by the internal clear pulse generated from the internal counter value even if the external clear pulse is not given in the horizontal cycle. By generating a horizontal address to be generated, a stable horizontal address is generated.

This makes it possible to generate a horizontal address which does not have a plurality of start points for the composite synchronization signal and which is not disturbed even when the composite synchronization signal has a jitter or spike-like pulse.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a horizontal address generating circuit according to one embodiment of the present invention includes a digital integrator 1.
, A horizontal synchronization width detection unit 2, a horizontal phase detection unit 3, and a counter unit 4.

When synchronizing and separating a television video signal in which waveform distortion and noise are superimposed due to the influence of the transmission line of the television video signal, a composite synchronous signal having jitter and spike-like pulses is obtained.

The digital integrator 1 integrates the composite synchronization signal 101 to remove spike-like pulses. The horizontal synchronization width detector 2 detects the width from the leading edge to the trailing edge of the composite synchronization signal 111 integrated by the digital integrator 1, and extracts the phase of only the horizontal synchronization signal 121.

The horizontal phase detector 3 detects the phase of only the horizontal synchronization signal 121 extracted by the horizontal synchronization width detector 2 and the phase of the output of the counter 4 for the horizontal address [from the decoder (not shown) of the counter 4]. Decoder pulses 142 to 14
4], and outputs an external clear pulse 131 to the counter unit 4 when the phase of only the horizontal synchronization signal 121 is deviated in a certain direction.

The counter section 4 receives the external clear pulse 13
1 determines the start point, and the external clear pulse 13
Even if 1 is not given in the horizontal cycle, the external clear pulse 1 is generated by the internal clear pulse generated from the internal counter value.
A horizontal address 141 for holding 31 phases is generated.

FIG. 2 is a block diagram showing the configuration of the digital integrator 1 of FIG. In the figure, a digital integrator 1 includes a 4-bit up / down counter 1a and a decoder 1
b, 1c, inverter circuits 1d, 1k, AND circuits 1e, 1f, NAND circuits 1g, 1h, and OR circuit 1i.
And a flip-flop circuit (DFF) 1j.

FIG. 3 is a block diagram showing the configuration of the horizontal synchronizing width detecting section 2 in FIG. In the figure, a horizontal synchronization width detection unit 2 includes flip-flop circuits (DFF) 2a, 2k, inverter circuits 2b, 21, AND circuit 2c, NAND circuits 2d, 2i, 2m, 7-bit counter 2e, and decoder 2f. 2h and an OR circuit 2j.

FIG. 4 is a block diagram showing the configuration of the horizontal phase detector 3 in FIG. In the figure, a horizontal phase detector 3 includes inverter circuits 3a and 3m and AND circuits 3b, 3c,
3r, 3s, NAND circuits 3d, 3e, 3h, OR circuits 3f, 3g, 3t, 3v, flip-flop circuits (DFF) 3i-3l, 3n, 3u, 4-bit up / down counter 3o, and decoder 3p , 3q.

FIG. 5 is a block diagram showing the configuration of the counter section 4 of FIG. In the figure, a counter unit 4 includes flip-flop circuits (DFF) 4a and 4b, an exclusive OR circuit 4c, AND circuits 4d and 4e, an OR circuit 4f,
It comprises a 10-bit counter 4g and decoders 4h-4k.

FIG. 6 is a timing chart showing the operation of one embodiment of the present invention, FIG. 7 is a timing chart showing the details of the part A in FIG. 6, and FIG. 8 is the details of the part B in FIG. It is a timing chart.

The operation of the embodiment of the present invention will be described with reference to FIGS. In the embodiment of the present invention, a signal having a period four times as long as the subcarrier signal 103 is used as the clock signal 102.

The input composite synchronizing signal 101 is sent to the digital integrator 1. The digital integrator 1 uses the composite synchronization signal 101 for up / down control of the 4-bit up / down counter 1a.

That is, the 4-bit up / down counter 1a performs a countdown operation at the falling transition point of the composite synchronization signal 101, and the counter value 112 changes from "15" to "0" in order. When the counter value 112 is "0" and the composite synchronization signal 101 is at the L (low) level, that is, in the countdown operation, the count enable signal 113 goes to the H (high) level and the operation of the 4-bit up-down counter 1a is performed. Stops.

The 4-bit up / down counter 1a
Is a count-up operation at the rising transition point of the composite synchronization signal 101, and the counter value 112 changes from "0" to "15" in order. When the counter value 112 is “1”
When the state is "5" and the composite synchronization signal 101 is at the H level, that is, in the count-up operation, the count enable signal 113 goes to the H level, and the operation of the 4-bit up / down counter 1a stops. Then, the count value 112
Is in the state of "0", the flip-flop circuit 1j is set to the L level, and the state of the flip-flop circuit 1j is held until the count value 112 becomes "15", whereby the composite synchronization signal 111 is restored.

According to the operation principle of the digital integrator 1,
A 14-clock width (approximately 1
Even if the pulse up to μS) is superimposed, the pulse is removed from the restored composite synchronization signal 111.

The composite sync signal 111 output from the digital integrator 1 is sent to the horizontal sync width detector 2. The horizontal synchronizing width detector 2 generates a leading edge pulse 122 of one clock width at the leading edge of the synchronizing portion of the composite synchronizing signal 111 and a trailing edge pulse 123 of one clock width at the trailing edge of the synchronizing portion.

The leading edge pulse 122 is a 7-bit counter 2e
, The count value 124 of the 7-bit counter 2e changes from "0" to "74" sequentially from the leading edge of the composite synchronization signal 111 as a start point, and the count value 124 of the 7-bit counter 2e At the time when the count value becomes "74", the count enable signal 12 from the decoder 2h connected to the enable terminal EN of the 7-bit counter 2e.
5 becomes L level, and the operation of the 7-bit counter 2e stops.

Count value 124 of 7-bit counter 2e
Is "63", when the phase of the decoding pulse 126 from the decoder 2f outputting the L level does not match the phase of the trailing edge pulse 123, the decoding pulse 126 causes the gate signal 12 which is the output of the flip-flop circuit 2k.
7 is at L level, and the L level state is maintained until the trailing edge pulse 123 is input. When the count value 124 of the 7-bit counter 2e is "73", the decode pulse 128 from the decoder 2g, which goes to the H level, is passed through the NAND circuit 2m only when the gate signal 127 is at the H level. To produce

According to the operation principle of the horizontal synchronization width detection unit 2,
The leading edge pulse 123 of the composite synchronizing signal 111 is delayed by 74 clocks only when the synchronization section of the input composite synchronizing signal 111 is within the range of 64 clock widths (about 4.4 μS) to 72 clock widths (about 5 μS). Decoded pulse 12
8 is output. For this reason, the vertical synchronization pulse section (about 27
.mu.S) and the equalization pulse section (about 2.35 .mu.S), the synchronization width is out of specification, and the horizontal synchronization signal 121 is not output. The horizontal synchronization signal 121 is output only in the case of the horizontal synchronization pulse section (about 4.7 .mu.S). Will be done.

The horizontal synchronizing signal 121 output from the horizontal synchronizing width detecting section 2 is sent to the horizontal phase detecting section 3. In response to the decode pulse 143 from the decoder 4i in which the count value of the 10-bit counter 4g for generating the horizontal address of the counter unit 4 becomes L level from "905" to "907", the phase of the horizontal synchronizing signal 121 becomes L level. If it is within the range, it is used as clear control of the 4-bit up / down counter 3o, and the count value of the 4-bit up / down counter 3o is "0". When the phase of the horizontal synchronizing signal 121 is in the range of the H level with respect to the decode pulse 143, it is used as disable control of the 4-bit up / down counter 3o.

Up-down control signal 1 when disabled
If 32 is at the H level, the 4-bit up / down counter 3o performs a count-up operation, and its count value 1
33 is incremented by one. If the up / down control signal 132 is at the L level at the time of disabling, the 4-bit up / down counter 3o performs a countdown operation, and the count value 133 thereof is decremented by one.

As described above, the count value 133 of the 4-bit up-down counter 3o becomes "+7" or "-".
When "7" is reached, the horizontal synchronization signal 121 is converted into a 2-clock width and output as the external clear pulse 131 of the 10-bit counter 4g. The up-down control signal 1
Numeral 32 indicates that the count value of the 10-bit counter 4g is changed from "448" to "45" by the flip-flop circuit 31.
When the position of the horizontal synchronizing signal 121 is within the range of the L level with respect to the decode pulse 144 from the decoder 4h which becomes the H level up to "5", the count value of the 10-bit counter 4g becomes H from "452" to "906". The polarity becomes the same as that of the decode pulse 142 from the decoder 4j which becomes the level.

When the position of the horizontal synchronizing signal 121 is in the range of the H level with respect to the decoding pulse 144 from the decoder 4h, the previous state is held in the up / down control signal 132. Therefore, the up-down control signal 1
32 can have hysteresis equal to the clock width of the decode pulse 144, and the decode pulse 142
The horizontal synchronization signal 121
Even in the case where there is, the determination of up / down does not become unstable, and the external clear pulse 131 can be output normally.

According to the principle of operation of the horizontal synchronization detector 3, 4
The count value 133 of the bit up / down counter 3o is increased when the horizontal synchronization signal 121 is deviated leftward with respect to the horizontal address 141, reaches “+7”, and is decremented when deviated rightward. The amount increases to reach "-7". 4-bit up / down counter 3o
When the count value 133 reaches “+7” or “−7”, the external clear pulse 131 is output, so that the phase of the horizontal address 141 with respect to the horizontal synchronizing signal 121 balances the up amount and the down amount. It is a point that was taken. That is, even when the composite synchronization signal 101 has jitter, the horizontal address 14 is determined based on the center point of the jitter.
One phase will be determined.

The external clear pulse 131 output from the horizontal phase detector 3 is sent to the counter 4. When the external clear pulse 131 is at L level and the subcarrier signal 10
When the 2FSC signal 145 having a period twice as long as 3 is at L level, 1
Horizontal address 141 output from 0-bit counter 4g
Becomes “0”, and sequentially changes to “909”. Also,
The 10-bit counter 4g indicates that the horizontal address 141 is "90".
8 ”or“ 909 ”and the 2FSC signal 145 is at the L level, the count value becomes“ 0 ”, and the count value becomes“ 90 ”in order.
Turn north to 9 ". For this reason, even when the external clear pulse 131 is not sent from the horizontal phase detection unit 3, the horizontal address 141 is in a state of holding the phase determined by the external clear pulse 131.

As described above, the input composite synchronization signal 10
1 is integrated by the digital integrator 1 and the horizontal sync width detector 2 detects the horizontal sync width to extract the phase information of the horizontal sync signal 121, thereby obtaining a composite signal generated due to line distortion or noise superposition. Pulse-like noise generated in the synchronization signal 101 can be removed.

Further, the horizontal phase detector 3 detects that the position of the horizontal synchronization signal 121 extracted by the horizontal synchronization width detector 2 is shifted in the same direction (leftward or rightward) with respect to the horizontal address 141. The external clear pulse 131 is output only in this case, and the phase of the horizontal address 141 is determined at the center point of the jitter of the phase of the horizontal synchronization signal 121 by capturing the external clear pulse 131 as the start point of the horizontal address 141. As a result, there is no phase disturbance with respect to the jitter of the composite synchronization signal 101 and the horizontal address 1 in which a plurality of start points do not exist.
41 can be obtained from the counter unit 4.

[0050]

As described above, according to the present invention, a horizontal address generating circuit for a television video signal including a counter for generating a horizontal address based on a composite synchronization signal synchronously separated from the television video signal is provided. ,
After removing the spike-like pulse of the composite sync signal by integrating the composite sync signal, the width from the leading edge to the trailing edge of the composite sync signal is detected, and the phase of only the horizontal sync signal is extracted. By comparing the phase with the phase of the output of the counter section and clearing the counter value of the counter section when the phase of only the horizontal synchronization signal is deviated in a fixed direction, a plurality of start operations can be performed for the composite synchronization signal. There is an effect that it is possible to generate a horizontal address that does not have any points and is not disturbed even when there is a jitter or spike-like pulse in the composite synchronization signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a digital integrator in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a horizontal synchronization width detection unit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a horizontal phase detection unit in FIG. 1;

FIG. 5 is a block diagram illustrating a configuration of a counter unit in FIG. 1;

FIG. 6 is a timing chart showing the operation of one embodiment of the present invention.

FIG. 7 is a timing chart showing details of a portion A in FIG. 6;

8 is a timing chart showing details of a part B in FIG. 6;

FIG. 9 is a block diagram showing a configuration of a conventional example.

FIG. 10 is a timing chart showing the operation of the conventional example.

11 is a timing chart showing details of a portion C in FIG. 10;

FIG. 12 is a timing chart showing phases of three types of horizontal addresses generated when an external clear inhibition area having a width of three 2FSC signals is used.

[Explanation of symbols]

1 Digital Integrator 1a, 3o 4-bit Up / Down Counter 1b, 1c, 2f-2h, 3p, 3q, 4h-4k Decoder 1j, 2a, 2k, 3i-3l, 3n, 3u, 4a, 4
b Flip-flop circuit 2 Horizontal sync width detector 2e 7-bit counter 3 Horizontal phase detector 4 Counter 4g 10-bit counter

Continuation of the front page (56) References JP-A-4-354475 (JP, A) JP-A-61-70861 (JP, A) JP-A-63-153963 (JP, A) JP-A-8-51555 (JP, A) JP-A-6-232741 (JP, A) JP-A-5-292432 (JP, A) JP-A-2-57668 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04N 5/04-5/12

Claims (3)

(57) [Claims] 1. A horizontal address generation circuit for a television video signal including a counter unit for generating a horizontal address based on a composite synchronization signal synchronously separated from a television video signal, wherein the horizontal address generation circuit integrates the composite synchronization signal. Integrating means for removing a spike-like pulse of the composite synchronizing signal; and horizontal synchronization for detecting a width from a leading edge to a trailing edge of the composite synchronizing signal integrated by the integrating means and extracting a phase of only the horizontal synchronizing signal. Width detecting means, and comparing the phase of only the horizontal synchronizing signal extracted by the horizontal synchronizing width detecting means with the phase of the output of the counter section, and when the phase of only the horizontal synchronizing signal is biased in a certain direction, the counter external clear pulse to clear the counter value of the parts and a horizontal phase detecting means for outputting to the counter part, the horizontal sync width detecting means, the product It has been integrated by means
The width of the composite synchronization signal from the leading edge to the trailing edge is detected.
And a counter at the leading edge of the synchronizing section of the composite synchronizing signal.
One clock width is applied to the leading edge pulse of the lock width and the trailing edge of the synchronization part.
Means for generating a trailing edge pulse, the counter and the leading edge
The horizontal synchronization signal based on the pulse and the trailing edge pulse.
Output means for determining a start point of the counter section by the external clear pulse, and the internal clear pulse generated from the counter value of the counter section even if the external clear pulse is not given in a horizontal cycle. A horizontal address generation circuit for generating a horizontal address for holding a phase of a clear pulse. 2. The horizontal address generation circuit according to claim 1, wherein said integration means includes an up / down counter for integrating said composite synchronization signal. 3. The horizontal address generating circuit according to claim 1, wherein: 3. The horizontal synchronization detecting means according to claim 2, wherein
The phase and water level of only the horizontal synchronization signal extracted by the width detection means
To compare the phase of the counter for the flat address
2. The method according to claim 1 , further comprising an up / down counter.
3. The horizontal address generating circuit according to claim 2, wherein: