JPH05336401A - Field discriminating circuit - Google Patents

Abstract

PURPOSE:To discriminate between an odd and an even field from the synchronizing signal of a television signal. CONSTITUTION:The vertical synchronizing signal VD is delayed by a time Td through a delay circuit 13 and a flip-flop circuit 14 is used to discriminate whether or not a horizontal synchronizing signal HD which is the time Td time later is H or L, thereby outputting a discriminated signal which indicates the odd or even field. Consequently, the circuit constitution is simple, and a low price and high stability are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for discriminating an odd field and an even field from sync signals such as NTSC, PAL, SECAM and HDTV which are general television signals.

[0002]

2. Description of the Related Art A conventional field discriminating circuit is disclosed, for example, in Japanese Patent Laid-Open No. 25171/1990.

FIG. 6 shows a block diagram of this conventional field discrimination circuit. Reference numeral 61 is a composite sync signal input terminal for inputting a composite sync signal, and 62 is a one-shot for separating a horizontal sync signal HD from the composite sync signal. Multivibrator circuit (hereinafter abbreviated as WMB circuit), 63 is a vertical sync signal separation circuit for separating the vertical sync signal VD from the composite sync signal and the horizontal sync signal HD, and 64 is the vertical sync signal VD.
And a field discrimination circuit for outputting the field discrimination signal FD from the composite synchronizing signal, and 15 for a field discrimination signal output terminal for outputting the field discrimination signal FD.

In the conventional field discriminating circuit configured as described above, the WMB circuit 62 is triggered by the trailing edge of the composite synchronizing signal and outputs a pulse having a pulse width of 10 μs as the horizontal synchronizing signal HD. The vertical synchronizing signal separating circuit 63 separates the vertical synchronizing signal VD using the separated horizontal synchronizing signal HD and the composite synchronizing signal. The field discrimination circuit 64 counts pulses for three horizontal periods from the time when the vertical synchronizing signal VD becomes L (or H). Then, the field is discriminated depending on whether the vertical synchronizing signal VD is H or L at the time of falling of the composite synchronizing signal.

[0005]

However, in the above-mentioned configuration, the pulses for three horizontal periods must be counted from the time when the vertical synchronizing signal becomes L (or H) in the field discriminating circuit 64. A circuit for counting is needed. Therefore, there is a problem that the circuit configuration becomes large and complicated.

In view of the above points, an object of the present invention is to provide a field discriminating circuit having a simple circuit configuration, low cost and high stability.

[0007]

SUMMARY OF THE INVENTION The present invention comprises a delay circuit for inputting a vertical synchronizing signal, and a flip-flop circuit for supplying a horizontal synchronizing signal to a signal input terminal and supplying an output signal of the delay circuit to a clock input terminal. The field discrimination circuit is characterized by being provided.

[0008]

According to the present invention, the vertical synchronizing signal is delayed by Td time and the horizontal synchronizing signal after the Td time has the H level.
, Or L is determined using a flip-flop circuit, and a signal that determines whether the field is odd or even is output.

[0009]

1 is a block diagram of a field discriminating circuit according to a first embodiment of the present invention. In FIG. 1, 11 is a vertical sync signal input terminal for inputting a vertical sync signal VD, 12 is a horizontal sync signal input terminal for inputting a horizontal sync signal HD, and 13 is a buffer for delaying the input signal for a certain period. A delay circuit, 14 is a D flip-flop circuit (hereinafter abbreviated as DFF circuit), and 15 is a field discrimination signal output terminal for outputting a field discrimination signal FD.

FIG. 2 is an operation waveform diagram of the field discriminating circuit in the first embodiment of the present invention. Here, the case of the NTSC system will be described as an example. VD indicated by 21 in FIG. 2 is a vertical synchronization signal input terminal 11
Vertical sync signal input to the horizontal sync signal, HD indicated by 22 is a horizontal sync signal input to the horizontal sync signal input terminal 12, and B indicated by 23.
S is the delayed output signal of the delay circuit 13, and FD shown at 24 is D
The field discrimination signals output from the FF circuit 14 and output to the field discrimination signal output terminals are shown.

The operation of the field discriminating circuit of this embodiment constructed as described above will be described below with reference to FIGS.
Will be explained.

First, the vertical synchronizing signal VD21 is delayed by the delay circuit 1.
When it is input to 3, the delayed output signal BS23 delayed by a fixed time Td is output. The time Td at this time may be set after the time when the horizontal synchronizing signal HD22 becomes completely L. For example, the delay time of a general TTL buffer is about 10 nsec for the LS type and about 5 nsec for the F type. Further, the CMOS buffer has a length of about 60 nsec, and if one stage is insufficient, a plurality of buffers may be formed. Next, in the DFF circuit 14,
The data of the horizontal synchronizing signal HD22 at the rising edge of the delayed output signal BS23 is held. That is, the field discrimination signal FD24 output from the DFF circuit 14 outputs L in the odd field and H in the even field.

As described above, according to this embodiment, by providing the delay circuit 13 and the DFF circuit 14, the circuit configuration is simple, highly stable and no adjustment is required, and each television system can be easily supported. You can

FIG. 3 is a block diagram of a field discriminating circuit according to the second embodiment of the present invention. In FIG. 3, 11 is a vertical synchronizing signal input terminal, 12 is a horizontal synchronizing signal input terminal, 14 is a DFF circuit, and 15 is a field discrimination signal output terminal, which are the same as those in the first embodiment and are the same. A number is added and the description is omitted here. The difference from the first embodiment is that 31 indicates a WMB circuit that outputs a certain pulse width by using the falling edge of the input signal as a trigger.

FIG. 4 shows an operation waveform diagram of the field discriminating circuit in the second embodiment of the present invention. Here, the case of the NTSC system will be described as in the first embodiment. In FIG. 4, VD shown at 21 is a vertical synchronizing signal, HD shown at 22 is a horizontal synchronizing signal, and FD shown at 24 is a field discriminating signal. Therefore, the description here is omitted. The difference from the first embodiment is that the WS shown in 41 is a WM.
This is the point showing the pulse output signal of the B circuit 31.

In the field discriminating circuit of this embodiment having the above-mentioned structure, the operation will be described below with reference to FIGS.
Will be explained.

First, when the vertical synchronizing signal VD21 is input to the WMB circuit 31, a pulse output signal WS41 having a pulse width of time Tw from the falling edge is output. The time Tw at this time sets the pulse width circuit constant RC of the WMB circuit 31 so that the horizontal synchronizing signal HD22 is in the L period. For example, in the case of NTSC, the period during which the horizontal synchronizing signal HD22 is L is 4.7 μsec, so the time is set within that period.

Next, the horizontal synchronizing signal HD22 is input to the signal input of the DFF circuit 14, and the pulse output signal WS is input to the clock input.
Enter 41 respectively. Then, the DFF circuit 14 takes in the signal input at the rising edge of the clock input, and therefore becomes L in the odd field. On the other hand, in the even-numbered field, the vertical synchronizing signal VD21 and the horizontal synchronizing signal HD22 are out of phase with each other, and thus become H. After all, the field discrimination signal FD24 outputs L in the odd field and H in the even field.

As described above, according to this embodiment, the WMB
By providing the circuit 31 and the DFF circuit 14, the circuit configuration is simple, and the pulse width circuit constant R of the WMB circuit 31 is R.
Each television system can be easily supported only by changing C.

In the first embodiment, the delay circuit 13
Is constituted by a buffer, but a similar effect can be obtained by a delay circuit constituted by an integrating circuit having a resistor R and a capacitor C as shown in FIG. Although the case of NTSC has been described here, other methods (for example, PAL, SECAM, HDTV, etc.) are used.
It goes without saying that the same effect can be obtained even with ().

[0021]

As described above, according to the present invention,
It is possible to provide a field discriminating circuit having a simple circuit configuration, low cost, and high stability, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a field discrimination circuit according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the embodiment.

FIG. 3 is a block diagram of a field discrimination circuit according to a second embodiment of the present invention.

FIG. 4 is an operation waveform diagram of the embodiment.

FIG. 5 is a configuration diagram of a delay circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a conventional field discrimination circuit.

[Explanation of symbols]

 11 Vertical Sync Signal Input Terminal 12 Horizontal Sync Signal Input Terminal 13 Delay Circuit 14 DFF Circuit 15 Field Discrimination Signal Output Terminal

Claims (4)

[Claims] 1. A field comprising a delay circuit for inputting a vertical synchronizing signal, and a flip-flop circuit for supplying a horizontal synchronizing signal to a signal input terminal and supplying an output signal of the delay circuit to a clock input terminal. Discrimination circuit. 2. The field discriminating circuit according to claim 1, wherein the delay circuit comprises a gate circuit. 3. The field discriminating circuit according to claim 1, wherein the delay circuit is composed of an integrating circuit including a capacitor and a resistor. 4. A one-shot multivibrator circuit for inputting a vertical synchronizing signal, and a flip-flop circuit for supplying a horizontal synchronizing signal to a signal input terminal and supplying an output signal of the one-shot multivibrator to a clock input terminal. Field discrimination circuit characterized by.