JP3198203B2 - Synchronous separation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separator for extracting a vertical sync signal (vertical sync pulse) from a composite sync signal used in a CRT display monitor.

[0002]

2. Description of the Related Art As a conventional sync separator for extracting a vertical sync signal from a composite sync signal, as shown in FIG. 3, an integrating circuit (low-pass filter) 1 for integrating the composite sync signal is used.
A method of slicing the signal waveform output from the comparator 2 at a constant level of slice voltage determined by the slice level adjusting resistors 3 and 4 and converting it into a vertical synchronizing signal is often used. Reference numeral 8 denotes an output resistor, a denotes an input terminal of the composite synchronization signal, b denotes a non-inverting input terminal of the comparator 2, c denotes an inverting input terminal of the comparator 2, and d denotes an output terminal of the vertical synchronizing signal.

FIG. 4 is a waveform diagram of each part of the sync separator shown in FIG. 3. FIG. 4A shows a waveform of a composite sync signal Va applied to an input terminal a, and FIG. 5 shows the waveforms of the output signal Vb (solid line) and the slice voltage Vc (dashed line) of the integrating circuit 1 inputted to the non-inverting input terminal b and the inverting input terminal c, respectively, and FIG. 5 shows a waveform of the vertical synchronization signal Vd.

[0004]

However, in such a configuration, when handling various kinds of composite synchronization signals as in a multi-scan CRT display, the integrated waveforms are different from each other. As shown in b), an unnecessary pulse having a small width may be generated at the leading edge or the trailing edge of the vertical synchronization signal. There has been a problem that the vertical synchronization becomes unstable due to the pulse, or a circuit that operates at the rising edge of the vertical synchronization signal malfunctions. As means for solving this problem, JP-A-5-6675
No. 3, JP-A-5-2147, JP-A-2-28
No. 3171 is proposed, but the circuit configuration is complicated.

An object of the present invention is to provide a synchronization separating apparatus which can prevent a malfunction with a relatively simple configuration.

[0006]

According to the present invention, the slice level of the comparator is changed from a conventional constant voltage system to a high or low slice level by a vertical synchronizing signal. That is, the sync separator includes a vertical
From the composite sync signal including the sync signal and the horizontal sync signal to the vertical
A synchronizing signal is separated and extracted. An integrating circuit for integrating the composite synchronizing signal is provided, and a slice voltage generating circuit for generating two kinds of high and low slice voltages is provided. The output signal of the integrating circuit and the output from the slice voltage generating circuit are provided. And extract the vertical sync signal from the composite sync signal.
A comparator to output provided, following the integration circuit after the rise of the vertical synchronizing signal switches the slice voltage at the rising of the output signal of the next integrating circuit after the fall of the extracted vertical synchronization signal from the comparator to a low voltage And a slice voltage switching circuit for switching the slice voltage at the time of falling of the output signal to a high voltage.

[0007]

According to the structure of the present invention, depending on the level of the vertical synchronizing signal, that is, at the time of the rising of the output signal of the next integration circuit after the falling of the vertical synchronizing signal, or at the next time after the rising of the vertical synchronizing signal. By changing the slice level of the comparator depending on whether the output signal of the integration circuit is falling or not, even if various types of composite synchronization signals are input as in the case of multi-scan, the integrated waveform of the composite synchronization signal is reduced in noise. You can slice in no time. As a result, generation of unnecessary pulses having a small width at the leading edge or trailing edge of the vertical synchronization pulse in the vertical synchronization signal is prevented.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A sync separation apparatus according to an embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, this synchronization separation device is different from the conventional synchronization separation device.
A slice voltage switching circuit 6 including a switching circuit, a capacitor 5, and a resistor 7 are newly added. The capacitor 5 and the resistor 7 together with the resistors 3 and 4
Slice voltage generation circuit 9 for generating different types of slice voltages
Is composed.

The slice voltage switching circuit 6 is turned on / off according to the level of the vertical synchronizing signal output from the comparator 2, thereby switching connection / disconnection of the resistor 7, so that the next slice after the fall of the vertical synchronizing signal is obtained. The slice level of the comparator 2 is changed depending on whether the output signal of the integration circuit rises or whether the output signal of the integration circuit falls after the rise of the vertical synchronization signal.

That is, when the vertical synchronizing signal is "0 (low level)" (after the falling of the vertical synchronizing signal), the switching elements 6a and 6b of the slice voltage switching circuit 6 are turned off. The voltage level is a voltage level determined by the resistors 3 and 4 and the capacitor 5. The vertical synchronization signal is “1 (high level)”
In this case (after the rise of the vertical synchronizing signal), the switching elements 6a and 6b of the slice voltage switching circuit 6 are turned on.
4 and 7 and the voltage level determined by the capacitor 5. In this case, the slice voltage level is low at the leading edge of the vertical sync pulse of the vertical sync signal, and is high at the trailing edge. The capacitor 5 has a function of preventing the operation of the comparator 2 from becoming unstable due to a sudden change in the slice voltage level.

FIG. 2 shows a waveform diagram of each part of the sync separator shown in FIG. 1. FIG. 2 (a) shows a waveform of a composite sync signal Va applied to an input terminal a, and FIG. 5 shows the waveforms of the output signal Vb (solid line) and the slice voltage Vc (dashed line) of the integrating circuit 1 inputted to the non-inverting input terminal b and the inverting input terminal c, respectively, and FIG. 5 shows a waveform of the vertical synchronization signal Vd.

Next, the effect of preventing malfunction due to noise components of the integrated waveform, which is the object of the present invention, will be described with reference to FIG. The composite synchronizing signal Va of FIG. 2A is a positive polarity composite synchronizing signal of the interlaced specification and contains a 1H equivalent pulse, and shows a case where the vertical synchronizing signal is delayed by 0.5H with respect to the horizontal synchronizing signal. . This composite synchronization signal Va is difficult to separate in synchronization. When the composite synchronizing signal Va is passed through the integration circuit 1, the signal Vb shown in FIG.
Waveform.

From the waveform of the signal Vb, the comparator 2
The slice voltage level to a low voltage level as the vertical sync pulse leading edge of the vertical synchronizing signal intersects the waveform of the signal Vb to the period T ₂ from T _1, also at the trailing edge of the vertical sync pulse of the vertical synchronizing signal from T ₃ to a high voltage level so as to intersect with the waveform of the signal Vb in the period T _4, it can be seen that not malfunction by setting respectively. As described above, the slice voltage level can be freely set separately for the leading edge and the trailing edge of the vertical synchronization pulse of the vertical synchronization signal by selecting the resistance values of the resistors 3, 4, and 7. Even if the integrated waveform of the signal changes, slicing can be performed at the lowest noise level, and a sync separation circuit without malfunction can be realized.

As can be seen from a comparison between FIG. 2 and FIG. 4, by switching the slice level as in this embodiment, the delay time of generation of the vertical synchronizing pulse is reduced as compared with the circuit shown in the conventional example. Vertical with little phase delay
The synchronization signal can be separated from the composite synchronization signal, and a more reliable synchronization separation circuit can be realized. In the above-described embodiment, the case where the composite sync signal has a positive polarity has been described. If the circuit configuration is set so that the slice level (at the time of rising) is set low, it is possible to realize a sync separation circuit free from malfunction as in the above embodiment.

[0015]

According to the sync separator of the present invention, the slice voltage at the time of the rise of the output signal of the next integration circuit after the fall of the vertical sync signal is switched to a low voltage, and the slice voltage after the rise of the vertical sync signal is changed. by of the fall time of the slice voltage of the output signal of the integration circuit employs a configuration for switching a high voltage, in no event the various composite synchronizing signal, such as a multi-scan with a relatively simple construction is input, Extract vertical sync signal from composite sync signal
When the horizontal
Large horizontal rate noise such as initial signal and equalizing pulse
The components can be removed stably, and a stable vertical synchronizing signal extraction operation without malfunction can be performed.

Further, it is possible to shorten the delay time of the vertical same Kipa Le <br/> scan generation from the circuit shown in the conventional example, less vertical phase delay
The synchronization signal can be separated from the composite synchronization signal, and a more reliable synchronization separation circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a synchronization separation device according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part of the sync separation device of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of an example of a conventional synchronization separation device.

FIG. 4 is a signal waveform diagram of each part of the sync separation device of FIG. 2;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 integration circuit 2 comparator 3, 4 resistance 5 capacitor 6 slice voltage switching circuit 7 resistance 8 output resistance 9 slice voltage generation circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (1)

(57) [Claims] 1. A composite including a vertical synchronizing signal and a horizontal synchronizing signal.
A synchronization component for separating and extracting the vertical synchronization signal from the combined synchronization signal
A release device, wherein an integrating circuit for integrating a composite synchronizing signal, high and low two kinds of the slice voltage generating circuit for generating a slice voltage, slice voltage output output signal of said integrating circuit from the slice voltage generating circuit And a comparator for extracting a vertical synchronization signal from the composite synchronization signal, and a slice voltage at the next rising edge of the output signal of the integration circuit after the falling edge of the vertical synchronization signal extracted from the comparator. And a slice voltage switching circuit for switching the slice voltage at the time of the fall of the output signal of the integrating circuit after the rise of the vertical synchronization signal to a high voltage.