JP3030971B2 - Synchronous separation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention extracts a stable sync separation signal even when the electric field strength is very weak, even with respect to a composite video signal having a lot of noise components and fluctuations in the sync signal level of the video signal. The present invention relates to a synchronizing separation device.

[0002]

2. Description of the Related Art FIG. 3 shows a conventionally used differential type synchronous separation circuit. In FIG. 3, 1 is an input terminal, 2 is a power supply voltage terminal, 3 is an output terminal, 4 is a ground terminal, 5, 6, 9, and 1.
0, 11 are NPN transistors, 7, 8, 12 are PNP transistors
Transistors, 13, 14, 15 are current sources, 16, 17,
Is an emitter resistor, 18 is a discharge resistor, 19 and 20 are load resistors, 21 and 22 are bias resistors, and 23 is a peak hold capacitor.

At the time of normal reception, when a negative composite video signal as shown in FIG.
A positive pulse as shown by the solid line in FIG. 4B appears in the load resistor 19 via the mirror circuit composed of the transistors 7 and 8.

On the other hand, a peak hold capacitor 23 and a discharge resistor 18 are inserted between the emitter of the transistor 9 and the ground terminal. Therefore, peak hold is performed during the synchronization period of the composite video signal, and discharge is performed by the discharge resistor 18 during the video period. As a result, a saw-tooth wave like the one-dot chain line in FIG. 4B whose potential is adjusted by the transistor 12 and the resistors 22 and 21 is generated at the base of the transistor 11.

The respective waveforms shown by the solid line and the dashed line in FIG. 4 (b) are compared with each other in voltage, and a sync separation output as shown in FIG.

[0006]

In the conventional synchronous separation device shown in FIG. 3, when the electric field strength is very weak, a waveform having a large noise component as shown in FIG. Is done. Further, there may be a case where the synchronization pulse level is lower than the normal level for some reason. At this time,
The load resistor 19 generates a positive pulse including a noise component and having a different output amplitude as shown by a solid line in FIG.

In this case, the reference based on the transistor 11
Voltage ｛ΔV₁≒ V₁[1-R_{twenty one}/ (R _{twenty one}+ R_{twenty two})]｝
As shown in FIG. 4F, the noise level of the sync separation output is
Have an effect.

The peak hold capacitor 23,
The discharge time constant determined by the discharge resistor 18 (τ ₁ = C ₂₃ ×
R ₁₈ ) is small, and when the synchronization pulse level is low, FIG.
As is clear from (e), the synchronization level may not be detected. Therefore, in order to obtain a stable synchronization separation signal, the reference voltage is set by the resistors 22 and 21, and the peak hold capacitor 23 and the discharge resistor 18 are used.
Is very important to determine the time constant, and it is extremely difficult to find the optimum value.

[0009] The present invention provides a synchronization separating apparatus which solves the above-mentioned problems.

[0010]

In order to achieve the above object, the present invention provides a synchronizing / separating apparatus comprising :
Input image signal and increase the difference from the signal voltage applied to the other end.
First differential amplifier circuit for extracting a width signal from an output terminal
And the signal of the output terminal of the first differential amplifier circuit
Extract the signal held at the constant discharge time constant to the output terminal
A first signal storage input to the other end of the first differential amplifier circuit
And a signal at the output terminal of the first signal holding circuit.
Signal and output the voltage-divided signal to the output terminal.
1 voltage dividing circuit and a first differential amplifier at one end of the input terminal pair.
The signal of the output terminal of the width circuit is input, and the other
1. A signal at an output terminal of the voltage dividing circuit of
Outputs a signal corresponding to the voltage difference between the signals applied to the terminal pair.
And a second differential amplifier circuit for outputting to the second differential amplifier.
Extract the signal separated from the output terminal of the amplifier circuit
A first sync separation circuit and an output of the first differential amplifier circuit
When the signal of the terminal is input and the first signal holding circuit is discharged.
Outputs a signal held with a discharge time constant larger than the constant
A second signal holding circuit for extracting the signal from the terminal;
Signal from the output terminal of the signal holding circuit
A second voltage dividing circuit for extracting a signal to an output terminal;
A signal at an output terminal of the first differential amplifier circuit at one end of the slave pair;
And the other end of the output terminal of the second voltage division circuit
The voltage of the signal that is input to the input terminal pair when a signal is input
Third differential amplifier for extracting a signal corresponding to the difference from an output terminal
From the output terminal of the third differential amplifier circuit.
A second sync separator to take out the separated signals, first
And a signal at the output terminal of the second sync separation circuit
Input each pair individually to output the minimum value signal or maximum value signal.
And a logical sum circuit for taking out the force terminal, the OR circuit
Characterized in that the signal at the output terminal of
It is those that.

[0011]

According to this configuration, by appropriately selecting the discharge time constants of the first and second synchronization separation circuits, the noise component is small even in the weak electric field, and the input level fluctuation during the synchronization period is suppressed. The synchronization signal can be detected, and a stable synchronization signal can be obtained.

[0012]

FIG. 1 shows a synchronizing signal separating apparatus according to an embodiment of the present invention. FIG. 2 is a signal waveform of each part in FIG. 1 and 2, the same parts as those in FIGS. 3 and 4 are given the same numbers.

In FIG. 1, elements having the same reference numerals as in FIG. 3 constitute a first synchronization separation circuit. The transistors 24, 25, 26, and 27, the capacitor 30 for peak hold, the resistor 31 for discharge, and the constant current sources 28 and 2
9. The second sync separation circuit is constituted by the resistors 32, 33 and 34. The transistors 35 and 36 and the constant current source 37 constitute an OR circuit. 38 is an output terminal.

The operation of the thus-configured synchronization separating apparatus of the present embodiment will be described below.

Similarly to the first synchronization separation circuit, in the second synchronization separation circuit as well, the synchronization period of the signal output to the load resistor 19 is peak-held by the peak-hold capacitor 30, and during the video period, the resistor 31 is used. Discharge.
As a result, a sawtooth wave whose potential is adjusted by the transistor 27 and the resistors 34 and 33 is applied to the base of the transistor 26. The first sync separation output is connected to transistor 1
0, the second sync separation output is taken out from the collector of the transistor 25 and applied to the bases of the transistors 35 and 36, respectively, which are OR circuits.
The final sync separation signal is output from the output terminal 38.

The general signal flow has been described above. Here, it is assumed that an input signal having a large noise component as shown in FIG. 2A is applied to the input terminal 1 in FIG. In this case, as in the prior art, a synchronization signal as shown in FIG. 2B is applied to the bases of the transistors 10 and 25, and ΔV ₁ ≒ V ₁ is applied to the base of the transistor 11 from the tip of the synchronization signal.
A signal which is lower by [1−R ₂₂ / (R ₂₁ + R ₂₂ )] and discharges with a time constant τ ₁ is added. A waveform as shown in FIG. 2C is obtained at the collectors of the transistors 10 and 11 constituting the differential amplifier. Although it depends on the setting of the ΔV _1,
A noise component is included in the synchronization pulse period. Also,
Even when the synchronization pulse level fluctuates and drops, the comparison voltage of the transistor 11 is reduced by the discharge, so that the synchronization pulse is output as shown in FIG.

On the other hand, the following voltage appears at the base of the transistor 26. ΔV ₂ ≒ V ₁ [1-R ₃₄ / (R ₃₃ + R ₃₄ )]> ΔV ₁ This voltage ΔV ₂ is set to a level at which a noise component is not detected as shown in FIG. 31, the time constant τ ₂ of the peak hold capacitor 30 is set to be larger than the time constant τ ₁ of the first synchronization separation circuit. The output pulse at this time does not include noise during the synchronization pulse period as shown in FIG. 2D, but may not be detected for a signal having a low synchronization level as shown in FIG.

Next, when the output signals shown in FIGS. 2C and 2D are respectively input to the bases of the transistors 35 and 36, a signal having a lower potential is output, as shown in FIG. 2E. In addition, a sync separated signal having no noise component and no missing sync signal can be obtained.

[0019]

As described above, the present invention relates to a synchronous separating apparatus which includes first and second synchronous separating circuits and outputs the logical sum of the first and second synchronous separating outputs. Even when a weak radio wave is received, a sync separation signal without noise can be obtained. Further, it has a sufficient detection capability even for an input signal having a low synchronization level, and can stably separate a synchronization separation signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a synchronization separation device according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part of the synchronization separation device according to one embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional synchronous separation device.

FIG. 4 is a signal waveform diagram of each part of the conventional synchronous separation device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input terminal 2 power supply terminal 4 ground terminal 5 to 23 element forming first synchronization separation circuit 24 to 34 element forming second synchronization separation circuit 35 to 37 element forming OR circuit 38 output terminal

Continuation of front page (56) References JP-A-3-72784 (JP, A) JP-A-54-81724 (JP, A) JP-A-49-46624 (JP, A) JP-A-55-34382 (JP, A) JP-A-2-306773 (JP, A) JP-A-57-128272 (JP, U) JP-A-61-23769 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB (Name) H04N 5/08

Claims (1)

(57) [Claims] A composite video signal is input to one end of an input terminal pair.
And amplifies the difference between the signal voltage given to the other end and the signal
A first differential amplifier circuit extracted from the output terminal;
Input the signal of the output terminal of the dynamic amplifier circuit and determine the predetermined discharge time
The signal held by the number is taken out to the output terminal and the first differential
A first signal holding circuit input to the other end of the width circuit;
Inputting the signal of the output terminal of the first signal holding circuit;
First voltage division for outputting a voltage-divided signal to an output terminal
And a first differential amplifier circuit at one end of the input terminal pair.
The signal of the output terminal is input, and the other end is connected to the first voltage divider.
A signal at an output terminal of the circuit is input and given to the input terminal pair.
Output to the output terminal according to the voltage difference of the received signal
A second differential amplifier circuit, and an output of the second differential amplifier circuit.
A first synchronization separation circuit for extracting a signal separated in synchronization from the input terminal, and a signal input to an output terminal of the first differential amplifier circuit, and
Discharge of a value larger than the discharge time constant of the first signal holding circuit.
A second method of extracting a signal held by the electric time constant from an output terminal
A signal holding circuit and an output terminal of the second signal holding circuit.
Input signal and take out voltage-divided signal to output terminal
A second voltage dividing circuit and the first terminal connected to one end of the input terminal pair;
The signal of the output terminal of the differential amplifier circuit is input, and the other end is connected to the other end.
Inputting the signal of the output terminal of the second voltage dividing circuit
Outputs a signal corresponding to the voltage difference between the signals applied to the terminal pair.
And a third differential amplifier circuit for extracting the third differential amplifier circuit.
Extracts the signal separated synchronously from the output terminal of the dynamic amplifier
A second synchronization separation circuit, and a signal at an output terminal of the first and second synchronization separation circuits
Minimum value signal or maximum value signal input individually to terminal pairs
And an OR circuit for extracting the signal to an output terminal, and a signal at an output terminal of the OR circuit is used as a synchronization separation signal.
A synchronization separation device characterized by the above-mentioned.