JP2815865B2 - Synchronous signal separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a synchronizing signal separating circuit in a television receiver, and more particularly, to a case where the amplitude level of a synchronizing signal changes. This is to ensure that the synchronization signal can be separated.

(Prior Art) FIG. 5 is a circuit diagram showing a conventional synchronizing signal separation circuit.

The base of NPN transistor Q51 is connected to input terminal IN via resistor R51 and capacitor C51. Also,
The base of the transistor Q51 is connected to the voltage source terminal Vcc via the resistor R52 and to the reference potential point via the capacitor C52. The emitter of the transistor Q51 is at the reference potential point, and the collector is the voltage source terminal V via the resistor R53.
When a composite video signal is supplied to the input terminal IN and connected to the input terminal IN, a synchronizing signal is generated at the output terminal O as a voltage drop of the resistor R53.

That is, utilizing the fact that the directions of the amplitude of the video signal and the synchronization signal of the composite video signal are different, the transistor Q51 is turned on only for the synchronization signal period to flow the collector current, and the transistor Q51 is cut off during the video signal period. It is working to become.

FIG. 6 is a waveform diagram showing a composite video signal introduced to the input terminal IN.

In order to detect only the synchronizing signal in the composite video signal, a predetermined synchronizing separation level Vth based on the leading edge level of the synchronizing signal is set. When the level of the composite video signal introduced to the input terminal IN exceeds this sync separation level Vth, the transistor Q51 is turned on to separate the sync signal.

During a period when the transistor Q51 is cut off (a period of a video signal), the capacitor C51 is charged from the voltage source terminal Vcc via the resistors R52 and R51. On the other hand, during the period in which the transistor Q51 is turned on (the period of the synchronization signal), the charge stored in the capacitor C51 is discharged to the base of the transistor Q51 via the resistor R51. The synchronization separation level Vth is set based on the charge amount of the capacitor C51. In this case, if the power supply voltage of the voltage source terminal Vcc is set sufficiently higher than the amplitude of the video signal, the charging current of the capacitor C51 can be regarded as substantially constant, and the synchronization separation level Vth is also substantially constant. can do. As described above, regardless of the amplitude of the video signal, the same synchronization separation characteristic is obtained, and the synchronization signal is separated.

However, in the conventional synchronization signal separation circuit, since the synchronization separation level Vth is substantially constant, there is a disadvantage that if the amplitude of the input synchronization signal is not constant, a constant synchronization separation characteristic cannot be obtained. .

For example, in an area where VHF band broadcasting is converted to UHF band and broadcast, a so-called collapse phenomenon in which the amplitude of a synchronization signal in a composite video signal becomes small occurs. When such a collapse phenomenon occurs, since the synchronization separation level Vth is fixed, the pedestal level portion is separated as a synchronization signal, and the reproduced image of the television set is distorted left and right, This causes a problem that the vertical synchronization is disturbed.

Also, assuming the occurrence of such a collapse phenomenon in advance,
If the sync separation level Vth is designed to be shallow, stable sync separation cannot be performed in a weak electric field region. Therefore, conventionally, the synchronization separation level Vth is designed at a compromise, and there is a problem that sufficiently satisfactory characteristics can be obtained under all conditions.

(Problems to be Solved by the Invention) As described above, in the above-described conventional synchronization signal separation circuit, when the amplitude of the synchronization signal fluctuates, there is a problem that it may not be possible to separate only the synchronization signal. was there.

The present invention has been made in view of the above problems,
It is an object of the present invention to provide a synchronization signal separation circuit capable of reliably separating only a synchronization signal even if the amplitude of the synchronization signal in a composite video signal varies.

According to the present invention, an input capacitor into which a composite video signal is introduced, and a level of the composite video signal from the input capacitor are compared with a predetermined synchronization separation reference potential. The charging path and the output path are formed during a period when the level of the positive composite video signal is lower than the sync separation reference potential or during a period when the level of the negative composite video signal is higher than the sync separation reference potential. Then, the input capacitor is charged with a charging current proportional to a difference between the synchronization separation reference potential and the level of the input composite video signal, and a pulse of a predetermined level is used as a synchronization signal in a period during which the output path is formed. A first circuit means for outputting to the output terminal; and a gate pulse indicating a predetermined period in the pedestal period is provided. The level of the composite video signal from the input capacitor is compared with the sync separation reference potential, and the level of the positive composite video signal is higher than the sync separation reference potential, or the level of the negative composite video signal is A second circuit for forming a discharge path and discharging the input capacitor with a discharge current proportional to a level of a difference between the predetermined sync separation reference potential and the pedestal level during a period in which the sync separation reference potential is lower than the sync separation reference potential; Means.

(Operation) In the present invention, the input capacitor is charged and discharged based on the level of the difference between the predetermined synchronization separation reference potential and the synchronization leading end level and the level of the difference between the predetermined synchronization separation reference potential and the pedestal level. As a result, the DC level of the video signal introduced into the first and second circuit means changes, and the predetermined synchronization separation reference potential maintains the level of the predetermined ratio of the synchronization signal. As a result, the first and second circuit means are turned on and off at a predetermined ratio level of the synchronization signal.

Hereinafter, the present invention will be described in detail with reference to the drawings. First
FIG. 1 is a circuit diagram showing one embodiment of a synchronization signal separation circuit according to the present invention.

A positive composite video signal is introduced into the input capacitor C1 via the input terminal IN1. The output terminal of the capacitor C1 is connected to the amplifier 1, and the video signal amplified by the amplifier 1 is introduced into the buffer amplifier 3 via the low-pass filter 2 including the resistor R2 and the capacitor C2. The output of the buffer amplifier 3 is introduced to the first circuit means 4 and the second circuit means 5.

When the input level becomes smaller than the synchronization separation reference potential V0 during the synchronization signal period, the first circuit means 4
, The capacitor C1 is charged, and a synchronization signal is output to the output terminal O. On the other hand, the burst gate pulse generated during the pedestal period is supplied to the input terminal of the second circuit means 5.
When the input level from the buffer amplifier 3 becomes higher than the reference potential V0 during the burst gate pulse period, the charge of the input capacitor C1 is supplied through the discharge path 7. To discharge. As described above, the input capacitor C1 is charged during the synchronization signal period and discharged during the gate pulse period. Note that the charging current to the input capacitor C1 during the synchronization signal period is proportional to the difference between the reference potential V0 and the synchronization tip level (synchronization separation level Vth), and the discharge current is proportional to the difference between the reference potential V0 and the pedestal level.

FIG. 2 is a circuit diagram showing a specific configuration of the synchronization signal separating circuit shown in FIG.

A composite video signal of positive polarity is introduced to the input terminal IN1. This composite video signal is guided to the base of the transistor Q1 via the input capacitor C1. The emitter of the transistor Q1 is connected to the emitter of the transistor Q2 via the resistor R1, and this connection point is connected to the reference potential point as the second potential point via the current source I1. The base of the transistor Q2 is connected to a reference potential point via a reference voltage source V1, and a base voltage is applied. These transistors
First by Q1, Q2, resistor R1, current source I1 and reference voltage source V1
The illustrated amplifier 1 is configured.

The collector of the transistor Q1 is connected to a voltage source terminal Vcc as a first potential point, and the collector of the transistor Q2 is connected to the voltage source terminal Vcc via a resistor R2. A capacitor C2 is connected between the collectors of the transistors Q1 and Q2. The low-pass filter 2 is configured by the resistor R2 and the capacitor C2.

The connection point of the resistor R2 and the capacitor C2 is the buffer amplifier 3
Are connected to the bases of the transistors Q3 and Q4, respectively. The collector of the transistor Q3 is connected to the reference potential point, and the emitter is connected to the voltage source terminal Vcc via the resistor R3. The first circuit means 4 comprises a transistor Q6 as a first transistor and a transistor Q5 as a second transistor, and the emitter of the transistor Q3 is connected to the transistors Q5 and Q5 of these transistors.
Also connected to the base of 6. On the other hand, the collector of the transistor Q4 is connected to the voltage source terminal Vcc, and the emitter is the current source I.
2 and to the reference potential point, and also to the base of the transistor Q7, which is the input terminal of the second circuit means 5.

The emitter of the transistor Q5 constituting the first circuit means 4 is connected to the voltage source terminal Vcc via the resistor R4, and the collector is connected to the reference potential point via the collector-emitter path of the transistor Q10 as the fourth transistor. Connected to the input capacitor C1. Transistor Q5
Is turned on and the transistor Q10 is turned off, thereby forming a charging path 6 for charging the capacitor C1 from the voltage source terminal Vcc via the resistor R4 and the transistor Q5. On the other hand, the emitter of the transistor Q6 is connected to the voltage source terminal Vcc via the resistor R5, the collector is connected to the reference potential point via the resistor R6 as an output circuit, and is also connected to the output terminal O. When the transistor Q6 is turned on, a synchronization signal output appears at the output terminal O due to the voltage drop of the resistor R6.

The collector of the transistor Q7 is connected to the reference potential point,
The emitter is connected to the emitter of a transistor Q8 forming a differential pair via a resistor R7, and to the voltage source terminal Vcc via a current source I3. An emitter-collector path of the transistor Q11, an emitter-collector path of the transistor Q12, and a collector-emitter path of the transistor Q13 are connected in series between the voltage source terminal Vcc and the base of the transistor Q8. And the collector are connected respectively. The base of the transistor Q8 is also connected to the reference potential point via the current source I4. The collector of the transistor Q8 is connected to the collector and the base of the transistor Q9 as a third transistor, and is also connected to the base of the transistor Q10. The emitter of the transistor Q9 is connected to the reference potential point, and the transistors Q9 and Q10 form a current mirror circuit. The collector of the transistor Q9 is also connected to the collector of the transistor Q14, the emitter of the transistor Q14 is connected to the reference potential point, and the base receives the burst gate pulse introduced to the input terminal IN2 as the gate pulse supply means. You. As a result, during the burst gate pulse period in which the transistors Q8 and Q9 are turned on and the transistor Q14 is turned off, a mirror current flows through the transistor Q10, and the discharge path 7 discharging the charge of the capacitor C1 from the capacitor C1 via the transistor Q10 is formed. It is formed. Note that the base-emitter voltage of each of the transistors Q3 to Q6 and Q11 to Q13 is V _BE .

Next, the operation of the thus configured embodiment circuit will be described with reference to the waveform diagrams of FIGS. 3 (a) and 3 (b).
FIG. 3A shows a composite video signal appearing at the base of the transistors Q5 and Q7, and FIG. 3B shows a burst gate pulse introduced to the input terminal IN2.

The composite video signal of positive polarity introduced into the input terminal IN1 is input to the base of the transistor Q1 via the input capacitor C1, and is amplified by the differential amplifier of the transistors Q1 and Q2, and is amplified by the low-pass filter 2 including the resistor R2 and the capacitor C2. Be guided. This low-pass filter 2 is used in a weak electric field area.
This is provided to obtain synchronization stability. The input composite video signal is guided to the bases of the transistors Q3 and Q4 of the buffer amplifier 3 after removing high-frequency components.

Thus, the composite video signal shown in FIG. 3 (a) is introduced into the bases of the transistors Q5 and Q6 from the emitter of the transistor Q3, and the bases of the transistors Q5 and Q6 have the sync separation reference potential V0 shown in FIG. It turns on when the following voltage levels are introduced. When the transistor Q6 is turned on, a synchronization signal pulse appears at the output terminal O.

On the other hand, this composite video signal is also introduced into the base of the transistor Q7 via the transistor Q4. Transistor Q7
Is Vcc−3 × V _{BE because} the base-emitter voltages of the transistors Q3, Q5 and Q4 are all V _BE . Also, a transistor that forms a differential pair with transistor Q7
As for the base potential of Q8, the voltage between the base and the emitter of the transistors Q11, Q12 and Q13 is _VBE , so that Vcc-3 × _VBE
It is. That is, the transistors Q3 to Q5, Q7 and the transistors Q11 to Q13 also act as a reference voltage source together with the power source terminal Vcc, and the synchronization separation reference potential V0 as the reference voltage is V0.
= Vcc−3 × _VBE .

Now, as a second level, a pedestal level voltage higher than the reference potential V0 is applied to the bases of the transistors Q5 and Q7.
It is assumed that V _H (see FIG. 3) is applied. Then, the transistors Q5 and Q6 are turned off, and no synchronization signal pulse appears at the output terminal 0. The potential difference between the emitters of the transistors Q7 and Q8 is ( _VH− V0),
, A current flows through the current source I3 and the resistor R7. This current flows through the collector-emitter path of the transistor Q9 while the burst gate pulse shown in FIG. 3B is at a low level, and a mirror current flows through the collector-emitter path of the transistor Q10.

The mirror current is the discharge current I _R of the capacitor C1, represented by the following formula (1).

This discharge current I _R tends to lower the input bias voltage.

Conversely, as the first level at the base of the transistors Q5 and Q7, the voltage V _{L of the} synchronous tip level lower than the reference potential V0
(See FIG. 3). Then, the sync signal pulse to the output terminal O transistor Q6 is turned on appear, flows the charging current I _C of the capacitor C1 is a transistor Q5 is turned on. The charging current I _C is resistance R4
And through the transistor Q5 to increase the input bias voltage. The charging current I _C is represented by the following equation (2).

Difference between reference potential V0 and sync tip level _VL (sync separation level
When the difference between the Vth) or the reference potential V0 and the pedestal level V _H is changed, amount of charge and discharge electric charge of the capacitor C1 is varied. For example, it is assumed that the synchronization front end level _VL decreases, (V0- _VL ) increases, and the charge amount of the capacitor C1 increases.
Then, the DC level of the video signal introduced to the transistor Q7 increases, ( _VH− V0) increases, and the capacitor C1
Discharge charge increases. Thus, the level of the difference between the reference potential V0 and the pedestal level _VH is
It operates so that Vth always has the same ratio.

This can be derived by: Assuming that the synchronizing signal period is TS and the gate pulse period is TG, the charge / discharge charge amount of the capacitor C1 in both periods is equal, so the following equation (3) is derived.

The following equation (4) is derived from the equation (3).

The left-hand side of this equation (4) shows the proportion of sync separation level Vth for the level of the difference between the reference potential V0 and the pedestal level V _H, the right side of the TS, TG, R4, R7 is because a constant value, Is also constant. Therefore, even if the amplitude of the sync signal portion changes, the sync separation level Vth also changes in proportion to this, and the sync separation level Vth is changed between the sync tip level V _L and the pedestal level V _L.
A predetermined ratio level between _H and _H is maintained. This allows
Regardless of the amplitude of the synchronization signal introduced to the input terminal IN1, the synchronization signal can be reliably separated.

Further, the ratio of the sync separation level Vth can be changed by changing the values (resistance ratio) of the resistors R4 and R7. Therefore, it is suitable for an integrated circuit in which such a resistance ratio has high accuracy (within ± 3%).

Usually, the burst gate pulse is generated based on a pulse from a horizontal oscillation circuit (not shown). Therefore, when a horizontal AFC circuit (not shown) is unlocked at the time of channel switching or the like, a burst gate pulse may be generated during a picture period of a video signal. In this case, by the difference between the reference potential V0 and the video signal level is high, the discharge current I _R becomes large. Then,
Since the sync separation level Vth approaches the pedestal level, there is a possibility that the sync separation output becomes unstable, and the locking operation of the horizontal AFC circuit requires a long time. Thus, in the present embodiment, the discharge current in such a case is set to be approximately the same as the discharge current I _R during normal operation (within about ± 20%).

FIG. 4 is a circuit diagram showing another embodiment. 4, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

The embodiment of FIG. 4 differs from the embodiment of FIG. 2 in that a transistor Q15 and an input terminal IN3 are provided. Transistor
The collector-emitter path of the transistor Q15 is connected between the collector of Q5 and the reference potential point, and a high-level pulse is introduced into the base of the transistor Q15 during the equalization pulse period and the vertical synchronization signal period via the input terminal IN3. Is done.
As a result, during the equalization pulse period and the vertical synchronization signal period, the transistor Q15 is turned on, and the capacitor C1 is turned on.
Is not charged.

Now, in order to secure the synchronization stability, the capacitor C1
Suppose that the capacity of is reduced. In this case, when the capacitor C1 is charged during the vertical synchronizing signal period, there is a problem that the synchronizing signal output from the output terminal 0 sags in the vertical cycle. Therefore, in the present embodiment, the charging of the capacitor C1 is stopped during the equalizing pulse period and the vertical synchronization signal period, and there is an effect that sag of the synchronization signal output can be prevented.

[Effects of the Invention] As described above, according to the present invention, a synchronization signal can be reliably separated even if the amplitude of the synchronization signal changes, and a high-quality reproduced image can be obtained by employing the present invention. be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a synchronization signal separating circuit according to the present invention, FIG. 2 is a circuit diagram showing a specific configuration of the circuit shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing another embodiment of the present invention, FIG. 5 is a circuit diagram showing a conventional synchronizing signal separating circuit, and FIG.
FIG. 3 is a waveform diagram showing a composite video signal introduced into the circuit shown in FIG. DESCRIPTION OF SYMBOLS 1 ... Amplifier, 2 ... Low-pass filter, 3 ... Buffer amplifier, 4 ... First circuit means, 5 ... Second circuit means, 6 ... Charge path, 7 ... Discharge path, C1 ... Input capacitors, Q1 to Q14: Transistors, R1 to R7: Resistors, IN1 to IN3: Input terminals, O: Output terminals.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/08

Claims (4)

(57) [Claims] An input capacitor into which a composite video signal is introduced, and a level of the composite video signal from the input capacitor is compared with a predetermined sync separation reference potential. A charging path and an output path are formed in a period in which the potential is lower than the potential or in a period in which the level of the negative composite video signal is higher than the synchronization separation reference potential, and the input capacitor is connected to the synchronization separation reference potential. First circuit means for charging with a charging current proportional to the difference between the level of the input composite video signal and outputting a pulse of a predetermined level as a synchronization signal to an output terminal during a period of forming the output path; A gate pulse indicating a predetermined period within the period is supplied, and during the period indicated by the gate pulse, the level of the composite video signal from the input capacitor is increased. Is compared with the sync separation reference potential, the period during which the level of the positive composite video signal is higher than the sync separation reference potential, or the level of the negative composite video signal is lower than the sync separation reference potential And a second circuit means for forming a discharge path during the predetermined period, and discharging the input capacitor with a discharge current proportional to a level of a difference between the predetermined synchronization separation reference potential and a pedestal level. Synchronization signal separation circuit. 2. An amplifying circuit to which a composite video signal including a synchronization signal is supplied via an input capacitor, wherein the amplification circuit is located between a pedestal level of the composite video signal amplified by the amplification circuit and a leading end level of the synchronization signal. A reference voltage source for generating a reference voltage having a voltage level; and a first and second transistor having one end connected to a main current path connected to a first potential point and conducting in conjunction therewith. A first circuit that compares the reference voltage with the first voltage to make a main current path conductive when a leading end level of the synchronizing signal of the composite video signal is at a first level exceeding the reference voltage; An output circuit coupled to the other end of the main current path of the first transistor for separating and outputting a synchronization signal pulse when the first transistor is turned on; and an output circuit coupled to the other end of the main current path of the second transistor, 2 A charging path for charging the input capacitor with a current proportional to a potential difference between the reference voltage and the leading end level of the synchronization signal when the transistor is turned on, and a gate corresponding to a part of a pedestal period of the amplified composite video signal. A gate pulse supply unit for outputting a pulse, a third transistor, and a fourth transistor having a main current path whose one end is connected to the second potential point when the main current path of the third transistor is conductive. Has,
Comparing the amplified composite video signal with the reference voltage in the gate pulse period, and comparing the amplified composite video signal with the reference voltage in the gate pulse period in which the composite video signal does not exceed the reference voltage.
A second circuit for conducting the main current path of the third transistor at the level of the second transistor; and a second circuit coupled to the other end of the main current path of the fourth transistor, and a potential difference between the reference voltage and the pedestal level. A discharge path for discharging the input capacitor with a proportional current;
A synchronizing signal separating circuit, wherein a DC level of a composite video signal supplied to a second circuit is changed. 3. The synchronization signal separating circuit according to claim 2, wherein a low-pass filter is provided between said amplifier circuit and said first and second circuits. 4. A synchronizing signal separator according to claim 2, further comprising means coupled to said charging path, for prohibiting charging of said input capacitor during a vertical synchronizing signal period and an equalizing pulse period. circuit.