JPS6126760B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is designed to prevent jitters (shaking and bending of the playback screen in the time axis direction) caused by uneven running of the tape, uneven rotation of the rotating part, etc. turbulence, etc.).

(Prior Art) As is known, jitter is a change in the time axis of a reproduced screen. This is nothing but a variation in the time interval of the horizontal synchronizing signal, which should originally be at equal intervals (1H is 63.5 μs).

(Objective of the Invention) Therefore, the present invention separates the horizontal synchronizing pulse from the video signal and detects and measures the time interval variation as jitter, and provides a measurement method with a simple configuration and high measurement accuracy. This is what we provide.

(Structure of the Invention) The invention of claim 1 is as shown in FIG. In the figure, 1 is a synchronization separation circuit that removes the video signal from the VTR video signal (a composite video signal consisting of a video signal and a synchronization signal as shown in Figure 3), and 2 is a synchronization separation circuit that removes the video signal as shown in the figure. an equivalent/vertical pulse removal circuit 3 for further removing equivalent pulses and vertical synchronizing pulses from the removed video signal and separating horizontal synchronizing pulses as shown in FIG.
is a first removal circuit that removes the first horizontal synchronization pulse _H1 in the horizontal synchronization pulses as shown in FIG.
4 is the horizontal synchronizing pulse _H1 removed by the first removal circuit
A second removal circuit removes the next horizontal synchronizing pulse _H2 as shown in Fig. 3, 5 is a resistor R and a capacitor C.
and an integrating circuit which integrates the horizontal synchronizing pulse which is the output of the first removal circuit 3 as shown in FIG. 3, an amplifier 6 which amplifies the integrated voltage, and C ₂
is the capacitor that charges the amplified peak voltage,
7 is a peak hold circuit that holds the peak value of the amplified voltage; 8, 9, and 10 are gate circuits;
_S1 is a discharge switch, _S2 is a charge switch, and _S3 is a hold switch.

As shown in FIG. 4, the equivalent/vertical pulse removal circuit 2 includes an integrating circuit 11 and a monostable multivibrator 1.
2 and a gate circuit 13. The integration circuit 11 integrates the equivalent pulse and the vertical synchronization pulse in the output signal of the synchronization separation circuit 1 as shown in FIG. 6B. The monostable multivibrator 12 is turned off 10 to 12 hours before the equivalent pulse starts, as shown in FIG. 6C, and turned on at trigger point A in FIG. 6B.

The gate circuit 13 uses the output signal of the synchronous separation circuit 1 as one input, and the monostable multivibrator 12
The output signal of 1 is used as the other input, and it operates only when this signal is on, so that only the horizontal synchronizing pulse is the output signal. In this case, in order to reliably remove the equivalent pulse and the vertical synchronizing pulse, the trigger point A of the monostable multivibrator 12 must be set between the equivalent pulse and the horizontal synchronizing pulse next to it; Since the TV uses interlaced scanning, the interval is 1H as shown in Figure 6 A.
In addition to the case of 0.5H, the interval is particularly narrow in the latter case. Therefore, trigger point A
It is difficult to reliably set it within that 0.5H. Even if it is set within 0.5H, the integration circuit 1
The input voltage to 1 is not necessarily constant and may be small or large.

If it is small, the peak level of the waveform integrated by the integrating circuit 11 will decrease as shown by the dashed line in Figure 6B, and the trigger point A of the monostable multivibrator 12 will move to point _A1 in Figure 6B. , enters the equivalent pulse, and the monostable multivibrator 12 turns on within the equivalent pulse, so that the equivalent pulse is not removed. When the input voltage is large, the peak level of the waveform integrated by the integrating circuit 11 increases, as shown by the two-dot chain line in Fig. 6 (b), and accordingly, the trigger point A of the monostable multivibrator 12 increases as shown by the two-dot chain line in Fig. 6 (b). Move to point A ₂ , and as shown in Figure 8, the monostable multivibrator 12 enters the horizontal synchronization pulse and then turns on. Therefore, the pulse width of the first horizontal synchronizing pulse extracted through the equivalent/vertical pulse removal circuit 2 becomes narrower. When this pulse width becomes narrower, in the present invention, switches S ₁ to _{S 3} in FIG. 2 are turned on,
Since the leading edge of the horizontal sync pulse is used as shown in Figure 3 to turn off, those switches turn on,
The off-timing will be off, causing malfunctions and resulting in jitter measurement errors.

Therefore, in the present invention, the first removal circuit 3 is provided to eliminate the first horizontal synchronization pulse among the horizontal synchronization pulses.
H ₁ , thereby increasing the spacing between the equivalent pulse and the second horizontal sync pulse H ₂ by the amount that the first horizontal sync pulse H ₁ was removed, ensuring that the spacing is Trigger point A can be set.

The first removal circuit 3 includes a delay circuit 1 as shown in FIG.
4, flip-flop circuit 15 and gate circuit 16
It consists of. This first removal circuit 3 directly inputs the horizontal synchronizing pulse shown in FIG. A horizontal synchronizing pulse delayed by a predetermined time as shown in FIG. The differential signal shown in FIG. 7c is input. As a result, the flip-flop circuit 15 is reset as shown in FIG. 7d when the differential signal shown in FIG. During this setting, the first horizontal synchronizing pulse H1 is removed and the horizontal synchronizing pulses after the second horizontal synchronizing pulse _H2 appear at the output terminal e of the gate circuit ₁₆ , as shown in FIG. 7e. There is.

The configuration and operation of the second removal circuit 4 are the same as those of the first removal circuit 3, and thereby removes the second horizontal synchronization pulse _H2 as shown in FIG.

The gate circuit 8 is designed to keep the pulse width of the pulse generated from the internal monostable multivibrator constant as shown in Figure 3', and to synchronize the rise of the pulse with the fall of the horizontal synchronizing pulse shown in the same figure. The waveform shown in FIG. 3 is created by this, and the discharge switch _S1 is turned on and off by this waveform.

The gate circuit 9 makes the pulse width of the pulse generated from the internal monostable multivibrator longer than the pulse width of the figure 3' as shown in FIG. Similarly, the waveform shown in FIG. 3 is created in synchronization with the falling edge of the horizontal synchronizing pulse shown in the same figure, thereby turning the charging switch _S2 on and off.

As shown in FIG.
The hold switch S3 is turned on at the falling edge of the third horizontal synchronizing pulse among the horizontal synchronizing pulses output from the removal circuit 4, and the discharging switch _{S1 is} turned on.
The hold switch _S3 is turned off before turning on.

As a result, the discharging switch S ₁ becomes the charging switch
It is turned on and off before S ₂ is turned on, and the horizontal synchronizing pulse from the first removal circuit 3 is accumulated in the capacitor C ₁ before being charged to the capacitor C ₁ via the charging gate circuit 9. After the charge is discharged, the charging switch _S2 is turned on and a horizontal synchronizing pulse is charged to the capacitor _C1 through the charging gate circuit 9 as shown in Fig. 3. At the peak of the integrated value, the hold switch is turned on. _S3 turns on and capacitor
The peak voltage of _C1 is applied to the peak hold circuit 7.
It is designed to be held as shown in the figure.

The invention of claim 2 is as shown in FIG. This includes the voltage-frequency conversion circuit 17 and the pulse conversion circuit 1 in the invention of claim 1.
8. A mixing circuit 19 is added.

The voltage-frequency conversion circuit 17 triggers the voltage held by the peak hold circuit 7 at the falling edge of the horizontal synchronization pulse shown in FIG. The circuit operates and converts the signal into the signal shown in FIG. The pulse conversion circuit 18 converts the signal shown in FIG.
Convert to pulse signal as shown in the figure.

The mixing circuit 19 superimposes the pulse signal shown in FIG. 3 on the composite video signal, which is also the input signal of the synchronization separation circuit 1, to produce a signal as shown in FIG. Let it appear over time.

(Operation of the invention) The invention of claim 1 operates as follows.

The composite video signal shown in FIG.
By passing through the vertical pulse removal circuit 2, sequentially,
The video signal, equivalent pulse, and vertical synchronizing signal are removed, and the horizontal synchronizing pulse is extracted as shown in FIG. This pulse passes through the first removal circuit 3 and becomes the first horizontal synchronizing pulse as shown in FIG.
H ₁ is removed and enters the gate circuit 8.

The gate circuit 8 turns the discharge switch S ₁ on and off as shown in Figure 3, so when the second and subsequent horizontal synchronization pulses are input to the gate circuit 8, the discharge switch S ₁ turns on and off, turning off the capacitor. The charge stored in _C1 is discharged. At this time, since the second and subsequent horizontal synchronizing pulses are also applied to the gate circuit 9, the charging switch _S2 is turned on as shown in Fig. 3.
The capacitor _C1, which was turned off and previously discharged, is charged by the horizontal synchronization pulse as shown in FIG. The time during which the charging switch _S2 is on (charging time) has the pulse width shown in FIG. Therefore, when the pulse width of the horizontal synchronizing pulse is large, the charging time becomes long and the peak value of the integral waveform becomes large, and when the pulse width is small, the charging time becomes short and the peak value of the integrated waveform becomes small.

Furthermore, if the pulse interval of the horizontal synchronizing pulse is larger or smaller than 63.5 .mu.s, which should be an equal interval, the magnitude becomes jitter, so the magnitude of the peak of the integral waveform is proportional to the magnitude of the jitter. Therefore, jitter is detected as a voltage of an integral waveform.

When the integral waveform reaches its peak, the gate circuit 10 turns on and off the hold switch _S3 as shown in FIG. ) is held by the peak hold circuit 7 as shown in FIG. In this case, the hold switch _S3 is turned off before the discharge switch _S1 is turned on, so when the switch _S1 is turned on, the hold by the peak hold circuit 7 should be stopped, but the hold switch _S3 is turned off. When the capacitor _C2 is turned on, the peak voltage is also charged, so the hold switch _S3 is turned off and the discharge switch is turned off.
Even when S ₁ is turned on, the held peak voltage continues as shown in FIG.

Therefore, if a waveform observation device such as an oscilloscope is connected to the output end 22 of the visual correction filter 21 after the peak hold circuit 7, the voltage held in the peak hold circuit 7 with a waveform as shown in FIG. 3 can be observed. , this allows jitter to be measured as a voltage value.

In the invention of claim 2, since the output voltage of the peak hold circuit 7 is pulse-converted and superimposed on the composite video signal as shown in FIG. When connected, the pulses (jitter) shown in Figure 3 will be displayed as a white line in the center of the screen, and when the pulse interval changes due to jitter fluctuations, the white line on the screen will sway by that amount, and that lateral fluctuation will cause jitter fluctuations. Detected as .

Up to this point, for convenience of explanation, the horizontal sync pulse to be removed, the horizontal sync pulse to operate the gate circuits 8, 9, and 10, and the horizontal sync pulse to charge the capacitor _C1 have been described as the first horizontal sync pulse and the second horizontal sync pulse, respectively. The horizontal synchronizing pulse and the third horizontal synchronizing pulse are not necessarily the first, second, and third horizontal synchronizing pulses in the present invention, but from the purpose of the present invention, and the first horizontal sync pulse is the nth,
The second horizontal sync pulse is the n+1st, the 3rd
The th horizontal sync pulse may be the (n+2) th horizontal sync pulse.

(Effect of the invention) The present invention has the following effects.

(B) Since the n-th and n+1-th horizontal synchronizing pulses are removed from the composite video signal output from the VTR, even if the trigger point A of the monostable multivibrator 12 moves slightly, the trigger point A can be reliably set between the equivalent pulse and the horizontal synchronizing pulse next to it, and therefore the equivalent pulse and the vertical synchronizing pulse can be reliably removed and the horizontal synchronizing pulse can be reliably extracted. Therefore, the gate circuits 8 and 9 are reliably operated by the n+1st horizontal synchronizing pulse and the gate circuit 10 is operated by the n+2nd horizontal synchronizing pulse, respectively, and the discharging switch S ₁ , the charging switch S ₂ , The hold switches _S3 operate reliably in sequence. Therefore, the charge accumulated in capacitor C ₁ must be discharged before a new capacitor is connected.
Although capacitor C ₁ is charged and charge is accumulated in capacitor C ₁ , there is no new charge, so no jitter error occurs and accurate jitter measurement is possible.

(b) Since the charging time for the capacitor _C1 is determined by the pulse interval of the horizontal synchronizing pulses from the n+1st onwards, the voltage held in the peak hold circuit 7 reliably corresponds to jitter and is accurate with no errors. High jitter measurements can be made.

(c) Horizontal sync pulse H ₁ next to vertical sync pulse
is located at the top of the screen of the monitor television receiver, so the presence of that pulse _H1 , combined with skew distortion (a phenomenon in which the top of the screen is distorted), causes a jitter measurement error, which is caused by the jitter that is inserted after the peak hold circuit 7. Passing through the visual correction filter 21 with a large time constant not only adversely affects skew distortion but also adversely affects subsequent correctly detected jitter values. This does not occur because the th horizontal synchronizing pulse is removed.

(d) If the n-th and n+1-th horizontal synchronizing pulses are not removed, the jitter of the same pulses may become larger than the skew distortion, and in that case, the skew distortion is included in the jitter and the jitter is replaced by the skew distortion. However, in the present invention, since the (n+1)th horizontal synchronizing pulse is removed, jitter larger than the skew distortion hardly occurs. Therefore, skew distortion and jitter can be clearly separated and measured, making it possible to measure jitter with even higher accuracy.

In addition, in the present invention, in order to further reduce the adverse effects caused by the movement of the trigger point A of the monostable multivibrator 12 when removing the equivalent pulse and the vertical synchronization pulse, a limiter is provided at the front stage of the first removal circuit 3. You can do it like this.

[Brief explanation of the drawing]

FIG. 1 is a block explanatory diagram showing an embodiment of the invention claimed in claim 1, FIG. 2 is a block explanatory diagram showing an embodiment of the invention claimed in claim 2, and FIG. 1 and 2 are explanatory diagrams of the operation of the invention shown in FIGS. An explanatory diagram, FIG. 5 is a block explanatory diagram showing an example of the first removal circuit, and FIG.
Figure 7 is an explanatory diagram of the operation of the equivalent vertical pulse removal circuit, Figure 7 is an illustration of the operation of the first elimination circuit, and Figure 8 is the relationship between the monostable multivibrator and the first horizontal synchronization pulse in the equivalent vertical pulse removal circuit. An explanatory diagram showing. 1 is a synchronous separation circuit, 2 is an equivalent/vertical pulse removal circuit, 3 is a first removal circuit, 4 is a second removal circuit, 5
is an integration circuit, 7 is a peak hold circuit, 8, 9,
10 is a gate circuit, 17 is a voltage-frequency conversion circuit, 18 is a pulse conversion circuit, and 19 is a mixing circuit.

Claims (1)

[Claims] 1. A horizontal synchronizing pulse is extracted from a composite video signal output from a VTR, and among these horizontal synchronizing pulses, up to the nth horizontal synchronizing pulse for each field is removed, and the horizontal synchronizing pulses from the (n+1)th onward are removed. The charge stored in the integrating circuit is discharged by the synchronous pulse, and then the nth
The +1st horizontal synchronizing pulse and subsequent horizontal synchronizing pulses are integrated by an integrating circuit for a time proportional to the pulse interval, and then the peak value of the voltage integrated by the integrating circuit is held by the n+2nd horizontal synchronizing pulse and subsequent horizontal synchronizing pulses. A method for measuring jitter, characterized in that jitter, which is a fluctuation in pulse intervals, is detected as a voltage value. 2. Extract horizontal synchronization pulses from the composite video signal output from the VTR, remove up to the nth horizontal synchronization pulse for each field, and use the (n+1)th and subsequent horizontal synchronization pulses to integrate the horizontal synchronization pulses into the integration circuit. Then, the horizontal synchronizing pulse from the n+1st onward is integrated by an integrating circuit for a time proportional to the pulse interval, and then the peak value of the voltage integrated by the integrating circuit is calculated as the n+2nd horizontal synchronizing pulse. The jitter, which is the pulse interval variation of the horizontal synchronizing pulse, is held at the horizontal synchronizing pulse after the th horizontal synchronizing pulse, and the jitter is detected as a voltage value, and this held voltage is converted to a frequency proportional to it by a voltage-frequency conversion circuit,
The converted output signal is converted into a pulse proportional to the jitter value using a pulse conversion circuit, and this pulse is superimposed on the composite video signal so that the same pulse appears as a white line on the TV screen. Jitter measurement method.