JP3097084B2 - Horizontal sync frequency discrimination circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronizing signal discriminating circuit for judging whether or not a composite synchronizing signal of a target horizontal synchronizing frequency is input, and a composite of a plurality of horizontal synchronizing frequencies. The present invention relates to a horizontal synchronization frequency determination circuit that determines which frequency of a synchronization signal is input in a synchronization signal.

2. Description of the Related Art In recent years, many high-resolution video media that handle frequencies other than the horizontal synchronization frequency of 15.75 KHz of standard television broadcasting have appeared.
It is necessary to determine the frequency, such as 3KHz, 31.5KHz, 32.84KHz, and automatically switch the internal circuit.

Conventionally, the circuit that determines the horizontal synchronization frequency is an individual circuit that operates with a CR time constant such as a monostable multivibrator.
It is configured using IC.

Hereinafter, an example of the above-described conventional horizontal synchronization frequency determination circuit will be described with reference to the drawings.

FIG. 7 shows a circuit diagram of a horizontal synchronization frequency discriminating circuit for discriminating frequencies of 15.75 KHz and 32.5 KHz as an example of the prior art. In FIG. 7, 70 and 71 are monostable multivibrators. 72, 73, 74 and 75 are transistors. FIG. 8 shows a monostable multivibrator.
This shows a truth table of 70 and 71 (hereinafter, monostable multivibrator may be referred to as MMV for simplicity).

The operation of the horizontal synchronization frequency determination circuit shown in FIG. 7 will be described below. First, the sync separation output extracted from the composite video signal is supplied to the transistor 72.
The composite synchronizing signal is amplified by the waveform shaping transistor 72, inverted by the transistor 73, and applied to pin 12 of the MMV 70 and pin 4 of the MMV 71.

MMVs 70 and 71 are monostable multivibrators having a retrigger function. The external CR time constant of the MMV70 is approximately 46 μS, and the external CR time constant of the MMV71 is
It is set to about 600 μS.

Since pin 13 of the MMV 70 is connected to the H level, according to the truth table of FIG. 8, the MMV 70 operates in the positive edge trigger mode. Therefore, when the signal of FIG. 9A is input to the 12th pin, the signal shown in FIG. 9B is output to the 10th pin. This means that the equivalent pulse and the vertical synchronization signal are removed from the composite synchronization signal, and only the horizontal synchronization signal remains.

3 pin of MMV71 is connected to H level, 4 pin is MMV70
According to the truth table of FIG. 8, the MMV 71 operates in the negative edge trigger mode only when pin 4 is at the L level. Therefore, when the signal shown in FIG. 9B is input to pin 5, the signal shown in FIG. 9c is output to pin 6. This is due to the narrow cut H at the end of the equivalent pulse, just for each field.
Level signal. The output of pin 6 of this MMV71 is R15
And C16, the output of H level is always taken out. This discrimination output is output through the transistor 5.

When a decoded synchronizing signal having a horizontal synchronizing frequency of 31.5 KHz is input, the MMV 70 is triggered at every rising edge of each horizontal synchronizing signal, and the output of pin 10 is always at H level. Since this output is connected to pin 3 of the MMV 71, according to the truth table of FIG. 8, the Q output of the MMV 71 is at the L level, and is taken out as a discrimination output of a 31.5 KHz horizontal synchronization signal.

However, in the horizontal synchronization frequency discrimination circuit as described above, when an empty channel output of the TV tuner is applied as an input, the monostable multivibrator is triggered even for the noise pulse. Therefore, there is a risk of malfunction. Further, when some of the horizontal synchronizing pulses are lost due to noise or the like, the trigger is not activated during that period, so that there is a disadvantage that frequency discrimination becomes unstable.

Conventionally, there is a problem that it is difficult to incorporate the circuit into a gate array because of a circuit configuration using a monostable multivibrator that operates with a CR time constant.

The present invention has been made in view of the above problems, even when a noisy pulse is added or when some of the horizontal synchronization pulses are missing,
Judge that the horizontal sync pulse is input stably,
Further, it is an object of the present invention to provide a horizontal synchronizing frequency discriminating circuit which has an advantage that its frequency can be discriminated, and since it is a circuit composed of only digital circuits, it is easy to form a gate array.

Means for Solving the Problems In order to solve the above problems, a horizontal synchronization frequency discriminating circuit of the present invention includes a period measurement unit that measures a pulse interval of an input composite synchronization signal with a time measurement counter, , And a pulse counting unit that counts whether or not the correct number of horizontal synchronization pulses are received at regular time intervals delimited by the timer.

In the configuration described above, the cycle measuring unit measures the time interval of each pulse of the composite synchronization signal every time the pulse is input, and determines whether or not this is within a certain tolerance as the cycle time of the horizontal synchronization pulse. Find out. If it is within the tolerance, it is determined that the pulse is a correct horizontal synchronization pulse. Further, the pulse counting unit counts whether or not a correct number of horizontal synchronizing pulses enters for a certain fixed time. If the number of pulses is too large or too small, it is not determined that the signal is a correct horizontal synchronization signal. In this way, by measuring the period of the pulse and observing the number of pulses for a certain period of time,
The horizontal synchronization pulse can be determined with high accuracy, and the frequency can be determined. Further, since the circuit of the present invention can be constituted entirely by digital circuits, it can be easily formed into a gate array.

Embodiment Hereinafter, a horizontal synchronization frequency determination circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a horizontal synchronizing frequency discriminating circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a period measuring unit, and 12 denotes a pulse counting unit. The composite synchronizing signal 14 enters the cycle measuring unit 11, and the cycle of the pulse is measured. Among the pulses included in the composite synchronization signal 14,
The pulse signal 15 determined to be a horizontal synchronization pulse enters the pulse counting unit 12, and its horizontal synchronization frequency is finally determined. 16 is a frequency determination result. Reference numeral 17 denotes a clock for operating an internal counter and the like, which is supplied to the cycle measuring unit 11, the pulse counting unit 12, the timer 13, and the like.

The outline of the operation of the horizontal synchronizing frequency discriminating circuit configured as described above will be described below with reference to FIGS.

FIG. 2 (a) shows input / output signals of the cycle measuring unit 11 of FIG. When the input signal shown in FIG. 2A is input to the cycle measuring unit 11, an internal cycle time measuring counter is started by a falling edge of the signal. This counter is
It operates on the clock 17 and measures the time interval until the next falling edge of the input signal. If the obtained time interval is within a preset range, one pulse signal is sent as an output to the next-stage pulse counting unit.

The timer 13 measures a certain period of time and sends a timing signal to the pulse counting unit. Then, the pulse counting unit 12 determines the frequency at each time interval.

The pulse counting unit 12 has a counter for counting the pulse signal from the period measuring unit 11 inside. FIG. 2b shows the input / output signals of the pulse counter 12 of FIG. 1, where A, B and C in the figure indicate fixed time intervals separated by the timer 13. The input signal of FIG.
When input to 12, an internal counter counts the number of pulses. At the point B in the figure, first, it is determined whether the number of pulses counted by the internal counter between A and B is too large or too small, and it is determined whether the horizontal synchronization signal is correct. Then, the counter is cleared in preparation for the determination at the next point C. Thus, the pulse counting unit 12
The frequency of the horizontal synchronization signal is determined at regular intervals.

Next, the internal circuits of the cycle measuring section 11 and the pulse counting section 12 in FIG. 1 will be specifically described using a circuit example for determining whether or not a horizontal synchronizing signal having a cycle of 63.5 μS is input.

FIG. 3A is a circuit example of the cycle measuring unit 11. A 3.58 MHz clock 300 is supplied for the operation of the counter and the flip-flop. The falling edge of the input signal 301 is captured by the flip-flop 308. Flip-flop 308
And the flip-flop 309 constitute a synchronous differentiating circuit.
Output one differential pulse from the
302 is reset, and the flip-flops 305 and 306 are reset one clock later. By these operations, the cycle time measurement counter 302 starts measuring the pulse interval. As the threshold value of the period measurement unit 11,
The decoder 303 is set for 107% of the horizontal synchronization signal period of 63.5 μS, and the decoder 304 is set for 93% of the time. The output Q of the flip-flop 305 becomes high about 59 μS after the period time measurement counter 302 starts, and the output Q of the flip-flop 306 becomes H after about 68 μS.
Since the gate is in the igh state, a signal is generated from the gate 307, which falls after approximately 59 μS and rises after 68 μS. When the input signal 301 falls again, the period time measurement counter 3
If 02 is a value between 93% and 107% of 63.5 μS, one pulse signal is output through the gate 313 which has a role of comparing the threshold value.

Note that the gate 311 has a role of preventing the next reset from being applied until approximately 59 μS after reset of the cycle time measurement counter 302.

FIG. 3B is a circuit example of the timer 13. In this embodiment, in order to reduce the number of bits of the asynchronous counter 322,
15.75KHz clock 320 separately from 3.58MHz clock 321
Is supplied from outside. When the value of the counter 322 reaches 63, one pulse is output from the output 327 by the flip-flops 324 and 325 and the gate 326. The interval between these pulses is about 4 ms.

FIG. 3C is a circuit example of the pulse counting unit 12. The pulse counting section 12 has a pulse counting counter 332 for counting the pulse signal from the cycle measuring section 11 therein. The timer 13 supplies a sampling clock to the flip-flop 335 and resets the pulse count counter 332 and the flip-flop 334 at regular intervals of about 4 ms. At the time of sampling of the flip-flop 335, if the value of the pulse counter 332 is 56 or more, the Q output of the flip-flop 334 is in the high state. When this state is sampled, the flip-flop 33
The Q output of 5 becomes High, and it is determined that the horizontal synchronizing signal having a period of 63.5 μS is input.

As described above, according to the present embodiment, the period measuring unit that measures the period of the horizontal synchronizing pulse, and the pulse counting unit that counts whether a correct number of horizontal synchronizing pulses enter for a certain period of time. With the provision of the two blocks, the periodicity of the horizontal synchronization signal can be determined with high accuracy, and its frequency can be determined.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram of a horizontal synchronization frequency discriminating circuit showing a second embodiment of the present invention. In the figure, 41 is a cycle measuring unit, 42 is a pulse counting unit, 43 is a timer, and the above is a circuit similar to the configuration of FIG. The difference from the configuration of FIG. 1 is that a noise removing unit 44 is provided as preprocessing of the cycle measuring unit 22. Input multiple synchronization signals
If a large amount of pulse noise is included in the signal 45, it is not preferable for frequency determination.
Is added as an input of the period measuring unit 41.

The operation of the circuit of the noise removing section 44 will be specifically described with reference to the circuit of FIG. In FIG. 5a, 501, 502, 503, 50
4 is a flip-flop, which constitutes a shift register,
The input signals are sequentially sampled here. Gate 50
5 is Low for all flip-flops 501, 502, 503, 504
The state is detected, and the gate 506 detects all the High states, and sets and resets the RS flip-flop 507. Then, a composite synchronization signal from which pulse noise has been removed is output to Q of the RS flip-flop 507.
Thereafter, the operation up to the frequency determination is the same as that of the first embodiment, and the description is omitted.

In the second embodiment, the circuit of the noise removing unit 44 is the circuit shown in FIG. 5A, but the same result can be obtained with the circuit shown in FIG. 5B.

Note that a similar effect can be obtained even if a capacitor is inserted between the period measuring unit 41 and the ground instead of the noise removing unit 44.

In the first and second embodiments, the circuit determines whether the horizontal synchronization frequency of the input composite synchronization signal is the target frequency. In the third and fourth embodiments, a circuit is used to determine which of a plurality of horizontal synchronization frequencies is being input.

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 6A. In the figure, reference numeral 601 denotes a synchronous measurement unit, 6
02 is a pulse counting unit, 603 is a timer, and the above is a circuit similar to the configuration of FIG. The difference from the configuration of FIG. 1 is that the internal thresholds of the period measuring unit 601 and the pulse counting unit 602 are switched by an external control terminal 606. With this function, it is possible to correspond to a plurality of horizontal periodic frequencies such as 15.75KHz, 24.83KHz, 35.5KHz.

In the third embodiment, the threshold value is switched, but in the embodiment shown in FIG. 6B, switching between the cycle measuring unit 611 and the operation clock 617 of the timer 613 is performed to support determination of a plurality of horizontal synchronization frequencies. doing. A frequency divider 616 can change the frequency division ratio. The frequency of the clock 617 is switched by the control terminal 618.

Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG. 6c. In the figure, reference numeral 621 denotes a period measuring unit, 6
22, 623, 624 are pulse counting units, 625 is a timer, and the above is a circuit similar to the configuration of FIG. The difference from the configuration of FIG. 1 is that the period measuring section 621 has a plurality of outputs and that a plurality of pulse counting sections 622, 623, 624 are provided.

The multiple outputs of the period measurement unit 621 are each 15.75 KHz
, 24.83KHz, 32.84KHz etc. are prepared according to each frequency. When the composite synchronizing signal is input, the falling edge activates an internal period time measurement counter to measure the time interval until the next falling edge. The obtained time interval is the cycle time of each frequency 63.5μS, 4
It is determined which of the values of 0.3 μS and 50.5 μS falls within the tolerance, and if there is a suitable frequency, one pulse signal is sent to an output terminal corresponding to the frequency.

The timer 625 measures a certain time by a clock and sends a timing signal to the pulse counting unit. The pulse counter performs frequency determination at each time interval.

The pulse counting units 622, 623, 624 are prepared in accordance with the frequency to be determined, and each has a period measuring unit 62 therein.
There is a counter that counts pulse signals sent from one. When a timing signal is sent from timer 625,
Each pulse counting unit checks whether the counted number of pulses falls within a tolerance of a preset value, and determines the frequency of the input horizontal synchronization signal. For example, when a composite synchronization signal having a horizontal frequency of 24.83 KHz is input, the period determination unit 62
1 sends the most pulse signals to the output end for 24.83KHz. Therefore, among the plurality of pulse counting units, only the pulse counting unit 623 for 24.83 KHz counts the largest number of pulse signals and outputs that the horizontal synchronization frequency has been determined.

As described above, by providing the external control terminal for selecting the threshold value inside the period measuring unit and the pulse counting unit,
It is possible to deal with the determination of a plurality of horizontal synchronization frequencies. In addition, according to the horizontal synchronization frequency to be determined, by providing a period measurement unit having an output terminal dedicated to that frequency and a plurality of pulse counting units, a composite synchronization signal having any horizontal synchronization frequency is input. Can be determined.

In the third and fourth embodiments, the noise removing unit 44 may be connected to the input.

Effect of the Invention As described above, the present invention has a period measuring unit that measures the period of a horizontal synchronization pulse, and a pulse counting unit that counts whether or not a correct number of horizontal synchronization pulses are received for a certain period of time. ing. With these circuits, it is possible to measure whether the input pulse falls within a certain tolerance as the period of the horizontal synchronization signal, observe the number of pulses for a certain period of time, and determine whether the number of pulses is too large or too small. By checking whether or not the frequency is the same, the period of the horizontal synchronization signal can be determined with high accuracy, and the frequency can be determined. Further, since the circuit of the present invention is entirely composed of digital circuits, it has an advantage that it can be easily formed into a gate array.

[Brief description of the drawings]

FIG. 1 is a block diagram of a horizontal synchronizing frequency discriminating circuit in a first embodiment of the present invention, FIGS. 2 (a) and (b) are input / output diagrams of the horizontal synchronizing frequency discriminating circuit of FIG. 1, and FIG. a is an example of a circuit of a period measuring unit, FIG. 3 b is an example of a circuit of a timer, and FIG.
4 is a circuit example of a pulse counting unit, FIG. 4 is a block diagram of a horizontal synchronization frequency discriminating circuit in a second embodiment of the present invention, and FIG.
6 (a) and 6 (b) are circuit examples of a noise removing unit, FIG. 6 (a) is a block diagram of a horizontal synchronization frequency discriminating circuit in a third embodiment of the present invention, and FIG. 6 (b) is a third embodiment of the present invention. FIG. 6C is a block diagram of a horizontal synchronization frequency determination circuit according to a fourth embodiment of the present invention, and FIG. 7 is a conventional horizontal synchronization frequency determination circuit having the same functions as those of the embodiment. FIG. 8 is a truth table of the monostable multivibrator, and FIGS. 9 (a), (b) and (c) are timing diagrams of the conventional horizontal synchronizing frequency discriminating circuit of FIG. 11: Period measuring unit, 12: Pulse counting unit, 13: Timer, 302: Period time measuring counter, 303, 304 ... Decoder for period time threshold value, 332: Pulse counting counter, 333: Pulse Number threshold value decoder, 44: Noise removal unit, 41: Period measurement unit, 42: Pulse counting unit,
43… Timer, 501, 502, 503, 504… Shift register, 5
11,512,513,514 …… Shift register, 601,611,621 ……
Period measuring unit, 602, 612, 622, 623, 624: pulse counting unit, 6
03,613,625 …… Timer, 606,618 …… External control terminal, 616
… Divider, 70, 71… Monostable multivibrator, 72, 73, 74, 75… Transistor.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 23/10 G01R 23/15 H04N 5/04

Claims (4)

(57) [Claims] A time measuring counter for measuring a pulse interval of an input signal; comparing a time interval measured by the time measuring counter with a cycle time of a target horizontal synchronizing frequency; If it is within the range, a period measuring unit for outputting a pulse signal, a timer for measuring a fixed time, and a pulse counter for counting an output pulse signal from the period measuring unit for each time measured by the timer And a pulse counting unit that determines that a signal having a target frequency is input if the number of pulses counted by the pulse counting counter is within a preset threshold value. When a composite synchronizing signal having a frequency is input, the values of the time measurement counter and the pulse counter are set in the period measurement unit and the pulse counter. If it fits within had values, the horizontal synchronizing frequency discrimination circuit composite synchronizing signal is characterized in that determined to be input with the horizontal synchronizing frequency of interest. 2. A post-stage of a noise removing section, comprising a shift register for storing an input signal, and taking a logical product of outputs of respective bits of the shift register to remove pulse noise from an input composite synchronizing signal. A horizontal synchronization frequency discriminating circuit to which the circuit according to claim 1 is connected. 3. The circuit according to claim 1, further comprising an external control terminal for switching between a threshold value of a period measuring unit and a threshold value of a pulse counting unit, and for determining a plurality of horizontal synchronization frequencies. A horizontal synchronization frequency discrimination circuit characterized by being able to cope. 4. The circuit according to claim 1, further comprising: a period measuring unit having a plurality of thresholds; and a plurality of pulse counting units having different thresholds, and wherein the unknown horizontal synchronization is provided. When a composite synchronization signal having a frequency is input, the values of the time measurement counter and the pulse counter are determined by determining whether the values fall within threshold values set in the period measurement unit and the pulse counter. A horizontal synchronization frequency determination circuit that can determine a plurality of horizontal synchronization frequencies.