JPS61261973A - Frame synchronizing separator circuit - Google Patents

Frame synchronizing separator circuit

Info

Publication number
JPS61261973A
JPS61261973A JP60103088A JP10308885A JPS61261973A JP S61261973 A JPS61261973 A JP S61261973A JP 60103088 A JP60103088 A JP 60103088A JP 10308885 A JP10308885 A JP 10308885A JP S61261973 A JPS61261973 A JP S61261973A
Authority
JP
Japan
Prior art keywords
circuit
frame synchronizing
supplied
signal
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60103088A
Other languages
Japanese (ja)
Other versions
JPH0628383B2 (en
Inventor
Ikuo Someya
Shingo Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Japan Broadcasting Corp
Original Assignee
Nippon Hoso Kyokai NHK
Sony Corp
Japan Broadcasting Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Hoso Kyokai NHK, Sony Corp, Japan Broadcasting Corp filed Critical Nippon Hoso Kyokai NHK
Priority to JP60103088A priority Critical patent/JPH0628383B2/en
Publication of JPS61261973A publication Critical patent/JPS61261973A/en
Publication of JPH0628383B2 publication Critical patent/JPH0628383B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To perform a separation influenced less noise with a simple constitution by detecting a frame synchronizing signal with integrating the coincidence interval of a frame synchronizing pattern with an updown counter.
CONSTITUTION: The least significant bit of a signal which is AD-converted from an input signal in an MUSE system is upplied to an input terminal 21 and also, is supplied to delay circuits 22 and 23. And each delay signal and the original input signal are supplied to exclusive OR circuits 24 and 25 and the outputs of these circuits are applied to an AND circuit 26 and the coincidence of a pattern is discriminated. And the on-time of the circuit 26 is counted by an updown counter 41 and when exceeding a prescribed value, the carry of the counter 41 is supplied to an AND circuit 34. Furthermore, the output is supplied to a 14 clock period detecting circuit 42 and a frame synchronizing pulse is obtained. Thus, it is possible to eliminate the influence of the noise with a simple circuit constitution.
COPYRIGHT: (C)1986,JPO&Japio
JP60103088A 1985-05-15 1985-05-15 Frame sync pattern separation circuit Expired - Fee Related JPH0628383B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60103088A JPH0628383B2 (en) 1985-05-15 1985-05-15 Frame sync pattern separation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60103088A JPH0628383B2 (en) 1985-05-15 1985-05-15 Frame sync pattern separation circuit

Publications (2)

Publication Number Publication Date
JPS61261973A true JPS61261973A (en) 1986-11-20
JPH0628383B2 JPH0628383B2 (en) 1994-04-13

Family

ID=14344878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60103088A Expired - Fee Related JPH0628383B2 (en) 1985-05-15 1985-05-15 Frame sync pattern separation circuit

Country Status (1)

Country Link
JP (1) JPH0628383B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148276A (en) * 1989-12-05 1992-09-15 Matsushita Electric Industrial Co., Ltd. Synchronous signal generator for the muse signal
EP0596687A2 (en) * 1992-10-31 1994-05-11 Samsung Electronics Co., Ltd. Broadcasting mode name display apparatus
WO2012144057A1 (en) * 2011-04-21 2012-10-26 富士通株式会社 Data reception apparatus, marker information extraction method, and marker position detection method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679579A (en) * 1979-11-30 1981-06-30 Seiko Epson Corp Detection circuit for vertical synchronizing signal
JPS61248674A (en) * 1985-04-26 1986-11-05 Toshiba Corp Detection circuit for frame timing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679579A (en) * 1979-11-30 1981-06-30 Seiko Epson Corp Detection circuit for vertical synchronizing signal
JPS61248674A (en) * 1985-04-26 1986-11-05 Toshiba Corp Detection circuit for frame timing

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148276A (en) * 1989-12-05 1992-09-15 Matsushita Electric Industrial Co., Ltd. Synchronous signal generator for the muse signal
EP0596687A2 (en) * 1992-10-31 1994-05-11 Samsung Electronics Co., Ltd. Broadcasting mode name display apparatus
EP0596687A3 (en) * 1992-10-31 1994-10-26 Samsung Electronics Co Ltd Broadcasting mode name display apparatus.
WO2012144057A1 (en) * 2011-04-21 2012-10-26 富士通株式会社 Data reception apparatus, marker information extraction method, and marker position detection method
JP5850047B2 (en) * 2011-04-21 2016-02-03 富士通株式会社 Data receiving apparatus, marker information extracting method, and marker position detecting method
US9647781B2 (en) 2011-04-21 2017-05-09 Fujitsu Limited Data reception device, marker information extraction method, and marker position detection method

Also Published As

Publication number Publication date
JPH0628383B2 (en) 1994-04-13

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees