JPS5851675A - Agc circuit - Google Patents

Abstract

PURPOSE:To attain AGC operation, independently of the waveform and the interval of a synchronizing signal, by controlling charges of a capacitor storing an AGC detection output in response to a signal obtained at a synchronizing separation means. CONSTITUTION:A synchronizing separation output bypass circuit 12 is formed with a resistor R1, one end 12a of the resistor R1 is connected to the emitter of a buffer use emitter follower transistor (TR)Q6 of a synchronizing separator 6 and another end 12b is connected to the base of a TRQ5 of a current mirror circuit 10. When a synchronizing signal part with small amplitude or a video signal having a synchronizing signal part which is not discriminated with distortion is inputted to this separator 6, the separator 6 discriminates the input as the synchronizing signal and outputs a high level signal during the presence of the input. Since a charge of a capacitor C1 constituting an AGC filter 9 is picked up, even if lockout is generated, the state can be restored to the normal state.

Description

[Detailed Description of the Invention] The present invention relates to the Hiromu Gσ circuit, particularly for television receivers,
The present invention relates to an AGC circuit applied to a video signal magnetic recording/reproducing device, etc.

As one of the AGC circuits applied to devices that handle video signals, such as television receivers and video signal magnetic recording and reproducing devices, it detects the amplitude of the synchronization signal, which does not change depending on the brightness of the image, and ensures that this remains constant. There is an AGC circuit that controls the amplitude of the video signal so that the

This is called a sink AGC circuit, and to explain its outline, as shown in FIG.
is applied through the input terminal 1, and the output of the GC amplifier 3 is supplied to the color signal removal circuit 4, where the color signal is removed at ζ, leaving only the Y component of the luminance signal. The signal is then input to the sync separator 6 and the sync tip clamp I) 5. The luminance signal Y is synchronized by the sync separator 6, in which a horizontal synchronizing signal portion PI having a signal width T is formed, and immediately after that, the pedestal period T is set to the pedestal level V, and subsequently the visual synchronization signal portion is formed. The signal is separated, and the separated synchronization signal clamps the luminance signal Y to a constant level during the signal @T. That is, the tip of the sync signal portion (sync tip) of the luminance signal Y is 2-amped to a constant level. The output of the sync chip clamp 5 is supplied to the AGC detector 8. A detection pulse 8G formed by a synchronization signal delayed to the pedestal position by the detection pulse generator 7 is further applied to the AGC detector 8, and the pedestal period T,
, the pedestal level V of the luminance signal Y and the reference voltage Vrd are compared, and the difference voltage is detected. This detection output is applied to the control terminal of the MGO amplifier 3 via the sink AGO filter 9, and its gain is controlled.

A specific example of the AGC detection II8 will be explained with reference to FIG. 3.The period during which the sync chip clamped video signal is input to the base of the transistor Qs and the detection pulse BG supplied from the detection pulse generator 7 exists. , the difference between the video signal and the reference voltage Vrd forming the base bias voltage of transistor 9 is output to the collectors of transistors Qa and Q. The collector current Il of the transistor Qs flows into the current mirror circuit 10 via the terminal 1Oa, and the collector current Il of the transistor Q flows into the current mirror circuit 1 (l) via the sink GC filter 9 and the terminal 10b. At this time, approximately the same current flows through the terminal 10b as the current flowing through the terminal jO&. Therefore, the DC current amplification factor M of the transistor Q is large b
Then, the current (In-Im) that is the difference between the collector currents of transistor QssQ will flow into the sink AGC filter 9 (when In<It), or the current that is the difference (In
It) is the capacitor C of the sink AGC filter 9
When Is>Is, the current flows through the transistor 9. In an equilibrium state in which the collector currents Is and 1m of transistors Qst and Q are equal, the current flowing to the terminal 10b is equal to the collector current 1m of transistor No. 9. The capacitor Cs of the rounding syncum GC filter 9 is equal to
Almost no current flows through K. Naturally, during the period in which the detection pulse BG is not supplied, all the transistors Q*""Q- are turned off, so there is no fluctuation in the charge in the capacitor Cm of the sink AGC filter 9.

When the AGC control voltage is large and the gain of the AGC amplifier circuit 3 is controlled to be small, when a video signal with a small amplitude arrives, the amplitude of the output of the AGC amplifier 3 becomes extremely small at that moment.

In this state, the synchronous separator 6 may not work properly, and the synchronous signal may not be separated, so the detection pulse BG is not generated, and the AGC detector 8 may not work properly. , the synchronization signal part P shown in FIG.
'Clamp the tip of the signal at the clamp level V, set the sync signal tip level VC to (VC=V,), and then clip it at a constant clip level v1 to set the sync signal p/
When the method of obtaining /y is applied, the output amplitude of the AGC amplifier 3 as described above becomes extremely small, and the amplitude of the video signal remains at the clamp level V, the peak level, and the lip level throughout one horizontal scanning period k. When a state exists between V and V, all signals are regarded as synchronous signals and cannot be separated. In this state, the AGC detector 8 also does not operate, the charge in the capacitor CI of the sink AGC filter 9 does not change, and the mu GC control voltage is still maintained at a value that controls the AGC amplifier 3 to the minimum gain, so-called Locked out.

In order to eliminate this drawback, it has been proposed to connect a resistor in parallel to the capacitor C1 to release the lockout, but this may reduce the detection sensitivity of the AGC detector 8, etc.
It has the disadvantage that the C function is insufficient.

The purpose of the present invention is to provide synchronization/separation even in a state where synchronization cannot be performed.
There is a K which provides an AGC circuit capable of AGC.

The present invention is designed to discharge the electric charge of a capacitor charged by the detection output signal of the MuGC detector using the output of the synchronous separation circuit.

Hereinafter, an example of the AGCD path according to the present invention will be described in detail with reference to the drawings in FIG. 3, in which reference numeral 12 denotes a synchronous separation output bypass circuit. The synchronous separation output bypass circuit is formed of a resistor R1, one end 12a of this resistor R1 is connected to the emitter of the emitter follower transistor Q6 for the synchronous separator 6 buffer, and the other end 12atxt is connected to the emitter of the transistor Q1 of the current transmission circuit 10. It is connected to the base. In addition, in the figure, X', X1Y', and Y indicate that they are respectively connected in this embodiment.

Here, a current 11 discharged from the capacitor C1 during the signal portion T of the horizontal synchronization signal portion PR in FIG.
However, vlI is the peak voltage value of the synchronization signal generated at the emitter of transistor Q-.

■, 1; is the current 1. flowing through the resistor R. The voltage drop across diode D, due to the voltage drop across transistor Q, and hf of transistor Q. As shown in equation (1), the charge on capacitor CI is discharged.

In the period d of the detection pulse BG generated during the pedestal period τ of the horizontal synchronization signal part PM in FIG. 2, the capacitor Cm
K current flowing in! , is R2I, +v, , = (It, +R4>< x, -x
−>−−−・−(2) However, % 1/, : is resistance R,
The current flowing through the terminals 10m and 10b are respectively equal.

v12; is the voltage drop across the diode DI due to the current I/K flowing through the resistor R. Also, x, small x--■, so! ,
is the formula (3). Therefore, the charge of the capacitor C is released during the period of the synchronization signal part T, and the detection pulse BGC)/f
During the Rus period, the charges accumulate and cancel each other out. Also, under normal conditions, the current I, , I, of the capacitor C1 during the period of the synchronization signal section T, is I,? , + I,
? , ” 0 ...... (4) If formula (4) is satisfied, i and sei 2 are maintained.Also,!,.

■Current of capacitor C4 1. compared to 2. It is desirable that 1 and 1 are sufficiently small, so that K is the synchronization separation output J (
The resistance value of the resistor R1 of the path circuit 12 is made large, and the peak voltage value V of the synchronizing signal or the value of the resistor R4 is selected so as to satisfy the above formula (4). As described above, the synchronizing separator 6 When a synchronization signal having a synchronization signal part that is distorted and unrecognizable is input, the synchronization separator 6 identifies all of them as synchronization signals and removes the high-level signal during the period in which they exist. output and set the emitter potential of transistor Q- to V, K. This allows current to flow through the current circuit 10 and extracts the charge from the capacitor C1, so that even if a lockout occurs, the normal state can be restored.

The AGC circuit according to the present invention has a structure including a charge control means for controlling the charge of a capacitor that accumulates the AGC detection output according to the signal obtained by the synchronization separation means, so that it can be used regardless of the waveform and interval of the synchronization signal. It has the feature of performing AGC operation. Therefore, the occurrence of a lockout state in which the AGC operation is interrupted can be prevented.

Furthermore, since the configuration includes an adding means for adding the signal obtained by the synchronization separation means and the detected output, it has the advantage that the detected output during the pedestal period does not deviate. For this reason A
The control accuracy of the GC amplifier can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional AGC circuit, FIG. 2 is an explanatory diagram of a synchronization signal, and FIG. 3 is a circuit diagram showing a partial block diagram of an embodiment of the AGC circuit of the present invention. In the figure, reference numeral 3 is an AGC amplifier, 6 is a synchronous separator, 9 is a sink AGC filter, 10 is a current circuit, 12 company synchronous separation output bypass circuit, Qs to Q- are transistors, and Dl is a diode.

Claims (2)

[Claims] (1) A synchronization separation means for separating the synchronization signal, a detection means for detecting the pedestal level of the Eirin signal, which is double-amplified with the tip of the synchronization signal portion at a certain level, and a capacitor for accumulating the detection output obtained by the interference detection means. The AGC circuit comprises charge control means for controlling the charge accumulated in the capacitor according to the signal obtained by the synchronization separation means, and performs the AGC operation regardless of the waveform and interval of the synchronization signal. An AGC circuit characterized by being configured as follows. (2) The charge control means does not include addition means for adding the signal obtained by the synchronization separation means and the detection output, and is configured to control the charge according to the addition result. AGC according to claim 1, characterized in that
[ ] Road.