JPS6036924Y2 - Horizontal oscillation frequency control circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention is a horizontal oscillation frequency control circuit that eliminates the adverse effects of spurious noise secondary to the antenna, etc. from the high voltage circuit when the video signal disappears in a television receiver, etc. Regarding.

Television receivers are equipped with an oscillation circuit that synchronizes with a synchronization signal included in a video signal.

One example is a horizontal oscillation circuit.

The oscillation operation of this circuit is as explained below.

FIG. 1 is a block diagram showing a horizontal oscillation AFC (automatic frequency control) circuit of a television receiver.

Its configuration is such that a video signal 3 is input to an input terminal 2 of a synchronous separation circuit 1, and the synchronous separation circuit 1
It is connected to a horizontal oscillation circuit 5 via a circuit (phase detection circuit) 4.

The horizontal oscillation circuit 5 is connected to one end of a primary winding of a flyback transformer 7 via a horizontal output circuit 6, and the other end of the primary winding of the flyback transformer 7 is supplied with a power supply voltage B.

One end of the secondary winding of the flyback transformer 7 is a diode 8
connected to the anode of a cathode ray tube (CRT) through
The other end is connected to ABL (automatic brightness limit circuit).

Further, one end of the secondary winding of the flyback transformer 7 is grounded, and the other end is feedback-connected to the AFC circuit 4.

Horizontal oscillation AF for a television receiver with the above configuration
The operation of the C circuit is controlled by the horizontal synchronizing signal 9 and the AFC sawtooth wave (obtained by integrating the flyback pulse) 10.
This will be briefly explained with reference to FIGS. 2 and 3, which show the following.

The synchronization signal 9 is separated from the video signal 3 by the synchronization separation circuit 1.

This separated horizontal synchronization signal 9 is compared with a sawtooth signal 10 created by integrating the flyback pulse, and the AF
The phase is detected within the C circuit 4, and an AFC voltage is generated to correct the phase shift according to the phase shift.

The oscillation frequency of the horizontal oscillation circuit 5 is oscillated in synchronization with the horizontal synchronizing signal 9 by this AFC voltage.

Note that this is the case where the video signal 3 is present.

On the other hand, when the video signal 3 disappears, that is, when there is no signal, the horizontal oscillation circuit 5 oscillates at its own (free) oscillation frequency.

This horizontal oscillation pulse is then amplified by the horizontal output circuit 6.

However, in this case, the television receiver receives switching spurs (flyback pulse rectifier diode 8 and tamper diode) synchronized with the free oscillation frequency from the circuit to which high voltage is supplied or from the horizontal output circuit 6. (switching spurious due to etc.) becomes more likely to occur.

If this spurious component jumps into the front stage of the antenna or intermediate frequency amplification circuit, a signal similar to the synchronization signal is generated, and this signal is included in the video signal path as a pseudo synchronization signal.

This pseudo synchronization signal is detected by the synchronization separation circuit 1 as a synchronization signal.

However, the pseudo synchronization signal obtained in this manner has a phase lag due to a phase lag element such as a surface wave filter provided upstream of a video intermediate frequency amplification circuit (not shown).

This is shown by the solid line waveform 11 in FIG.

The dotted line in FIG. 3 indicates the regular synchronization signal 9, T1. T2 indicates phase delay.

Therefore, if this pseudo synchronization signal 11 and the sawtooth wave voltage 10' caused by free oscillation are phase-detected by the AFC circuit 4, the detected voltage of the AFC circuit 4 instantaneously changes the free oscillation frequency of the horizontal oscillation circuit 5. (hereinafter referred to as "f", "l jump").

This fH jump causes an abnormally high voltage to be generated at the anode of the cathode ray tube, or causes the high voltage protector circuit to malfunction.

The present invention has been made in view of the above points, and includes a circuit that has a first transistor that performs a switching operation in response to a synchronization signal separated from a video signal, and that generates a constant output voltage during the switching operation period. Then, the sawtooth wave signal obtained by integrating the flyback pulse is superimposed on the above output voltage, and the integrating capacitor is charged and discharged based on the output voltage, and the charging and discharging voltage is smoothed to obtain A.
means for generating an FC voltage, a first switch means that performs a switching operation when the synchronization signal is at a normal level, and a second switch means that performs a switching operation during the flyback pulse period between a voltage source and a reference potential point. a series circuit connected in series with the voltage source, and a capacitor charged by the voltage from the voltage source, and when the first and second switching means simultaneously perform a switching operation, the charge of the capacitor is transferred through the series circuit. It has an integrating circuit for discharging, and a third switching means that performs a switching operation when the output voltage of the integrating circuit exceeds a predetermined level, and the switching operation of the third switching means causes the first transistor to switch. It is an object of the present invention to provide a horizontal oscillation frequency control circuit which is equipped with a means for performing a switching operation even when there is no synchronizing signal, and which prevents the occurrence of abnormally high voltage.

The present invention will be explained below with reference to FIG.

To explain the configuration of this figure, 4 is an AFC (phase detection) circuit, and a terminal 12 is connected to the base of a phase inverting transistor 13 and grounded via a resistor 14.

The emitter of transistor 13 is grounded, and its collector is connected to power supply terminal 16 via resistor 15 and to the base of transistor 18 via resistor 17.

The collector of this transistor 18 is connected to the terminal 19 and grounded via a resistor 60.

Further, the emitter is connected to the power supply end 16 via a resistor 20, and is connected to the collector of the transistor 23 via a series circuit of diodes 21 and 22, and is connected to the collector of the transistor 23 via a series circuit of diodes 21 and 24. connected to the base.

The base of this transistor 23 is grounded via a resistor 25, and the emitter is also grounded.

Further, the colefter of the transistor 23 is connected to the base of a transistor 27 via a diode 26 and to the base of a transistor 30 via a series circuit of diodes 28 and 29.

Transistors 30 and 27 are complementary connected.

Among these, the collector of the transistor 30 is connected to the power supply terminal 16 via a resistor 31, and the emitter of the transistor 27 is grounded via a clamp circuit 32 having a clamp level Vo.

A resistor 33 is connected to the collector of the transistor 30, and the other end is placed at the connection point between the diodes 28 and 29.

The emitter of the transistor 30 and the collector of the transistor 27 are connected to a terminal 35 via a resistor 34.

A synchronizing signal control circuit 56, which exhibits the features of the present invention, is connected to each terminal of the AFC circuit 4 having the above configuration.

That is, the terminal 12 is connected via a resistor 36 to the emitter of a transistor 37 constituting a third switching circuit.

The base of the transistor 37 is connected to the collector of the transistor 38 constituting the first switching circuit, and is also grounded via an integrating circuit including a capacitor 39 and a resistor 40.

A collector of the transistor 37 is connected to the power supply terminal 16.

Terminal 19 is connected to the base of transistor 38 via a series circuit consisting of capacitor 41 and resistor 42, and this base is grounded via a parallel circuit consisting of capacitor 43 and resistor 44.

On the other hand, the terminal 35 is connected to an input terminal 46 of the horizontal oscillation circuit 5 via a low-pass filter 45 and is grounded via an integrating capacitor 47.

The terminal 48 to which the flyback pulse is supplied is connected to a resistor 49.
It is connected to the terminal 35 via.

Further, the terminal 46 is grounded via an integrating capacitor 50,
It is also connected to the power supply end 16 via an adjustment resistor 51 .

The base of the transistor 52 constituting the second switching circuit is connected to the terminal 48 via a resistor 53 and grounded via a resistor 54.

Further, the emitter of the transistor 38 is connected to the transistor 52.
The collector of the transistor 38 is connected to the power supply terminal 16 via a resistor 55, and the emitter of the transistor 52 is grounded.

Note that the portion indicated by the dotted line is the synchronization signal control circuit 56.

The operation of the horizontal oscillation frequency control circuit having the above configuration will be explained with reference to FIG.

In FIG. 4, when the video signal 3 is input, the horizontal synchronization signal 9 is input to the terminal 12, and during the horizontal synchronization period, the transistor 13 is on → the transistor 18 is on → the transistor 23 is off → the transistor 30 is on , the transistor 27 is turned on.

The detection voltage of the AFC circuit 4 at the terminal 35 during which the transistor 27 is turned on is equal to the clamp level V of the clamp circuit 32.
The voltage is approximately the same as o.

Then, during the horizontal synchronization period, the flyback pulse is applied to the resistor 4.
9 and a capacitor 47.

This integrated waveform becomes the AFC sawtooth wave voltage 10,
The signal is supplied to the output terminal 35 of the AFC circuit 4.

Therefore, this AFC
A sawtooth voltage 10 is superimposed.

Then, charging and discharging of the integrating capacitor 47 is controlled based on the clamp level Vo.

The voltage of the capacitor 47 is then applied to the low-pass filter 45.
AFC voltage is generated according to the phase difference between the two.

This AFC voltage is input to the horizontal oscillation circuit 5 and controls its oscillation frequency to be constant.

Next, the synchronization signal control circuit 56 will be explained separately for cases in which the horizontal synchronization signal 9 is present and cases in which it is not present.

When the horizontal synchronization signal 9 is present, the transistor 38 constituting the first switching circuit is turned on during the horizontal synchronization pulse period because the horizontal synchronization signal 9 is input to the base.

Further, a transistor 52 constituting the second switching circuit
Since a flyback pulse is input to the base, the transistor 52 is turned on during that period.

Since the synchronization pulse period is shorter than the flyback pulse period, both transistors 38.52
turns on at the same time.

As a result, the charge in the capacitor 39 constituting the integrating circuit is discharged, and the base voltage of the transistor 37 decreases.

Since the capacitor 39 is charged through the resistor 55 while at least one of the transistors 38 and 52 is off, a sawtooth wave voltage is generated at the base of the transistor 37.

If the average DC level of this sawtooth voltage is BL, then
At this time, transistor 37 is off.

Next, when there is no horizontal synchronization signal, the transistor 52 is turned on by the flyback pulse at the free oscillation frequency described above.

However, since the horizontal synchronization pulse is not input to the transistor 38, the transistor 38 maintains an off state.

Therefore, the base potential of the transistor 37 is approximately equal to the potential obtained by dividing the voltage at the power supply terminal 16 by the resistors 55 and 40.
Capacitor 39 remains charged to that potential.

Let this average DC level be V B H.

Now, the threshold level at which the transistor 37 turns on is VBO, and the resistor 55, capacitor 39, and resistor 40
The above-mentioned potential relationship between the value of the resistor 36 and the value of the resistor 36 is VBL
By setting <VBO<VBH, the transistor 37 can be turned on and off.

That is, when the horizontal synchronizing signal 9 is present, the transistor 3
7 is maintained in an off state, and the horizontal oscillation circuit 5 and AFC circuit 4 can operate normally.

Then, when there is no horizontal synchronization signal 9 (no signal),
Since the transistor 37 is turned on, the base potential of the transistor 13 is held at a predetermined level determined by the resistor 36.

As a result, even if the transistor 13 is turned on and the pseudo synchronization signal is input to the AFC circuit 4 or the like, an output at a constant level is obtained at the output terminal 35.

In other words, when there is no horizontal synchronizing signal 9, the AF'C circuit 4
The DC level of the detected voltage at the terminal 35 is always clamped to the clamp level ■○ of the clamp circuit 32, and the output of the horizontal oscillation circuit 5 oscillates at a constant frequency and a free oscillation frequency at a constant level.

The above is the operation of the synchronization signal control circuit 56 of the present invention.

In this way, when the video signal disappears, in the television receiver, by keeping the output voltage of the AFC circuit 4 constant, the DC level that determines the free oscillation frequency of the horizontal oscillation circuit 5 can be kept constant. I can do it.

Therefore, spurious signals due to switching effects such as rectification of the flyback pulse from the horizontal output circuit 6 are input to the antenna, etc., and the horizontal oscillation A is generated as a pseudo synchronization signal.
Even if it is supplied to the FC circuit, the detected voltage of the AF''C circuit 4 will not take an abnormal value, and an abnormally high voltage will not be generated due to a "4fH jump" in the horizontal oscillation frequency.

As described above, according to the present invention, a switch means is provided that conducts by the synchronization signal and the flyback pulse, and when the synchronization signal is not detected, the DC level of the detected voltage of the AFC circuit that controls the oscillation frequency is kept constant. can be maintained, and does not cause abnormal oscillation like conventional
This has the effect of not generating abnormally high pressure.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the horizontal oscillation AFC circuit, Figure 2 is a waveform diagram showing the horizontal synchronization signal and AFC sawtooth wave, and Figure 3 is a waveform diagram showing the horizontal sync signal and AFC sawtooth wave.
The figure is a waveform diagram showing a pseudo synchronization signal and a free AFC sawtooth wave, and FIG. 4 is a circuit diagram showing a horizontal oscillation frequency control circuit according to the present invention. 37.38.52...Transistor, 36,4
0, 42.44. 53.55・・・Resistance, 3
9,43.41... Capacitor, 56...
...Synchronization signal control circuit.

Claims (1)

[Claims for Utility Model Registration] A circuit that has a first transistor that performs a switching operation in response to a synchronization signal separated from a video signal and generates a constant output voltage during the switching period, and a circuit that integrates a flyback pulse. The sawtooth wave signal obtained by the above output voltage is superimposed on the output voltage, the integration capacitor is controlled to charge and discharge based on the output voltage, and the charging and discharging voltage is smoothed to obtain A.
A means for generating an FC voltage, a first switching means that performs a switching operation when the synchronization signal is at a normal level, and a second switching means that performs a switching operation during the flyback pulse are connected between a voltage source and a reference potential point. It has a series circuit connected in series, and a capacitor charged by the voltage from the voltage source, and when the first and second switching means switch simultaneously, the charge of the capacitor is transferred through the series circuit. an integrating circuit for discharging; and a third switch means that performs a switching operation when the output voltage of the integrating circuit exceeds a predetermined level.
a horizontal oscillation frequency control circuit comprising means for causing the first transistor to perform a switching operation even in the absence of a synchronization signal in accordance with the switching operation of the switching means.