JPH05153432A - Clamp circuit - Google Patents

Abstract

PURPOSE:To clamp an input MUSE base band signal at an accurate level at all times. CONSTITUTION:A switch circuit 28 gives an input signal to the clamp circuit 12 when a MUSE base band signal in the state of out of synchronism is inputted. A maximum value detection circuit 18 and a minimum value detection circuit 20 detect the maximum value and the minimum value of the input signal and a center value detection circuit 22 detects a center level based on them. A clamp level of the clamp circuit 12 is set equal to the center level to clamp the input signal. When the input signal is in the synchronization state, the input signal is given to a clamp circuit 14, in which the usual clamping is implemented. Thus, a delay in synchronization locking at out of synchronism is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp device, and more particularly to a clamp device used in, for example, a MUSE television signal receiver.

[0002]

2. Description of the Related Art TEBF95 Technical Report of the Television Society
-2 "Satellite 1 channel transmission system for high definition television (MU
SE) ”, a system for transmitting a high-definition television signal having a wideband image signal by one channel of satellite broadcasting has been proposed by the Japan Broadcasting Corporation as a MUSE system.

This MUSE signal is positive polarity synchronized, that is,
Since the sync signal is included in the video amplitude, it is not possible to separate the sync in the amplitude direction. Therefore, the frame synchronization signal inserted in the vertical blanking period as shown in FIG. 7 is extracted by utilizing the correlation between the scanning lines, and then the horizontal synchronization signal is extracted and the phase synchronization oscillation of the input television signal and the receiver is extracted. It is in phase synchronization with the circuit.

Further, since the sync separation, the phase synchronization, and various other signal processing are digitally performed, it is necessary to convert the MUSE signal into an analog / digital signal. And
When the MUSE signal is input to the A / D converter, it is necessary to clamp the DC potential so as to fix it accurately. One method for performing this clamping is to use the clamp level information (line numbers 563 and 1125) in the MUSE signal transmission format shown in FIG. 8 and use the flat portion A of the horizontal synchronization signal shown in FIG. 9 and Table 1 or the horizontal synchronization signal. It is conceivable to perform at clamp level B following the signal.

[0005]

[Table 1]

However, frame synchronization must be established to extract the clamp level information. Further, since the clamp pulse is generated by the above-mentioned phase locked oscillator circuit, horizontal synchronization must be established. If either of these is not established, it will clamp where it is not in the proper position. For this reason,
The DC potential of the video Y signal may fluctuate, causing a malfunction in synchronization separation, and delaying the synchronization pull-in.

As a means for solving this problem, Showa 62
Japanese Patent Application Laid-Open No. 62-6977 filed March 31, 2016
No. 8 and Japanese Patent Application Laid-Open No. 62-173859 filed on July 30, 1987, when the phase-locked oscillator circuit is out of phase synchronization, the clamp circuit is set to the average value clamp system or A method of switching to the peak clamp method has been proposed.

[0008]

However, in the case of the average value clamp method, the clamp level may fluctuate due to the DC component of the video Y signal, and the sync separation circuit may malfunction. Also, in the case of the peak clamp method, the clamp level may fluctuate due to the distortion of the transmission path or the waveform distortion at the signal source, especially due to the rapid DC component fluctuation of the video tape recorder or video disc player, which may cause the sync separation circuit to malfunction. There is.

For example, when a normal MUSE baseband signal is input as shown in FIG. 10A, the average clamp level varies depending on the DC component of the video Y signal in the average clamp method. In this case, there is no influence on the detection of the vertical synchronization signal, but it is affected on the detection of the horizontal synchronization signal and the horizontal phase synchronization, and it takes time to establish the horizontal synchronization. On the other hand, in the peak clamp method, the maximum value of the input signal is detected, and a fixed amount (V
_A ) There is no problem because the lowered potential is input to the analog / digital converter as the center value of the input signal.

However, when a MUSE baseband signal having a waveform distortion as shown in FIG. 10B is input, the peak clamp method detects the maximum value of the distortion waveform, so that the phase locked loop circuit of the phase locked loop circuit is detected. It will cause malfunction. Further, the DC component that is rapidly changing as seen in a video disc player as shown in FIG.
Even when the USE baseband signal is input, in the peak clamp method, as in the case shown in FIG.
The phase lock circuit malfunctions.

Therefore, the main object of the present invention is to provide a clamping device which always provides an accurate clamping level.

[0012]

According to the present invention, there is provided a first clamp circuit for clamping an input positive polarity synchronous television signal containing clamp information of a constant cycle at a predetermined level, and an input positive polarity synchronous television signal having an upper peak value thereof. A second clamp circuit that clamps at a center value between the lower peak value and
The clamp device further includes a selection unit that selectively activates the first clamp circuit or the second clamp circuit according to the synchronization determination signal.

[0013]

When in the synchronized state, the selecting means activates the first clamp circuit. However, in the out-of-phase condition, the selection means activates the second clamp circuit. Second
The clamp circuit clamps the center value between the upper peak value and the lower peak value of the positive sync television signal such as the MUSE baseband signal as a clamp level. For example, when there is a sudden change in the DC component, the center value also rises due to the rise of the upper peak value. However, since the lower peak value decreases as the center value increases, the center value is immediately restored to the normal value. As a result, an accurate clamp level can always be obtained even for a positive-polarity synchronous television signal such as a MUSE baseband signal having distortion or a sudden change in direct current component.

[0014]

According to the present invention, an accurate clamp level can always be obtained even with respect to an input signal having distortion or a sudden change in DC component, so that the synchronization pull-in due to a malfunction of the clamp in the phase out-of-phase state. You can prevent delays. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a clamp device 10 of this embodiment includes clamp circuits 12 and 14. And
The clamp device 10 has, for example, an MU from the input terminal 16.
SE baseband signal is input. The MUSE baseband signal is selectively input to the clamp circuit 12 or 14 by the switch circuit 28, and the maximum value detection circuit 18 that detects the upper peak of the input signal and the minimum value that detects the lower peak of the input signal. It is input to the detection circuit 20.

The maximum value detection circuit 18 and the minimum value detection circuit 20 output the maximum value V _max and the minimum value V _min, respectively. The maximum value V _max and the minimum value V
_min is input to the center value detection circuit 22, and the center value detection circuit 22 detects and outputs the center value V _cent of the maximum value V _max and the minimum value V _min . Center value center value V _cent output from the detection circuit 22 is smoothed by the smoothing circuit 24 is input to the clamp circuit 12 as the average center value V _{ce nt / av.} In this clamp circuit 12 that operates as the second clamp circuit, V _{cent / av} is compared with the reference clamp level N input from the terminal 26, and the clamp operation is performed.

A clamp level signal and a clamp timing signal are input from terminals 30 and 32 to the clamp circuit 14 which operates as the first clamp circuit, and the clamp circuit 14 performs the clamp operation with respect to the input MUSE baseband signal. Is done. As described above, the input MUSE baseband signal is transmitted to the switch circuit 28.
And is applied to the clamp circuit 12 or 14. That is, in accordance with the synchronization determination signal input from the terminal 34, the clamp circuit 14 is activated in the phase locked state and the clamp circuit 12 is activated in the phase locked state.

Such a clamp device 10 is constructed, for example, as shown in FIG. Therefore, the operation of this embodiment will be described in detail with reference to FIG. When in the synchronized state, the switch circuit 28 is connected to the input end 28b side by the synchronization determination signal input from the input terminal 34. Therefore, the input MUSE baseband signal is clamped by the resistor R1 and the capacitor C1 according to the clamp level signal input from the terminal 30 and the clamp timing signal input from the terminal 32. That is, the normal clamp operation is performed.

Then, in the out-of-synchronization state, the switch circuit 28 is connected to the input terminal 28a side, and the MUSE baseband signal passes through the capacitor C1 and the maximum value detecting circuit 16 composed of the transistor Q1, the resistor R2 and the capacitor C2. To the base of the transistor Q1, and to the input of the minimum value detection circuit 18 including the transistor Q2, the resistor R3 and the capacitor C3, that is, the base of the transistor Q2.

The maximum value detection circuit 16 outputs the maximum value V _max , which is output via the buffer constituted by the transistor Q3 and the resistor R4. The minimum value detection circuit 18 outputs the minimum value V _min , which is output via the buffer formed by the transistor Q4 and the resistor R5. The maximum value V _max and the minimum value V _min are added by resistors R6 and R7. When the resistances of the resistors R6 and R7 are equal, a center value V _cent between the maximum value V _max and the minimum value V _min appears at the terminal 36. The center value V _cent is smoothed by the resistors R6 and R7 and the capacitor C4. Transistors Q5 to Q13 and resistors R8 to R14
The differential circuit constituted by (1) compares the average center value V _{cent / av} with the reference clamp level signal N input from the terminal 26 and _sets both to the same potential. Therefore, the input MUSE baseband signal is clamped by resistor R15 and capacitor C1.

The constant voltage source V ₁ is a bias of a constant current source composed of a transistor Q7 and a resistor R8, and the current value of this constant current source is controlled by a synchronization judgment signal, and is replaced by a switch circuit 28. Good. (A ') shown in FIG. 3 shows the case where a MUSE baseband signal subjected to waveform distortion is input. In this case, since the maximum value and the minimum value of the distortion waveform are detected, the detected center The value substantially matches the center potential of the input MUSE baseband signal.

Further, (b ') shown in FIG. 3 shows a case where a MUSE baseband signal whose DC component is abruptly changed, which is seen in a video disc player or the like, is input, and in this case, the maximum value is It changes according to the fluctuation of the DC component as in the conventional case. Along with this, the center value increases by 1/2 of the maximum value, and the MUS input by it increases.
The level of the E baseband signal drops by that amount,
The minimum value of the MUSE baseband signal lowered by the minimum value detecting operation is detected. Therefore, compared to the conventional
Remarkably quickly returns to the normal center value. Therefore,
An accurate clamp level can be output almost always.

Next, referring to FIG. 4, a clamp device 40 of another embodiment has a maximum value detection / smoothing circuit 42 that also performs maximum value detection and smoothing, and a minimum value detection and smoothing function. A minimum value detection / smoothing circuit 44 is included. This maximum value detection /
In the smoothing circuit 42 and the minimum value detection / smoothing circuit 44, the time constant for peak detection is also used as the time constant for smoothing. Therefore, the resistance R2 in FIG.
And the time constants of the capacitor C2, the resistor R3, and the capacitor C3 are the resistors R6, R7, and the capacitor C4.
The clamp device shown in FIG. 4 can be realized if the clamp device is designed to have the same time constant as. In addition, in FIG. 4, maximum value detection /
The configurations of the smoothing circuit 42 and the minimum value detection / smoothing circuit 44 subsequent to the smoothing circuit are the same as those of the clamp device 10 shown in FIG. 1, and therefore the description thereof is omitted here.

In the above embodiment, the switch circuit 2
8, the input MUSE baseband signal is switched and input to the clamp circuit 14 or 12 depending on whether it is in the synchronized state or out of synchronization. However,
The embodiments shown in FIGS. 5 and 6 may be used to selectively activate the clamp circuit 14 or 12 in response to the synchronization determination signal.

In the embodiment of FIG. 5 which is a modification of the embodiment of FIG. 1 or the embodiment of FIG. 6 which is a modification of the embodiment of FIG. 4, the input MUSE baseband signal is applied to clamp circuits 12 and 14. The switch circuit 28 selects the output of the clamp circuit 12 or 14 in accordance with the synchronization determination signal. In this way, either output may be selected, and as a result, the clamp circuit 14 or 12 may be selectively activated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the embodiment of FIG. 1 in detail.

FIG. 3 is a waveform diagram showing the operation of the center value detection circuit of the embodiment of FIG.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a waveform diagram showing a frame synchronization signal.

FIG. 8 is an illustrative view showing a MUSE signal transmission format.

FIG. 9 is a waveform diagram showing a horizontal synchronizing signal and a clamp position.

FIG. 10 is a waveform diagram showing each operation in the conventional clamp device.

[Explanation of symbols]

 10, 40 ... Clamping device 12, 14 ... Clamping circuit 18 ... Maximum value detecting circuit 20 ... Minimum value detecting circuit 22 ... Center value detecting circuit 28 ... Switch circuit 42 ... Maximum value detecting / smoothing circuit 44 ... Minimum value detecting / smoothing Circuit

Claims (1)

[Claims] 1. A first clamp circuit for clamping an input positive-polarity synchronized television signal containing clamp information of a fixed cycle at a predetermined level, wherein the input positive-polarity synchronized television signal is between its upper peak value and lower peak value. Second clamp with the center value of
A clamp device comprising: a clamp circuit; and a selection unit that selectively activates the first clamp circuit or the second clamp circuit according to a synchronization determination signal.