JP3547970B2 - Sync separation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a synchronization separation circuit that separates a horizontal synchronization signal from a video signal used in a television receiver, a video tape recorder, and the like, and particularly to a synchronization separation circuit that is not easily affected by noise and can stably separate synchronization. .
[0002]
[Prior art]
2. Description of the Related Art A sync separation circuit that separates a horizontal sync signal from a video signal used in a television receiver, a video tape recorder, or the like is known.
As the sync separation circuit, for example, the one shown in FIG. 2 can be considered.
A video signal is applied to the input terminal 1 in FIG. In the applied video signal, the sync tip (the leading end of the horizontal synchronizing signal) is clamped by the sync tip clamp circuit 2. The clamp voltage at this time becomes the reference voltage Vref1, which is the voltage of the reference voltage source 3.
[0003]
The clamped video signal is applied to the buffer 5 after the noise component is removed by the LPF 4. The video signal that has passed through the buffer 5 is compared in level with a reference voltage Vref2 by a comparator 6. The reference voltage Vref2 is superimposed on the reference voltage Vref1 and applied to the comparator 6.
As a result of the comparison by the comparator 6, a horizontal synchronizing signal synchronized with the output terminal 7 is obtained.
[0004]
[Problems to be solved by the invention]
However, in the method of FIG. 2, when the magnitude of the video signal applied to the input terminal 1 changes, the slicing position changes because the level for slicing the horizontal synchronization signal is fixed. If the slicing position changes, synchronous separation cannot be performed stably. In extreme cases, synchronization separation itself cannot be performed.
[0005]
This is shown in FIG. It is assumed that the slicing level approaches the leading end of the horizontal synchronization signal as indicated by a dotted line a in FIG. Then, erroneous determination is likely to occur due to the influence of noise that tends to occur at the tip. Conversely, it is assumed that the level to be sliced approaches the pedestal level as shown by a dotted line b in FIG. Then, as shown in the figure, it is affected by the video signal, and in this case, it is easy to make an erroneous determination.
[0006]
[Means for Solving the Problems]
The present invention has been made in view of the above points, and has a sync tip clamp circuit for clamping a sync tip level of a video signal to a reference voltage Vref, and a video signal clamped by the sync tip clamp circuit being supplied to one input terminal. A differential amplifier that is applied and operates only during a burst gate pulse period of a pedestal period, a capacitor that is charged according to an output signal of the differential amplifier, and an output voltage of the capacitor is fed back to the other input terminal of the differential amplifier. And a holding circuit for holding a pedestal level, including a feedback unit for performing the above operation, an amplifier for amplifying the video signal clamped by the sync tip clamp circuit, A horizontal synchronizing signal is derived from the comparator.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a sync separation circuit of the present invention.
10 is a sync tip clamp circuit for clamping the sync tip level of the video signal to the reference voltage Vref, 11 is a holding circuit for holding the pedestal level of the video signal clamped by the sync tip clamp circuit 10, and 12 is the sync tip clamp circuit A differential amplifier to which the video signal clamped at 10 and the reference voltage Vref are applied, 13 is a comparator for comparing the level of the output video signal of the differential amplifier 12 with the output voltage of the holding circuit, 14 is an LPF, 15 Is a buffer, and 16 is a reference voltage source.
[0008]
A video signal is applied to the input terminal 17. In the applied video signal, the sync tip (the leading end of the horizontal synchronization signal) is clamped by the sync tip clamp circuit 10. The clamp voltage at this time becomes the reference voltage Vref which is the voltage of the reference voltage source 16.
This is shown in the video signal A of FIG.
[0009]
The clamped video signal is applied to the buffer 15 after the noise component is removed by the LPF 14. The video signal passing through the buffer 15 is amplified by the differential amplifier 12 based on the reference voltage Vref.
This is shown in the video signal B of FIG. When the gain of the differential amplifier 12 in FIG. 1 is set to double, the waveform becomes as shown in FIG. 4B. That is, the amplitude is doubled while the level of the sync chip is kept at the reference voltage Vref.
[0010]
Therefore, in the present invention, the pedestal level of the video signal A shown in FIG. 4 is detected and used as the slice level so that the slice level comes to the center of the doubled horizontal synchronization signal. As a result, the horizontal synchronization signal can be separated at the optimum level.
In the present embodiment, the gain of the differential amplifier 12 is set to twice, but may be increased or decreased within an allowable range.
[0011]
In order to detect the pedestal level of the video signal A in FIG. 4, a holding circuit 11 that operates as an S / H circuit (sample and hold) is used. The holding circuit 11 applies S / H to the pedestal level in the video signal passed through the buffer 15 and applies the S / H to the comparator 13.
As a result, the comparator 13 can slice the horizontal synchronizing signal of the video signal B in FIG.
[0012]
FIG. 5 shows a specific circuit diagram of the holding circuit 11 of FIG. The video signal from the buffer 15 is applied to one input terminal 21 of the differential amplifier 20. The output signal of the differential amplifier 20 is led to the point A by the current mirror circuits 22, 23, 24. The capacitor 25 is charged and discharged by the current at the point A.
The voltage of the capacitor 25 is fed back to the base of the transistor 29 of the differential amplifier 20 via the transistors 26, 27 and 28. With this feedback, the base voltage of the transistor 29 follows the voltage of the input terminal 21.
[0013]
The operating current source 30 of the differential amplifier 20 operates when a BGP (burst gate pulse) is applied from the terminal 31, and does not flow current during other periods.
Therefore, the voltage of the input video signal during the BGP period, that is, the pedestal voltage is obtained at the output terminal 32. In FIG. 5, BGP is used as a pulse for detecting the pedestal period, but any pulse may be used as long as it is a pulse generated during the pedestal period.
[0014]
【The invention's effect】
As described above, according to the present invention, a sync tip clamp circuit for clamping a sync tip level of a video signal to a reference voltage Vref, a holding circuit for holding a pedestal level of a video signal clamped by the sync tip clamp circuit, An amplifier that amplifies the video signal clamped by the sync tip clamp circuit is provided, and the level comparison between the output video signal of the amplifier and the output voltage of the holding circuit is performed. The level comes to come. If the slicing position is fixed, synchronous separation can be performed stably regardless of the amplitude of the video signal.
[0015]
Further, according to the present invention, the pedestal level can be stably detected with a simple circuit, so that reliable synchronization separation can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a sync separation circuit of the present invention.
FIG. 2 is a block diagram showing a conventional sync separation circuit.
FIG. 3 is a waveform chart for explaining the conventional operation.
FIG. 4 is a waveform chart for explaining the operation of the present invention.
FIG. 5 is a specific circuit diagram of the holding circuit 11 of the present invention.
[Explanation of symbols]
(10) Sync tip clamp circuit (11) Holding circuit (12) Differential amplifier (13) Comparator (20) Differential amplifier (25) Capacitor

Claims (2)

A sync tip clamp circuit for clamping a sync tip level of a video signal to a reference voltage Vref;
A differential amplifier in which a video signal clamped by the sync tip clamp circuit is applied to one input terminal and operates only during a burst gate pulse period of a pedestal period , and a capacitor charged in accordance with an output signal of the differential amplifier, A holding circuit for holding a pedestal level including feedback means for feeding back the output voltage of the capacitor to the other input terminal of the differential amplifier;
An amplifier for amplifying the video signal clamped by the sync tip clamp circuit;
A synchronization separation circuit comprising: a comparator for comparing a level of an output video signal of the amplifier with an output voltage of the holding circuit to derive a horizontal synchronization signal from the comparator. A sync tip clamp circuit for clamping a sync tip level of a video signal to a reference voltage Vref;
A differential amplifier in which a video signal clamped by the sync tip clamp circuit is applied to one input terminal and operates only during a burst gate pulse period of a pedestal period , and a capacitor charged in accordance with an output signal of the differential amplifier, A holding circuit for holding a pedestal level including feedback means for feeding back the output voltage of the capacitor to the other input terminal of the differential amplifier;
An amplifier for amplifying the video signal clamped by the sync tip clamp circuit using a reference voltage Vref;
A synchronization separation circuit comprising: a comparator for comparing a level of an output video signal of the amplifier with an output voltage of the holding circuit to derive a horizontal synchronization signal from the comparator.

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