JPS63244977A - Synchronizing signal separating circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction in synchronizing and separating operation due to a flutter or the like by extending a synchronizing signal according to the fluctuation in the direct current level of a video signal. CONSTITUTION:An input video signal is applied to an output circuit 50, a pedestal level sampling circuit 100 and an AFC circuit 110. The fluctuation in the direct current level of the video signal is detected by a level fluctuation detecting means 90. The base of the transistor 27 of a clamp circuit 80 is biassed by the output of the level fluctuation detecting means 90, the level clamped by the clamp circuit 80 is changed according to the output of the level fluctuation detecting circuit 90 and the synchronizing signal part is extended according to the direct current level of the video signal. The video signal in which the synchronizing signal part is extended is applied to a slice circuit 130 and the synchronizing signal is separated.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a synchronization separation circuit for video signals, particularly when the DC level of the video signal fluctuates at low frequencies due to fluttering or the like. The present invention relates to a synchronization signal separation circuit that can stably separate synchronization signals even when the synchronization signal is used.

(Prior Art) Generally, when separating a synchronization signal from a video signal, the pedestal levels are once aligned, slice processing is performed at a predetermined level, and then synchronization separation is performed.

If the synchronization separation is not performed accurately, the horizontal synchronization or vertical synchronization will be disturbed and a normal reproduced video signal will not be obtained.

By utilizing this fact, for example, it is possible to perform DC offset processing on the horizontal synchronizing signal at random or at all timings, and to perform scrambling processing on the transmitted video signal.

However, when descramble processing is performed in a scrambling system that randomly performs DC offset processing on the horizontal synchronization signal and scrambles the video signal, the de-tempered signal may be reversed due to distortion in the transmission system. The synchronization signal obtained through offset processing and the synchronization signal obtained without such processing differ in the synchronization signal tip level obtained with the pedestal level as a reference.

That is, as shown in Fig. 3, even though the pedestal level of the horizontal synchronization signal A reproduced by reverse offset processing and the horizontal synchronization signal N obtained without offset processing match, the synchronization signal tip level has a different level. A deviation occurs by a. The descrambled video signal obtained in this way is subjected to clamp processing at the synchronization signal leading edge level, and RF modulation is performed.
When a video is played back on a general television receiver, the pedestal level fluctuates due to the level deviation described above. For this reason, the AGC operation for obtaining a reproduced image, for example, the keyed AGC operation, malfunctions due to the above-mentioned level deviation a, and as a result, the brightness changes for each horizontal line and appears as horizontal stripe noise.

This noise is caused by the low frequency of the pedestal level,
Occurs when accompanied by DC fluctuations.

In addition to the case shown in FIG. 3, such noise is also induced when a significant sag occurs in the synchronization signal portion of the descrambled signal, as shown in FIG.

In order to reduce horizontal stripe noise in such reproduced images,
It is conceivable to expand the sync signal once the pedestal levels of the sync signal are aligned, and then slice the sync signal portion at a predetermined level.

An example of processing the synchronization signal in this way is shown in FIG.

A video signal VA of positive polarity is applied to the input terminal IN in FIG. 5, and at this stage, the leading edge levels of the synchronization signals are uneven.

The resistors 1 and 2 and the transistor constitute an inverting amplifier, which inverts and amplifies the video signal inputted to the input terminal IN. An emitter-follower type transistor 2 is connected to the collector side of this amplifier, and a video output signal VB is obtained at an output terminal OUT provided to an emitter-follower resistor 13.

Further, the collector of the amplifier 3 and the transistor 12
A resistor 4 and a collector/emitter current path of a transistor 5 are connected between the base connection point and the reference potential, and the base of the transistor 5 is connected to the power supply terminal V. Of the resistors 6, 7, and 8.9 connected in series between the reference potential and the reference potential, the resistor 6 is connected to the connection point of the resistors 6 and 7.

Note that the connection point between the resistor 7 and the resistor 8 is connected to a reference potential via a capacitor 14.

Furthermore, a transistor 0 is provided, the base of which is connected to the connection point between the resistors 7 and 8, the collector of which is connected to the power supply terminal V, and the emitter of which is connected to the output terminal.

To explain the circuit operation in a conventional synchronizing signal separation circuit having such a circuit configuration, the video signal VA inputted to the input terminal IN is inverted and amplified by the amplifier 3, and the video signal VA is inverted and amplified by the amplifier 3.
is output to. At this time, transistor 5 is 0 to 20IR
It conducts at a brightness level of about E. That is, in the sync signal portion, when the level of the sync signal is less than 201RE, the transistor 5 becomes conductive.

In this way, when the leading edge level of the synchronizing signal is less than about 201RE, the transistor 5 becomes conductive, and the output terminal OU
T is the connection point of the resistors 7 and 8 above, and the potential is from ■ to vF (
The voltage (VP-VF) obtained by subtracting the base and emitter voltages of transistor o appears.

That is, during the period when the transistor 5 is conductive, the voltage level of the output terminal OUT (V, -VF) is lower than the potential of the synchronizing signal about 201RE, so the transistor 12 is in the off state. becomes.

As a result, when the synchronization signal is less than about 20 IRE, the transistor 5 becomes conductive and the voltage (V −
V, )l: A signal clamped and expanded to about -40 IRE is obtained at the output terminal OUT.

From the video signal whose leading edge level of the synchronization signal obtained at the output terminal OUT is adjusted to a predetermined level or higher, the synchronization signal is separated by slicing it at a predetermined level by a next-stage slicing circuit (not shown).

(Problem to be Solved by the Invention) In the conventional synchronous separation circuit described above, when flutter or the like occurs and the DC level changes at low frequency as shown in FIG. 6, it slices at the slice level Vs. When synchronously separating, even the picture signal may be sliced.

For this reason, there is a problem in that the picture may be damaged during the synchronization separation operation, and the reproduced image may deteriorate.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a synchronization separation circuit that can reduce malfunctions in the synchronization separation operation even if flutter or the like occurs in a video signal.

[Structure of the Invention] (Means for Solving the Problem) In the present invention, fluctuations in the DC level due to flutter of the video signal, etc. are detected by the level fluctuation detection means 90° 100, and the leading edge of the synchronizing signal is The synchronization signal is expanded when the level is less than a predetermined level. Thereafter, the synchronization signal is separated by slicing at a predetermined level, thereby preventing the picture signal from being damaged when the synchronization signal is separated.

As a result, a synchronization signal separation circuit capable of stably separating the synchronization signal in the video signal is obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a synchronous separation circuit according to the present invention.

In FIG. 1, a video signal input to an input terminal IN is applied to an amplifier 50. This amplifier 50 includes transistors 16, 17 . It is composed of resistors 14, 15, 18, 19, and outputs a signal with the same polarity as the input video signal.

The output of this amplifier 50 is the emitter follower type transistor 28. It is added to an output circuit 60 made up of a resistor 29.

Further, on the output side of the amplifier 50, a switching transistor 21. A switch circuit 70 is provided to selectively connect the output terminal of the amplifier 50 to a reference potential via the resistor 21.

Further, a clamp circuit 80 is provided which clamps the output level of the output circuit 50 to a predetermined fluctuating potential in response to the switch operation of the switch circuit 70. It is biased by a point potential, and its emitter is commonly connected to the transistor 28.

A resistor 26 is connected between the resistor 25 and the reference potential, a capacitor 24 is connected between the connection point of the resistors 23 and 25 and the reference potential, and the resistor 22 connected to the resistor 23 will be described later. It is connected to the output terminal of the level fluctuation detection means 90.

This level fluctuation detection means 90 is configured to receive an output from a pedestal level sampling means 100 that samples and holds the pedestal level of the video signal input to the input terminal IN.

This pedestal level sampling means 100 is controlled by a timing signal obtained by a timing generation circuit 120 using the output of an AFC circuit 110 that generates a timing signal synchronized with a horizontal synchronization signal that follows a synchronization signal in a video signal. .

Next, FIG. 2 shows the operation of the circuit shown in FIG. 1 above. This will be explained with reference to operation waveform diagrams. Assume now that a video signal exhibiting flutter as shown in FIG. 2(a) is input to the input terminal IN in FIG. 1.

This input video signal is transmitted to the output circuit 50. Pedestal level sampling circuit 100. and added to the AFC circuit 110.

The AFC circuit 110 outputs a timing signal synchronized with the separated horizontal synchronization signal, and the timing generation circuit 12
0 generates the timing pulse (FIG. 2(b)) necessary to sample the pedestal level.

The pedestal level sampling circuit 100 switches the switch 31 in response to the timing pulse (FIG. 2(b)).
The pedestal level is sampled to the capacitor 32 by driving the pedestal level. This sample voltage is op amp 33
After being amplified, the signal is applied to the level fluctuation detection means 90 via the capacitor 34.

The negative phase input terminal of this level fluctuation detection circuit 90 is connected to a power supply terminal V. A voltage dividing point potential VR of a resistor 35.37 interposed between and a reference potential is applied, and the output of the pedestal level sampling circuit 100 is applied to the positive phase input terminal. Therefore, the operational amplifier 39 outputs a voltage corresponding to the level difference between the potential VR and the output of the pedestal level sampling circuit 100. The voltage gain at this time is related to the resistors 36 and 40.41. As a result, it is applied to the base of the transistor 27 constituting the clamp circuit 80. That is, the base potential Vc of the transistor 27 exhibits the level fluctuation shown in FIG. 2(C).

On the other hand, the video signal VA applied to the input terminal IN is amplified by the amplifier 50 and then applied to the output circuit 60, but if the level of the tip of the synchronizing signal is less than about 20 IRE, the switch circuit 70 transistor 21
starts conducting.

At this time, as described above, the base of the transistor 27 of the clamp circuit 80 is biased by the output of the level fluctuation detection circuit 90, so when the switch circuit 70 switches and the transistor 21 becomes conductive, the clamp circuit 80 The level clamped by changes depending on the output of the level fluctuation detection circuit 90.

In other words, the sync signal portion which is less than about 201RE based on the output potential accompanied by the level variation detected by the level variation detection circuit 90 is expanded to about 401RE by the clamp circuit 80.

Further, in this case, since the clamp voltage itself corresponds to the amount of level fluctuation detected by the level fluctuation detection circuit 90, the amount of synchronization signal expansion also follows this.

As a result, when the transistor 21 of the switch circuit 70 becomes conductive, the output circuit receives a synchronization signal expanded in accordance with the amount of fluctuation detected by the level fluctuation detection circuit 90, and the transistor 21 is cut off. When the synchronizing signal is output from the amplifier 50, the synchronizing signal obtained is output as is.

The video signal V thus obtained at the output terminal of the output circuit 60 is sliced at a predetermined level by the next stage slicing circuit 130, thereby obtaining a synchronization signal at the output terminal OUT.

Note that the amount of expansion of the synchronization signal described above can be changed by an appropriate amount by adjusting the variable resistor 41 of the level fluctuation detection circuit 90. The amount of expansion can also be controlled by controlling the resistance value of the resistor 22.

Furthermore, the synchronization signal obtained at the output terminal OUT is the AFC
In addition to the circuit 110, the AFC circuit 110 performs a complementary operation when the synchronization signal cannot be separated by the AFC circuit 110.
It is also possible to stabilize the FC operation.

(Effects of the Invention) As described above, according to the synchronization separation circuit according to the present invention, even if flutter or the like occurs in the video signal, the synchronization signal can be stably separated, and it is possible to stably separate the synchronization signal only for normal video signals. Instead, it is possible to provide a synchronization signal separation circuit that can be applied to a video signal in which the synchronization signal is sysclampled by offset processing.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a synchronization signal separation circuit according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG.
This figure is a circuit diagram showing a conventional synchronizing signal separation circuit, and FIGS. 3, 4, and 6 are waveform diagrams for explaining the operation of the circuit shown in FIG. 5. 50...Amplification circuit, 60...Output circuit. 70... Switch circuit, 80... Clamp circuit. 90.100...Level fluctuation detection means. 130...Slice circuit.

Claims (1)

[Claims] An amplifier circuit that receives an input video signal and amplifies it with a predetermined gain; an output circuit that includes an emitter follower transistor that receives the output of the amplifier circuit; and an output of the output circuit. A slicing circuit that slices the signal at a predetermined level and separates the synchronization signal; a level fluctuation detection means that detects a change in the synchronization signal level in the input video signal; a clamp circuit in which the base bias voltage is controlled, the emitters of the emitter follower transistors of the output circuit are commonly connected, and the synchronization signal is extended in accordance with the amount of level fluctuation detected by the level fluctuation detection means; synchronization by the clamp circuit; A synchronous signal separation circuit comprising at least a switch circuit that blocks the output of the amplifier circuit from being applied to the output circuit during a signal expansion operation.