JPH06150685A - Sample-hold circuit - Google Patents

Abstract

PURPOSE:To reduce the deviation of a clamp by stopping the operation of an input buffer amplifier, activating a feed-through clamping circuit so as to make a feed back even at the time other than an optical black period in an image output signal. CONSTITUTION:In the period of a feed back clamping(FBC), operations of buffer amplifiers 4, 14 are interrupted by a FBC operation signal inputting from an input terminal 28. Then, signals from input terminals 22, 23 are not impressed to condense 5, 15 arranged for the feed-through, switches 6, 16 are closed, samplings are performed by switches 8, 18. Thus, output signals of output terminals 24, 25 have not alternate signal-s from a CCD image sensor 30, but have only direct current potentials and comparated by a comparator 33 to be outputted. Thus, the deviation of the clamp is reduced since the FBC is performed in the vacant transfering term other than the optical black period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit for reducing low frequency 1 / f noise and reset pulse noise of an image signal obtained by a CCD image sensor.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional sample and hold circuit corresponding to a CCD image sensor constructed by connecting a feed through clamp circuit and a video signal sample and hold circuit in series.

As shown in FIG. 4, a sample-and-hold circuit 41 of a conventional example includes a CCD image sensor 70, a capacitor 71, a comparator 73, and a differential amplifier 7.
A sample holder 42 including buffer amplifiers 44 and 47, a capacitor 45 for feedthrough clamp, a capacitor 49 for sample hold, a switch 46 for feedthrough clamp, and a switch 48 for sample hold corresponding to 2 and a buffer. Amplifiers 54 and 57, capacitor 55 for feedthrough, capacitor 59 for sample hold, switch 5 for feedthrough clamp
6, a sample holder 43 including a switch 58 for sample and hold, a feedthrough clamp reference voltage source 61, and a feedback clamp control voltage source 60.
And terminals 62 to 66.

FIG. 3 shows the CCD shown in FIG.
FIG. 6 is an operation waveform diagram of an image output signal output from the image sensor 70.

The image output signal for each pixel output from the CCD image sensor 70 is, as shown in FIG.
A reset noise period t1 and a feedthrough period t, which are generated when a reset pulse given to clear the charge of the previous pixel is leaked to the output during charge transfer in the CCD.
It is divided into 2 periods and 3 periods of the video signal period t3,
The signal required as the level of the video signal is the difference voltage A between the voltage during the feedthrough period t2 and the voltage during the video signal period t3.
Can be expressed as Of these, the reset noise has nothing to do with the video signal level, and when the video signal level is low, the signal is buried in the reset noise and the S / N ratio deteriorates.

Further, the low frequency 1 / f noise is usually superimposed on the image output signal output from the CCD image sensor 70. If this low frequency 1 / f noise is not removed, the image Since the brightness changes, the image quality deteriorates.

These reset noise and low frequency 1 / f
To remove noise, a sample and hold circuit 41 for the CCD image sensor output signal shown in FIG. 4 has been proposed.

An image output signal from the CCD image sensor 70 input from the input terminal 62 is input to the sample holder 42 and is fed through the buffer amplifier 44 in the sample holder 42 to the feedthrough clamp capacitor 45 and the feed. With the through-clamp switch 46, the voltage of the image input signal during the feed-through period t2 is clamped pixel by pixel through the feed-through culling function of adjusting the clamp reference voltage VR.
Low frequency 1 / f noise is removed. Here, the clamp reference voltage VR is a voltage set by the feedthrough clamp control voltage source 61.

Next, the buffer amplifier 47, the sampling switch 48, and the holding capacitor 48 sample and hold the signal voltage of the maximum amplitude level during the video signal period, and output it via the output terminal 64.
The image signal output from the output terminal 64 becomes a video signal based on the feedthrough voltage in which the low frequency 1 / f noise is removed and the reset noise and the feedthrough periods t1 and t2 are removed.

Further, in order to remove the fluctuation component of the clamp reference voltage VR and the sampling noise at the time of sampling and holding, the buffer amplifier 54, the capacitor 55 for the feedthrough clamp, the switch 56 for the feedthrough clamp, and the buffer amplifier. 57, a non-signal side sample holder 43 including a sampling switch 58 and a holding capacitor 59 is provided in parallel in the same circuit configuration as the signal side sample holder 42,
The output signals of the output terminals 64 and 65 corresponding to these sample holders 42 and 43 are input in a differential form to a differential amplifier 72 using a constant current source having an excellent common-mode rejection ratio, and the clamp reference voltage VR. The fluctuating voltage component and sampling noise are removed, and the image signal having an excellent S / N ratio is output.

Further, even if the clamp reference voltage VR is common to the signal-side sample holder 42 and the non-signal-side sample holder 43, the corresponding feed-through clamp switches 46 and 56 and buffer amplifiers 47 and 57, respectively. , Sampling switch 4
Due to variations in 8 and 48, etc., an offset voltage often occurs in the DC voltage obtained at the output terminals 64 and 65 described above.

When the differential amplifier 72 connected to the output terminals 64 and 65 also has a function as an AGC (automatic gain control amplifier) for amplifying the signal level at the time of low illuminance, its maximum The gain is 40 dB (1
In some cases, the DC voltage offset at the output terminals 64 and 65 is amplified by the gain, and therefore the output DC voltage of the differential amplifier 72 is set to about 100 times. In some cases, it may change significantly and interfere with normal operation. Corresponding to this case, as shown in FIG. 4, a comparator 73 is provided so that the DC voltages at the output terminals 64 and 65 of the sample holders 42 and 43 have the same potential. Are compared by the comparator 73, and the comparison output voltage is input to the feedback clamp control voltage source 60 via the terminal 66 to perform feedback clamp control such that the clamp control voltage VC on the non-signal side is varied. Has become. As shown in FIG. 4, the circuit for varying the clamp reference voltage varies the voltage on the signal side clamping switch 46 side, not on the side connected to the non-signal side clamping switch 56. However, there is no problem in terms of characteristics.

[0013]

In the above-described conventional sample hold circuit 41, the image output signal W output from the CCD image sensor 70 every horizontal period.
As shown in FIG. 2, No. 1 is the first optical black (hereinafter referred to as OB) that outputs an ideal black signal by covering the signal period and the photodiode on the CCD image sensor with aluminum. Of the conventional CCD image sensor 70 as described above, which includes the idle transfer section T2 in which an indefinite signal is output without a photodiode or CCD transfer section, and the third period T3 of OB. In the sample hold circuit 41, the period in which the feedback clamp for absorbing the offset of the DC voltage at the output terminals 64 and 65 can be applied is only the OB period of the image output signal W1 from the CCD image sensor 70. is there. In FIG. 4, the signal given to the amplifier at the next stage is given by the differential form of the output terminals 64 and 65, and the DC voltage outputted from the output terminal 65 on the non-signal side is a black level, It is necessary to compare and match with the DC voltage of the OB period output from the output terminal 64.

However, the OB period signal once used in the feedback clamp is damaged by the clamp, and if it is used twice or more at the same timing, the clamp may be misaligned due to the clamp damage. .

Further, the OB period of a general CCD image sensor is about 3 μsec in the portion corresponding to the first period T1 of OB shown in FIG. 2 and about 0.2 μsec in the second period T2 of OB. Therefore, it is possible to apply the feedback clamp twice with the timing shifted in the OB period T1, but it is difficult to apply the feedback clamp in the OB period T2 because the period is extremely short. For convenience, only two feedback clamps can be used in one horizontal period. However, in the image signal processing corresponding to the CCD image sensor, it is necessary to perform black level adjustment at least in the γ amplification section, and at the time of blanking, in some cases, feedback clamp in the color separation output section. At least two or three feedback clamps are performed. Therefore, the current CCD image sensor has a shortcoming that the OB period is short and it is difficult to clamp the OB period in the next stage. In particular, the feedback clamp in the conventional sample hold circuit 41 shown in FIG. 4 is preferably performed in a period other than the OB period in consideration of the clamp in the OB period in the subsequent signal processing, but it is not possible in the conventional example.

The object of the present invention is to solve the above-mentioned drawbacks,
An object of the present invention is to provide a sample hold circuit which can be clamped for B period.

[0017]

The first configuration of the sample and hold circuit of the present invention is to clamp a first buffer amplifier which receives an image output signal of a CCD image sensor and an output of the first buffer amplifier. A first sample holder for sampling and holding the output of the first clamp circuit and outputting the sample, a second buffer amplifier whose input is AC-grounded with low impedance, and A second clamp circuit for clamping the output of the second buffer amplifier, and a second sample holder for sample-holding and outputting the output of the second clamp circuit. The operation of the first and second buffer amplifiers is stopped during the period so that feedback is applied even during periods other than the optical black period in the image output signal. And characterized in that a means for operating said first, second clamp circuit.

According to a second aspect of the present invention, the first buffer amplifier which receives the image output signal of the CCD image sensor from the first signal input terminal and stops the operation at a predetermined output offset voltage absorption operation control signal. And a voltage level of the output of the first buffer amplifier, which is clamped to a predetermined reference clamp voltage by a predetermined clamp operation control signal and the predetermined output offset voltage absorption operation control signal, and is output.
The first clamp circuit and the output signal of the first clamp circuit are input, the voltage level of the output signal is sampled and held by a predetermined sampling operation control signal, and is output to the first signal output terminal. Sample holder and second
Is connected to the input of a second buffer amplifier which is grounded by AC low impedance and which stops operating at a predetermined output offset voltage absorption operation control signal, and the output voltage of the second buffer amplifier is A second clamp circuit that clamps the clamp operation signal and the predetermined output offset voltage absorption operation signal to a clamp voltage supplied by a predetermined voltage varying unit and outputs the clamp voltage, and an output signal of the second clamp circuit are input. And a second sample holder for sampling and holding the voltage level of the output signal with a sampling operation control signal similar to that of the first sample holder and outputting the sample signal to a second signal output terminal. The clamp voltage in the clamp circuit sets the output voltage level at the first and second signal output terminals to the predetermined output offset. The first and second outputs are given by the voltage varying means for adjusting the output voltage levels of the first and second signal output terminals so as to have the same potential by comparing in the absorption operation control signal period. It is characterized in that the output signals at the terminals are output in a reverse phase relationship.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a sample hold circuit according to an embodiment of the present invention.

As shown in FIG. 1, the sample and hold circuit 1 of the present embodiment has a CCD image sensor 30, a capacitor 31, a comparator 33 and a differential amplifier 32.
Corresponding to, a buffer amplifier 4 which stops the operation at the time of feedback clamp, a capacitor 5 for feedthrough clamp, a switch 6 for feedthrough clamp which is closed at the time of feedthrough clamp and feedback clamp, and a buffer amplifier 7. A sample holder 2 including a sampling switch 8 and a holding capacitor 9 which are closed at the time of sampling;
Buffer amplifier 14 which stops the operation at the time of clamping, capacitor 15 for feedthrough clamp, switch 16 for feedthrough clamp which is closed at the time of feedthrough clamp and feedback clamp, buffer amplifier 17, and sampling switch which is closed at the time of sampling 18 and a capacitor 19 for a holder, a feedback clamp control voltage source 20, and a feedthrough clamp reference voltage source 2
1 and are configured.

In FIG. 1, the capacitor 5 and the switch 6 and the capacitor 15 and the switch 16 are
A clamp circuit that operates via the same clamp operation control signal is formed, and the switch 8, the capacitor 9, the switch 18, and the capacitor 19 operate on the same sampling operation control signal. It forms an and hold circuit.

This embodiment is different from the above-mentioned conventional example in that
The operation of the buffer amplifiers 4 and 14 is stopped during the feeder back clamp operation, and the feedback clamp operation signal is input from the terminal 28, and the signals from the input terminals 22 and 23 are not transmitted to the capacitors 5 and 15 for feedthrough. In addition, in the feedthrough clamp switches 6 and 16, when the feedback clamp operation signal input from the terminal 28 is applied during the feedback clamp, the feedthrough clamp operation signal input from the terminal 27 is applied. Always close it.

The image output signal W1 for each pixel output from the CCD image sensor 30 is as described above.
Three periods t of reset noise, feedthrough, and video signal caused by the reset pulse leaking to the output
The signal required for the level of the video signal, which is divided into 1, t2 and t3, is represented as a difference voltage A between the voltage of the feed-through period and the voltage of the video signal period (see FIG. 3).
The video output signal W1 is input to the sample holder 2 via the terminal 22.

In the sample holder 2, the voltage during the feed-through period t2 of the image input signal is clamped by the feed-through clamp capacitor 5 and the feed-through clamp switch 6 via the buffer amplifier 4. The signal voltage having the maximum amplitude level during the video signal period is sampled and held by the buffer amplifier 7, the sampling switch 8 and the holding capacitor 9, and is output via the output terminal 24. The image signal output from the output terminal 24 is a feedthrough in which low-frequency 1 / f noise is removed and reset noise and feedthrough periods t1 and t2 are removed, as in the above-described conventional example. It is output as a voltage-based video signal.

The non-signal side input terminal 23 is provided with a capacitor 2 in order to prevent a disturbance signal such as noise from jumping in.
3 is grounded via 3 and is made to have an AC low impedance, and a buffer amplifier 14 similar to the sample holder 2 on the signal side, a capacitor 15 for feedthrough clamp, a switch 16 for feedthrough clamp, and a buffer amplifier. It is input to the sample-hold 3 including the switch 17, the sampling switch 17, and the holding capacitor 19, and its output is output via the output terminal 25 on the non-signal side. Needless to say, the sample holder 2 on the signal side and the sample holder 3 on the non-signal side are composed of similar circuits.

The feed-through clamp reference voltage source 21 is provided in the switch 6 for the feed-through clamp on the signal side.
The feedthrough reference voltage VR is supplied by
Switch 16 for feedthrough clamp on the non-signal side
Is the feedthrough reference voltage VR by the feedthrough reference voltage source 21 and this feedthrough clamp VR.
Control voltage source 2 for feedback clamp to be superimposed on
A control voltage VC of 0 is supplied. This control voltage VC is compared with the output of the signal side output terminal 24 and the output of the non-signal side output terminal 25 in the comparator 33 in the feedback clamp period, and the comparison output result is the terminal 2
Control voltage source 20 for feedback clamp via 6
Is a control voltage by being fed back to the output terminals 24 and 25.
The direct-current voltage potentials at are controlled to be the same. Further, the feed-through clamp operation control signals given to the feed-through clamp switches 6 and 16 are made the same, and the sampling operation signals given to the sampling switches 8 and 18 are made the same, so that sampling noise and clamp Since the fluctuation component of the reference voltage VR is output from the output terminals 24 and 25 in the same phase, by configuring the differential amplifier 32 with a differential amplifier that has an excellent common mode rejection ratio and uses a constant current source,
The characteristics higher than those of the conventional example shown in FIG. 4 can be obtained.

During the video signal period of the image output signal output from the CCD image sensor 30, the feedback clamp operation signal input terminal 28 is supplied with the feedback clamp stop signal, and the buffer amplifiers 4 and 14 are The switches 6 and 16 for feed-through clamp and the switches 8 and 18 for sampling perform clamping and sampling for each pixel, respectively, and the comparator 33 is set to the off state. . Therefore, the control voltage VC by the feedback clamp control signal given during the feedback clamp period is held at the same level.

Next, in the feedback clamp period, the feedback clamp operation signal input terminal 28 is supplied with the feedback clamp operation signal, and the buffer amplifiers 4 and 14 stop the operation.
The signals from the input terminals 22 and 23 are feed through.
Not applied to clamp capacitors 5 and 15, and switches 6 and 1 for feedthrough clamp
6 is closed and switches 8 and 1 for sampling
In No. 8, sampling is performed at the timing of each pixel.

For this reason, the signals output to the output terminals 24 and 25 are only the DC potential that does not include the AC signal regardless of the output from the CCD image sensor 30, so that the output terminals of the comparator 33 are the same. Only the DC voltage components output to 24 and 25 are compared and the comparison result is output. As described above, since the signal component from the CCD image sensor can be ignored, the feedback clamp can be performed in the idle transfer section other than the OB period. If feedback clamp can be performed in this idle transfer section, CCD
The feedback clamp in the sample hold circuit for the image sensor eliminates the fear of damaging the OB period, and the entire OB period can be used in the signal processing unit after the sample hold.

Further, in the idle transfer section T2 shown in FIG. 2, there are cases where the potential in the OB period and the DC offset voltage exist, and in such a case, the idle transfer section T2 is entirely feedback-clamped. In the period, only the DC potential is output to the output terminals 24 and 25, the offset voltage component of the idle transfer portion is not output to the differential amplifier 32, and the potential in the OB period is output instead.

Therefore, even when the differential amplifier 32 has a high gain, when the idle transfer portion has an offset voltage in the opposite direction to the signal side, the inverting component is generated in the conventional sample hold circuit. Even if the circuit saturation is large and there is a problem, the problem does not occur in this embodiment.

In this embodiment, buffer amplifiers 4 and 1
When 4 has stopped its operation during the feedback clamp period, its output voltage becomes indefinite, so that the switches 6 and 16 for the feedthrough clamp need to be closed.

If the output impedance of the buffer amplifiers 4 and 14 is sufficiently larger than the impedance of the voltage supplied from the switches 6 and 16 for the feedthrough clamp, the signals output from the buffer amplifiers 4 and 14 will be different. Since the voltages input to the buffer amplifiers 7 and 17 are determined by the feedthrough clamp reference voltage VR and the feedback clamp control voltage VC, it is not necessary to stop the operation of the buffer amplifiers 4 and 14 during the feedback clamp. In this case, it is not necessary to provide a mechanism for stopping the operation of the buffer amplifiers 4 and 14, and the circuit can be simplified.

Further, in the above-mentioned embodiment, the feedback clamp control voltage VC is given to the switch 16 for the feedthrough clamp on the non-signal side. However, by inverting the input phase or the output phase of the comparator 33,
Even if the voltage is applied to the feed-through clamp switch 6 on the signal side, there is no change in characteristics. The details of the operations of the sample holders 2 and 3 are the same as in the case of the conventional example described above.

[0035]

As described above, according to the present invention, the CCD
In response to the image output signal output from the image sensor, the operation of the input buffer amplifier is stopped during the feedback clamp period, and the feedthrough clamp circuit is operated, so that the feedback clamp is performed even during the period other than the OB period. Therefore, there is an effect that the OB can be prevented from being damaged by the clamp, and therefore the clamp deviation can be made extremely small even if the OB period is used in the subsequent clamp operation in the signal processing unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a sample hold circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the output voltage of the CCD image sensor during one horizontal period.

FIG. 3 is a waveform diagram showing an output voltage in one pixel period of the CCD image sensor.

FIG. 4 is a block diagram showing a conventional sample hold circuit.

[Explanation of symbols]

1,41 Sample-hold circuit 4,7,14,17,44,47,54,57 Buffer amplifier 6,8,16,18,46,48,56,58 Switch 2,3,42,43 Sample holder 5, 9, 15, 19, 31, 45, 49, 55, 59,
71 Capacitor 21,61 Feedthrough Clamp Reference Voltage Source 20,60 Feedback Clamp Control Voltage Source 30,70 CCD Image Sensor 33,73 Comparator 32,72 Differential Amplifier

Claims (2)

[Claims] 1. A first clamp circuit, comprising: a first buffer amplifier which receives an image output signal of a CCD image sensor; and a first clamp circuit which clamps an output of the first buffer amplifier. A first sample holder for sample-holding and outputting the output of the second buffer, a second buffer amplifier whose input is AC grounded with low impedance, and a second clamp circuit for clamping the output of the second buffer amplifier. In a sample hold circuit having a second sample holder for sampling and holding the output of the second clamp circuit and outputting the sample hold signal, feedback is applied even in a period other than the optical black period in the image output signal. A means for stopping the operation of the first and second buffer amplifiers and operating the first and second clamp circuits during the period is provided. A sample and hold circuit characterized in that 2. A first image input signal from a CCD image sensor is applied from a first signal input terminal and operation is stopped by a predetermined output offset voltage absorption operation control signal.
Of the buffer amplifier and the output voltage of the first buffer amplifier are clamped to a predetermined reference clamp voltage by a predetermined clamp operation control signal and the predetermined output offset voltage absorption operation control signal and output. A first sample which is input with a clamp circuit and an output signal of the first clamp circuit, samples and holds the voltage level of the output signal with a predetermined sampling operation control signal, and outputs the sample signal to a first signal output terminal. The holder and the second input terminal are connected to an input of a second buffer amplifier which is grounded in an AC low impedance and which stops operating at a predetermined output offset voltage absorption operation control signal. The output voltage is a clamp voltage supplied by a predetermined voltage varying means with the clamp operation signal and the predetermined output offset voltage absorption operation signal. A second clamp circuit for clamping and outputting to the second clamp circuit and an output signal of the second clamp circuit are input, and the voltage level of the output signal is sampled by a sampling operation control signal similar to that of the first sample holder. A second sample holder for holding and outputting to a second signal output terminal, wherein the clamp voltage in the second clamp circuit outputs the output voltage level at the first and second signal output terminals to the predetermined output. The output voltage levels of the first and second signal output terminals are adjusted by the voltage varying means so that the output voltage levels of the first and second signal output terminals are adjusted to the same potential by comparing in the offset absorption operation control signal period. A sample-and-hold circuit, wherein output signals at output terminals are output in a reverse phase relationship.