JP2875431B2 - Noise reduction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a charge coupled device (CC).
D: A simplification of a circuit configuration when a television signal is generated from a solid-state imaging device using a charge coupled device (CC).
The present invention relates to reduction of noise induced by a vertical CCD transfer pulse among noises exceeding the Nyquist frequency included in the output of a D-type solid-state imaging device.

[0002]

2. Description of the Related Art Conventionally, a correlated double sampling method has been used for a signal reading circuit of a CCD type solid-state imaging device. The reduction of the reset noise related to the image sensor output unit and the noise generated by the output amplifier are realized by the correlated double sampling circuit.

FIG. 3 is a circuit diagram showing a configuration of a conventional noise reduction circuit provided with a correlated double sampling circuit. 1, reference numeral 1 denotes an input terminal of a conventional noise reduction circuit, 2 denotes an output terminal of the circuit, 3 denotes a conventional noise reduction circuit, 4 denotes a correlated double sampling circuit, 5 denotes a DC bias circuit, and 8 denotes a negative power supply terminal. Reference numeral 10 denotes a CCD solid-state imaging device, 11 denotes a capacitor, 41 and 42 denote first and second sample and hold circuits, 43 denotes a differential amplifier, and 44 and 45 denote first and second control pulse sources.

First, a signal output from the CCD type solid-state imaging device 10 will be described with reference to FIG.

FIG. 4A shows a CCD solid-state imaging device 10.
This represents one horizontal scanning period of a signal repeatedly output, and includes an image signal period and an optical black level (OB: O
[Picture Black] period and a vertical CCD transfer period. Of these, the period in which the optical black level period and the vertical CCD transfer period are combined is called a blanking period, and is a period during which no display is performed on the screen in a television.

FIG. 4B shows a CCD solid-state imaging device 10.
5 is an enlarged view of the vertical CCD transfer period in the output signal of FIG. This period is an unnecessary period in signal processing, and is a period having a relatively clear waveform in a normal case. However, actually, during this period, the CCD
Since the vertical CCD transfer of the solid-state imaging device 10 is driven, the vertical CCD transfer pulse appears as an induced noise on the output signal of the imaging device.

FIG. 4C shows a CCD type solid-state imaging device 10.
The output signal of FIG. 1 is an enlargement of one pixel in the image signal period, and is divided into three periods of a feed-through period, a pixel signal period, and a reset pulse period. Actual pixel information is represented by the difference between the signal potential during the feedthrough period and the signal potential during the pixel signal period.

As shown in FIG. 3, only the AC component of the output signal of the CCD solid-state imaging device 10 having such a waveform is input to the input terminal 1 of the noise reduction circuit 3 via the capacitor 11, and the DC bias is applied. After the DC component is added again by the circuit 5, it is input to the correlated double sampling circuit 4 connected to the next stage.

The signal input to the correlated double sampling circuit 4 is held at a potential during a feedthrough period by a first sample and hold circuit 41, and is held at a potential during a pixel signal period by a second sample and hold circuit 42. The hold potential in each period is input to the differential amplifier 43. As a result, only the potential difference in each period is output to the output terminal 2 of the noise reduction circuit 3. Therefore, actual pixel information can be extracted from the output signal of the CCD solid-state imaging device 10 during the imaging signal period. In addition, reset noise relating to the output section of the CCD solid-state imaging device 10 and noise generated by its output amplifier are reduced by the correlated double sampling circuit 4.

[0010]

The conventional noise reduction circuit shown in FIG. 3 has a problem that the induced noise caused by the vertical CCD transfer pulse shown in FIG. 4B cannot be reduced. This induced noise has a frequency component exceeding the Nyquist frequency of the correlated double sampling circuit 4, and cannot be reduced by the correlated double sampling method. It is known that the correlated double sampling method can reduce noise below the Nyquist frequency but cannot reduce noise above the Nyquist frequency.

The operation of the correlated double sampling circuit 4 during the vertical CCD transfer period will be described with reference to FIG.

In the vertical CCD transfer period, FIG.
The vertical CCD transfer pulse shown in FIG.
0, the vertical CC is applied as shown in FIG.
CCD type solid-state imaging device 10 at the time of logic transition of D transfer pulse
Inductive noise is generated in the output of. On the other hand, the output pulse of the first control pulse source 44 is a vertical CCD as shown in FIG.
The output pulse of the second control pulse source 45 is synchronized with the logical transition of the transfer pulse, and the output pulse of the second control pulse
It deviates from the logical transition of the CD transfer pulse. Vertical CCD
As a result of such a phase relationship between the transfer pulse and the output pulses of the first and second control pulse sources 44 and 45, the first and second control pulse sources 44 and 45 cause the first and second control pulse sources 44 and 45 to generate the first and second control pulses. When the second sample-and-hold circuits 41 and 42 are respectively controlled, as shown in FIGS. 11E and 11F, a signal including an induced noise component is output from the first sample-and-hold circuit 41, and A signal containing no induced noise component is output from the sample and hold circuit 42. Since the potential difference between the outputs of the first and second sample and hold circuits 41 and 42 is amplified by the differential amplifier 43, the induced noise is not reduced as shown in FIG.
The signal is amplified by the correlated double sampling circuit 4 in a warped manner.

In the signal processing circuit connected to the subsequent stage of the noise reduction circuit 3, a capacitor is connected between the blocks and the signal potential in a blanking period as a non-signal period is clamped to thereby reduce the DC voltage value. Correction has been performed. However, if the amplified induction noise is present in the output signal of the noise reduction circuit 3, an offset voltage is generated between the clamp potential and the original no-signal potential due to the phase relationship with the clamp pulse. It was necessary to add a complicated circuit for removing the noise.

SUMMARY OF THE INVENTION An object of the present invention is to reduce, with a simple structure, induced noise in the output of a CCD solid-state imaging device caused by a vertical CCD transfer pulse.

[0015]

In order to achieve the above object, the present invention provides a noise reduction circuit for reducing noise included in an output signal of a CCD solid-state imaging device. The output signal from the solid-state imaging device is cut off.

Specifically, the present invention relates to a method for selecting a DC signal output from a DC voltage source during a vertical CCD transfer period, so as to select an output signal of a CCD solid-state imaging device and a DC signal from the DC voltage source. And a correlated double sampling circuit to which an output signal of the signal switching circuit is input.

[0017]

According to the present invention, CC is transferred during the vertical CCD transfer period.
Since a DC voltage having no induced noise is input to the correlated double sampling circuit instead of the output signal of the D-type solid-state imaging device, the correlated double sampling circuit reduces the induced noise in the output signal of the CCD solid-state imaging device. Amplification can be prevented.
That is, the induced noise is removed before the correlated double sampling circuit.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a noise reduction circuit according to an embodiment of the present invention having a correlated double sampling circuit. In the figure, 1 is an input terminal of the noise reduction circuit according to the present embodiment, 2 is an output terminal of the same circuit, 3 is a noise reduction circuit according to the present embodiment, 4 is a correlated double sampling circuit,
5 is a DC bias circuit, 6 is a signal switching circuit, 7 is a positive power supply terminal, 8 is a negative power supply terminal, 10 is a CCD solid-state imaging device, 11 is a capacitor, 41 and 42 are first and second sample and hold circuits, 43 is a differential amplifier, 44, 45,
68 is a first to third control pulse sources, 51, 64, 65,
66 is first to fourth resistors, 52 is a reference voltage source, 61 is a constant current source, and 62, 63 and 67 are first to third transistors. However, the output pulse of the third control pulse source 68 is the vertical CCD of the output signal of the CCD solid-state imaging device 10.
It is set to “H” only in the transfer period.

The operation of the noise reduction circuit 3 according to this embodiment having the above configuration will be described.

The output signal of the CCD solid-state imaging device 10 is
The signal is input to the input terminal 1 of the noise reduction circuit 3 of the present invention via the capacitor 11, and the first resistor 51 and the reference voltage source 52
After the DC bias is applied by the DC bias circuit 5 composed of the following, the constant current source 61, the first to third transistors 62, 63, 67, and the second to fourth resistors 64, 6
5, 66 and a third control pulse source 68. Here, the reference voltage source 52 is set such that the base potential of the second transistor 63 becomes higher than the maximum input voltage value in the feedthrough period shown in FIG. And second to fourth resistors 64, 65,
It is assumed that 66 is set.

First, when the output of the third control pulse source 68 is "L", the third transistor 67 is cut off. The first and second transistors 62,
Considering the base potential of No. 63, the second
Since the base potential of the first transistor 62 is lower than the base potential of the transistor 63 of
Transistor 63 is cut off. Therefore, the output signal of the CCD type solid-state imaging device 10 input from the input terminal 1 and supplied with the DC bias is supplied to the correlated double sampling circuit 4 via the emitter follower circuit including the constant current source 61 and the first transistor 62. The CCD type solid-state image sensor 1
After the reset noise relating to the output unit of 0 and the noise generated by the output amplifier thereof are reduced by the correlated double sampling circuit 4, the imaging signal is output from the output terminal 2.

Conversely, when the output of the third control pulse source 68 is "H", the third transistor 67 is in a saturated state, and the collector terminal of the third transistor 67 is substantially connected to the negative power supply terminal 8. The potentials are equal. Therefore,
At this time, the base potential of the second transistor 63 is lower than when the output of the third control pulse source 68 is “L”. At this time, if the second and third resistors 64 and 65 are set so that the base potential of the second transistor 63 is lower than the base potential of the first transistor 62, the first transistor 62 is cut. In the off state, the correlated double sampling circuit 4 connected to the next stage of the signal switching circuit 6 becomes higher than the base potential of the second transistor 63 by the potential difference between the base and the emitter of the second transistor 63. DC voltage is input. The signal output to the output terminal 2 is, as described above, the first and second sample-and-hold circuits 4 controlled by the first and second control pulse sources 44 and 45, respectively.
The difference between the output potentials of the output potentials 1 and 42 is amplified by a differential amplifier 43. In this case, since the input voltages of the first and second sample hold circuits 41 and 42 are DC voltages that are constant over time, only the DC voltage without induced noise is output to the output terminal 2. .

FIG. 2 is a time chart showing an example of a signal waveform of each part in FIG.

As shown in FIG. 2A, the output signal of the CCD type solid-state imaging device 10 has induced noise having a frequency component exceeding the Nyquist frequency caused by the vertical CCD transfer pulse during the vertical CCD transfer period. I do. On the other hand, the output pulse of the third control pulse source 68 is
As shown in FIG. 2B, the output signal of the CCD solid-state imaging device 10 is set to "H" only during the vertical CCD transfer period. As a result, as shown in FIG. 3C, the output waveform of the noise reduction circuit 3 according to the present embodiment, that is, the waveform of the output terminal 2 does not include the induced noise caused by the vertical CCD transfer pulse. .

The signal in the reset pulse period shown in FIG. 4C among the output signals of the CCD type solid-state imaging device 10 is unnecessary for signal processing. If the amplitude is large, the first and second signals are not generated. The input dynamic range is exceeded by the sample and hold circuits 41, 42, etc., and the frequency characteristics of both sample and hold circuits are deteriorated due to saturation of the circuit components. Therefore, usually, a method of inserting a high clip circuit before the sample and hold circuit is adopted. According to this embodiment, the constant current source 61, the first and second transistors 6 among the components of the signal switching circuit 6 in FIG.
2, 63 and the second to fourth resistors 64, 65, 66 correspond to the high clip circuit. In other words, it is possible to remove the above-mentioned induced noise with only one transistor (third transistor) 67 and the third control pulse source 68 only.

[0027]

As described above, according to the present invention, there is provided a configuration in which the output signal from the CCD solid-state image pickup device is cut off during the vertical CCD transfer period so that no induced noise is applied to the correlated double sampling circuit. With the adoption, the induced noise in the output of the CCD solid-state imaging device due to the vertical CCD transfer pulse can be reduced with a simple configuration.
This eliminates the need for adding a complicated circuit for removing induced noise to the signal processing circuit connected to the subsequent stage unlike the conventional one, so that the circuit for generating a television signal from the solid-state imaging device is not necessary. The structure can be simplified. Further, since the signal path is simplified, the generated noise is reduced, which leads to an effect of improving the S / N.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a noise reduction circuit according to an embodiment of the present invention.

FIGS. 2A and 2B are time chart diagrams showing examples of signal waveforms of respective parts in FIG. 1, wherein FIG. 2A shows an output signal waveform of a CCD solid-state imaging device, and FIG. 2B shows an output of a third control pulse source; FIG. 3C is a diagram illustrating a pulse waveform, and FIG. 3C is a diagram illustrating a signal waveform at an output terminal of the noise reduction circuit.

FIG. 3 is a circuit diagram showing a configuration of a conventional noise reduction circuit.

4A and 4B are time charts showing output waveforms of the CCD solid-state imaging device in FIG. 3, wherein FIG. 4A shows one horizontal scanning period of an imaging device output signal, and FIG. FIG. 3C is an enlarged view of one period in an image pickup signal period.

5A and 5B are time charts showing examples of signal waveforms at various parts in FIG. 3, wherein FIG. 5A shows an output signal waveform of a CCD solid-state imaging device, and FIG. (C) shows the waveform of the output pulse of the first control pulse source, (D) shows the waveform of the output pulse of the second control pulse source, and (E) shows the waveform of the output pulse of the first control pulse source. 3 (F) is a diagram showing an output signal waveform of a second sample-hold circuit, and FIG. 3 (G) is a diagram showing a signal waveform of an output terminal of a noise reduction circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal of noise reduction circuit 2 Output terminal of noise reduction circuit 3 Noise reduction circuit 4 Correlated double sampling circuit 5 DC bias circuit 6 Signal switching circuit 7 Positive power supply terminal 8 Negative power supply terminal 10 CCD solid-state imaging device 11 Capacitor 41, 42 sample-and-hold circuit 43 differential amplifier 44,45,68 control pulse source 51,64-66 resistor 52 reference voltage source 61 constant current source 62,63,67 transistor

Claims (1)

(57) [Claims] 1. A noise reduction circuit for reducing noise contained in an output signal of a CCD type solid-state imaging device, wherein said circuit selects a DC signal output from a DC voltage source during a vertical CCD transfer period. A signal switching circuit for switching and outputting an output signal of a CCD solid-state imaging device and a DC signal from the DC voltage source; and a correlated double sampling circuit to which an output signal of the signal switching circuit is input. A noise reduction circuit characterized in that: