JPH10126698A - Output signal processing circuit for ccd image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the phase request accuracy of sample pulses to the dispersion of delay time due to the dispersion of temperature characteristics and a semiconductor even when the operation frequency of a signal processing becomes high. SOLUTION: Reset pulses included in the output signals of a CCD image sensor 11 are detected in a reset pulse reproducing circuit 34 and the phase difference of the reset pulses and reference pulses outputted from a pulse generation circuit 35 is detected in a phase difference detection circuit 37. Based on the detected result, a delay time switching circuit 36 is controlled so as to turn the phase difference to zero and the phase of reference clocks supplied from an oscillator 31 to the pulse generation circuit 35 is controlled through the delay time switching circuit 36.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output signal processing circuit of a CCD image sensor, and more particularly to an output signal processing circuit of a CCD image sensor suitable for use in an image input section of an image signal processing device such as a copying machine.

[0002]

2. Description of the Related Art In recent years, as an image signal processing apparatus such as a copying machine, a digital type having an excellent feature that various image processings such as cut and paste, color correction and editing can be freely performed has been rapidly spread. ing. The basic configuration is, as shown in FIG. 16, an image input unit 151 that reads a document and inputs the image information, and an image data processing unit that performs various processes on image data from the image input unit 151. Part 15
2 and an image output unit 153 for forming and outputting an image corresponding to the image data from the image data processing unit 152.

The digital image signal processing apparatus is shifting to a higher-speed and higher-quality image signal processing apparatus while combining a plurality of functions such as a copying function, a facsimile function, and a printing function. Along with this, the image input unit 151 has also been speeded up, and the reading speed of the original has conventionally been about 20 to 30 sheets in A4 per minute, but in recent years, the one having a function of 50 to 60 sheets has been developed. It is getting.

The operating frequency f of the CCD image sensor constituting the image input unit 151 and its output signal processing circuit
Is given assuming that the total number of pixels of the CCD image sensor is N,
The following relationship holds between the reading speed v and the reading density m. f = v × m × N Therefore, the operating frequency f of the output signal processing circuit of the CCD image sensor constituting the image input unit 151 is proportional to the reading speed v of the document, and is vertical and horizontal for the reading density m. It is proportional to the square because there is an element of direction.

Therefore, for example, in order to increase the reading speed v of a document from 30 sheets to 60 sheets at A4 per minute, the operating frequency f of image processing is doubled, and the reading density m is 400 pixels per inch. In order to increase the definition to 600 pixels, the operating frequency of the image processing needs to be increased by 2.25 times. Thus, C in the image signal processing device is
The output signal processing circuit of the CD image sensor is required to have a higher operating frequency f in the future.

Hereinafter, an image input unit 15 of the image signal processing device will be described.
The output signal processing circuit of the general CCD image sensor constituting the first embodiment will be described. FIG. 17 is a block diagram showing a conventional example of an output signal processing circuit of a CCD image sensor. In FIG. 17, a CCD image sensor 201,
The CCD drive unit 200 including the drive signal generation circuit 202 and the output buffer amplifier 203, etc.
Since optical position adjustment such as skew and MTF (Modulation Transfer Function) is required, a configuration in which the substrate is separated from the output signal processing circuit unit 300 is generally adopted.

Normally, to drive the CCD image sensor 201, transfer clocks φ1, φ2, reset pulse φRS, shift pulse φSH, final stage transfer pulse φ2
B is supplied from the drive signal generation circuit 202. Light source 401
The reflected light from the document 402 based on the irradiation light is incident on the imaging area of the CCD image sensor 201, is converted into an electric signal by the CCD image sensor 201, and is output through an output buffer 202 and a transmission line 403. It is sent to the circuit unit 300.

The output signal processing circuit 300 includes a CDS (correlated double sampling) circuit 301, an S / H (sample and hold) circuit 302, a gain adjustment circuit 303, a DC adjustment circuit 304, and an ADC (analog / digital conversion) circuit 3.
05, light-time correction circuit 306, gap correction circuit 307,
It comprises a clock generation circuit 308, a DAC (digital / analog conversion) circuit 309, and a line memory 310.

Next, the output signal processing circuit section 30 having the above configuration
The circuit operation of 0 will be described. Output signal processing circuit 3
At 00, the output signal of the CCD image sensor 201 (hereinafter simply referred to as CCD output signal) is output after the feedthrough period is clamped by the CDS circuit 301, so that 1 / f superimposed on the CCD output signal.
Noise and kTC noise (reset noise) are reduced. Thereafter, in the S / H circuit 302, only the signal component is extracted by sampling the signal output period to remove the reset feed-through component.

[0010] Then, R
The input signals (red), G (green), and B (blue) are adjusted in magnitude, the DC level is adjusted by the DC adjustment circuit 304, and then converted to a digital value by the ADC circuit 305. A shading correction process is performed on the digital signal by the light-time correction circuit 306. An original reading unit (not shown) is provided with a standard white plate, and in shading correction, processing is performed using information read from the standard white plate. The standard white plate is a white plate having an optical density of 0.07, and stores a value A obtained by reading the white plate for each pixel.

Here, assuming that the value when the original 402 is read is X and the DC offset level is B, the lightness correction circuit 306 performs an arithmetic process based on the following equation. X ′ = 255 (X−B) / (A−B) where the digital signal is 8 bits and the maximum value is 25
5 R, which is thus corrected for shading,
The G and B signals are sent to the image data processing unit 152 in FIG. 16 after the registration correction of R, G and B is performed by the gap correction circuit 307.

[0012]

All the sample pulses of data such as CDS and sample hold necessary for the operation of these circuits are detected by a clock generation circuit 308 from an oscillation clock of an oscillator (not shown) and a CCD output signal. It is generated by dividing, inverting, delaying, and performing a logical operation on the basis of the reset pulse (for example, see Japanese Unexamined Patent Application Publication No.
-83645). Therefore, at the time of high-speed operation, due to the delay variation of the arithmetic element used at that time, the delay variation exceeds the timing requirement specification of the sample pulse, and work such as individual adjustment at the time of product shipment has been required.

Taking the operation at 50 MHz as an example, the parallel 2
In the case of the output type CCD image sensor 201, 1
The operating frequency is 25 MHz per output, and one clock period is 40 ns. The signal output period is 50
Assuming that the clock is driven by a clock having a% duty, half of the time is 20 ns, and of this period, the data determination period is a half of about 10 ns. In order to sample this data, the phase accuracy of the sample pulse is ± 5.
ns or more is required. Further, in the CDS circuit 301, since the feedthrough period after reset is about 5 ns, the phase accuracy of the sample pulse is required to be ± 2.5 ns or more.

Thus, the data sample pulse is
Based on the oscillation clock of the oscillator or the reset pulse detected from the CCD output signal, if it is generated by a combination of buffer elements for frequency division, inversion, delay, logical operation or signal transmission, the delay of each semiconductor element Due to variations in time, it has been difficult to achieve the required phase accuracy during high-speed operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to reduce variations in delay time due to variations in temperature characteristics and semiconductors even when the operating frequency of signal processing increases. It is another object of the present invention to provide an output signal processing circuit for a CCD image sensor which can realize the required phase accuracy of a sample pulse.

[0016]

An output signal processing circuit of a CCD image sensor according to the present invention includes a reset pulse detecting means for detecting a reset pulse included in an output signal of the CCD image sensor, and an output signal of the CCD image sensor. Timing pulse generating means for generating a timing pulse for sampling and a reference pulse corresponding to the reset period of the output signal of the CCD image sensor, and phase comparing means for comparing the phase of the reset pulse with the reference pulse and detecting the phase difference And a phase difference adjusting means for adjusting the phase difference between the reset pulse and the reference pulse based on the comparison result of the phase comparing means.

In the output signal processing circuit of the CCD image sensor having the above-mentioned configuration, the timing pulse generating means includes:
In addition to the timing pulse for sampling the output signal of the CD image sensor, a reference pulse corresponding to the reset period of the output signal of the CCD image sensor is generated. The phase comparison means detects a phase difference between the detected reset pulse and the reference pulse. In the phase difference adjusting means,
By adjusting the phase difference between the reset pulse and the reference pulse based on the detection result, the relative phase between the output signal of the CCD image sensor and the timing pulse is controlled. Then, signal processing is performed on the output signal of the CCD image sensor based on the timing pulse.

An output signal processing circuit of another CCD image sensor according to the present invention receives a drive pulse for driving the CCD image sensor as an input, and outputs a CC based on the drive pulse.
The configuration is provided with timing pulse generating means for generating a timing pulse for sampling the output signal of the D image sensor.

In another output signal processing circuit for a CCD image sensor having the above-mentioned configuration, the timing palace generating means generates a timing pulse for sampling an output signal of the CCD image sensor based on a driving pulse for driving the CCD image sensor. I do. Then, signal processing is performed on the output signal of the CCD image sensor based on the timing pulse.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, the CCD driving unit 10
A D image sensor 11, a drive signal generating circuit 12 for generating a drive signal therefor, an output buffer 13, and a coupling capacitor 14 connected between the CCD image sensor 11 and the output buffer 13; Tilt,
The substrate is separated from the output signal processing circuit unit 20 to enable optical position adjustment such as skew and MTF. The drive signal generation circuit 12 includes an oscillator 31
Various timing signals for driving the CCD image sensor 11 are generated based on the oscillation clock. CC
The output signal of the D drive unit 10 is transmitted to the output signal processing circuit unit 20 via the transmission line 32.

The output signal processing circuit 20 includes an input buffer 21, a line clamp circuit 22, a CDS circuit 23,
H circuit 24, AGC (auto gain control)
It comprises a circuit 25, an AOC (auto offset control) circuit 26, an A / D (analog / digital) conversion circuit 27, and a shading correction circuit 28. The line clamp circuit 22 is supplied with a line clamp pulse generated by the line clamp pulse generation circuit 33. The line clamp pulse generation circuit 33 generates a line clamp pulse based on a reference clock provided from the oscillator 31.

The output signal of the line clamp circuit 22 is supplied to a reset pulse reproducing circuit 34. The reset pulse reproducing circuit 34 detects (reproduces) a reset pulse included in an output signal of the CCD image sensor 11. C
The DS circuit 23 and the S / H circuit 24 are supplied with a CDS clamp pulse and a sample pulse generated by the pulse generation circuit 35, respectively. Pulse generation circuit 35
Along with the CDS clamp pulse and the sample pulse based on the reference clock of the oscillator 31 which is delayed by a predetermined delay time in the delay time switching circuit 36,
A reference pulse corresponding to the reset period of the output signal of the CCD image sensor 11 is generated.

The reset pulse detected by the reset pulse reproducing circuit 34 and the reference pulse generated by the pulse generating circuit 35 become two inputs of the phase difference detecting circuit 37. The phase difference detection circuit 37 detects a phase difference between the reset pulse and the reference pulse, and outputs a voltage having a DC component proportional to the phase difference. The DC voltage output from the phase difference detection circuit 37 is quantized by an A / D (analog / digital) conversion circuit 38 and supplied to a CPU (central processing unit) 39. The CPU 39 performs LUP (Look Up
The switching of the delay time switching circuit 36 is controlled with reference to the table of the detected voltage versus the phase difference of the phase difference detecting circuit 37 stored in the table 40.

The oscillator 31, the line clamp pulse generating circuit 33, the reset pulse reproducing circuit 34,
The pulse generation circuit 35, the delay time switching circuit 36, the phase difference detection circuit 37, the A / D conversion circuit 38, the CPU 39, and the LUT 40 are mounted on the same substrate as the output signal processing circuit unit 20. However, the oscillator 31 may be independently mounted on both substrates of the CCD drive unit 10 and the output signal processing circuit unit 20. According to this, a transmission line for transmitting a clock between the CCD driving unit 10 and the output signal processing circuit unit 20 is not required, so that
This is advantageous for measures against radiation noise.

In the output signal processing circuit section 20 having the above configuration, the CDS circuit 23 may be of a clamp type,
A subtraction method using a sample hold is known. As an example, the clamp type CDS circuit shown in FIG. 2 will be described as an example. In FIG. 2, a CCD output signal is applied to one end of a resistor R1. The other end of the resistor R1 is connected to the base of the bipolar transistor Q1. The collector of bipolar transistor Q1 is connected to positive power supply Vcc, and the emitter is grounded via resistor R2.

One end of the capacitor C1 is connected to the emitter of the bipolar transistor Q1, and the other end is connected to the gate of the FET Q2. Capacitor C1
Between the other end (gate of FET Q2) and ground,
The switch SW and the capacitor C2 are connected in series. A divided voltage by the resistors R3 and R4 is applied to a common connection point P of the switch SW and the capacitor C2. The resistors R3 and R4 are connected in series between the positive power supply Vcc and the ground.

The drain of the FET Q2 is connected to a positive power supply Vcc, and the source is connected to a negative power supply Vee via a resistor R5. The base of the bipolar transistor Q3 is connected to the source of the FET Q2. The collector of bipolar transistor Q3 is connected to positive power supply Vcc, and the emitter is connected to negative power supply Vee via resistor R6. Then, the CDS output is derived from the emitter of the bipolar transistor Q3.

FIG. 3 shows the timing relationship between the CCD output signal which is an input signal of the CDS circuit 23, the clamp pulse of the CDS circuit 23, and the reset pulse φRS applied to the CCD image sensor 11. The clamp pulse of the CDS circuit 23 is generated during a feed-through period of the CCD output signal.

As shown in FIG. 4, the delay time switching circuit 36 includes, for example, a delay line 41 formed by connecting a plurality of delay elements having a predetermined unit delay time in series, and a delay line 41 obtained from each stage of the delay line 41. And a switch group 42 that receives a plurality of delay clocks sequentially delayed by a given unit delay time and outputs a delay clock having an arbitrary delay time under switching control by the CPU 39. The configuration of the delay time switching circuit 36 is merely an example, and the configuration is not limited to this. That is, in the present example, the delay time is controlled stepwise by switching. However, for example, a configuration in which the delay time is continuously controlled using a sine wave output oscillator may be used.

FIG. 5 is a block diagram showing an example of the configuration of the pulse generation circuit 35. In FIG. 5, the delay clock from the delay time switching circuit 36 is an input clock φ1, and, for example, four delay outputs φ2, φ3, φ obtained by sequentially delaying the input clock φ1 by a predetermined delay time.
4, a delay circuit 43 for generating φ5 is provided. The logical product of the input clock φ1 and the delay output φ3 is A
The reference pulse is generated by the ND gate 44, and the delay output φ3 becomes an A / D pulse as it is.

The AND of the delay output φ2 and the delay output φ4 is taken by the AND gate 45 to generate a clamp pulse, and the AND of the delay output φ4 and the delay output φ5 is taken by the AND gate 46. Generates an S / H pulse. The AND gates 44 to 46 are opened when an enable (EN) pulse is externally applied. The reference pulse is supplied to the phase difference detection circuit 37 by A /
The D pulse is supplied to the A / D conversion circuit 27, and the clamp pulse is supplied to the A / D conversion circuit 27.
The S / H pulse is supplied to the DS circuit 23 and the S / H circuit 24, respectively.

Since the pulse generating circuit 35 having the above configuration is a combination circuit of the delay circuit 43 and a small number of AND gates 44 to 46, it is configured in the same integrated circuit.
The phase relationship between each timing pulse can be set substantially constant. FIG. 6 shows an input clock φ1, delay outputs φ2 to φ5,
Reference pulse, clamp pulse, S / H pulse and A /
The timing relationship of the D pulse is shown.

As is apparent from the timing chart of FIG. 6, delayed outputs φ2, φ3,
φ4 and φ5 are sequentially delayed by a certain delay time τ,
The reference pulse is a period during which the delay output φ1 and the delay output φ3 are both at the “H” level, and the clamp pulse is a period during which the delay output φ2
And the delay output φ4 are both at the “H” level, and the S / H pulse is generated when both the delay output φ4 and the delay output φ5 are at the “H” level.

FIG. 7 is a circuit diagram showing an example of the phase difference detection circuit 37. In FIG. 7, there are provided differential pair transistors Q11 and Q12 whose emitters are commonly connected, and similarly, differential pair transistors Q13 and Q14 whose emitters are commonly connected. These differential pair transistors Q11-Q
14, the bases of the transistors Q11 and Q13 are commonly connected to the (+) input terminal IN11, and the bases of the transistors Q12 and Q14 are connected to the (−) input terminal IN12.
It is connected to the.

A reset pulse detected by the reset pulse reproducing circuit 34 is applied between these input terminals IN11 and IN12. The collectors of the transistors Q11 and Q13 are connected to the positive power supply Vcc via the resistors R11 and R12 and to the output terminals OUT1 and OUT2. From these output terminals OUT1 and OUT2, an output voltage Vout corresponding to the detected phase difference is derived.

Further, differential pair transistors Q15 and Q16 whose emitters are commonly connected are provided, and the collector of the transistor Q15 is connected to the differential pair transistors Q11 and Q11.
The collector of the transistor Q16 is connected to the common emitter connection point of the transistors Q13 and Q14, respectively. The base of the transistor Q15 is connected to the (+) input terminal IN21,
The base of the transistor Q16 has a (-) input terminal IN22.
Connected to each other.

A reference pulse supplied from the pulse generating circuit 35 is applied between these input terminals IN21 and IN22. A current source I is connected between the common emitter connection point of the differential pair transistors Q15 and Q16 and the negative power supply Vee.

Next, the circuit operation of the output signal processing circuit according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG.

First, in the CCD driving section 10, the driving signal generation circuit 12 drives the CCD image sensor 11 based on the oscillation clock of the oscillator 31.
Various timing signals such as clocks (transfer clocks) φ1 and φ2 are generated. When the CCD image sensor 11 is driven based on these timing signals, an image signal is output from the CCD image sensor 11. This image signal is supplied to the coupling capacitor 1
4. The signal is sent to the output signal processing circuit unit 20 via the output buffer 13 and the transmission line 32.

In the output signal processing circuit section 20, the line clamp circuit 22 changes the DC potential in the shielding pixel period (black reference) to a predetermined clamp potential Vclmp for each line output of the image signal supplied from the CCD drive section 10. Is performed. The clamped signal is supplied to the CDS circuit 23 and the reset pulse reproducing circuit 34. In the reset pulse reproducing circuit 34, the clamp output of the line clamp circuit 22 is applied to a predetermined reference voltage Vr.
By comparing with ef, the reset pulse included in the image signal is detected.

Since the noise component of the reset pulse superimposed on the image output waveform is about 500 mV, the reset pulse reproducing circuit 34 uses the reference potential Vref
Is set to a voltage about 250 mV higher than the clamp potential Vclmp, and this reference potential Vref is compared with the image output, so that the reset pulse can be detected as its comparison output waveform. This reset pulse is one input of the phase difference detection circuit 37. Phase difference detection circuit 37
Uses the reference pulse output from the reference pulse generation circuit 35 as the other input.

FIG. 9 shows enlarged waveforms of two inputs and a detection output of the phase difference detection circuit 37. This phase difference detection circuit 37
Detects the phase difference between the reset pulse and the reference pulse,
A voltage having a DC component proportional to the phase difference is output.
The DC voltage corresponding to the phase difference between the reset pulse and the reference pulse is quantized by the A / D conversion circuit 38. The quantized phase difference data is provided to the CPU 39. CP
U39 is a phase difference detection circuit 37 stored in LUP40.
The delay time switching circuit 36 is controlled so as to set an optimum delay time for canceling the phase difference between the reset pulse and the reference pulse with reference to the table of the detected voltage versus the phase difference.

In the delay time switching circuit 36, in FIG. 4, when an arbitrary switch in the switch group 42 is selected by the CPU 39, the reference line delayed by the delay time corresponding to the selected switch on the delay line 41. A clock is obtained. In the pulse generation circuit 35 that generates various timing pulses based on the reference clock, the delay time, that is, the phase of the reference clock is controlled, so that the skew variation between the timing pulses is minimized and the image signal and the sampling are controlled. The phase relative to the pulse can be adjusted.

As described above, the CCD image sensor 1
1 is detected by the reset pulse reproducing circuit 34, the phase difference between the reset pulse and the reference pulse is detected by the phase difference detection circuit 37, and the phase difference is detected based on the detection result. By controlling the phase of the reference clock supplied to the pulse generation circuit 35 so that the phase difference becomes zero, the phase relationship between the image signal output from the CCD image sensor 11 and the sample pulses of data such as CDS and sample hold is kept constant. Can be maintained.

Thus, accurate sampling can be realized, and even if the operating frequency of the signal processing increases with the shift to high-speed reading or high-definition reading,
The required phase accuracy of the sample pulse can be realized with respect to variations in delay time caused by variations in temperature characteristics and semiconductors. The phase adjustment of the timing pulse is periodically performed in a specific operation mode after power-on.
As a result, the phase relationship between the image signal output from the CCD image sensor 11 and the sample pulse can always be kept constant without being affected by aging.

FIG. 10 is a block diagram showing a second embodiment of the present invention. Referring to FIG.
A CCD image sensor 51, a drive signal generation circuit 52 for generating a drive signal for the CCD image sensor 51, an output buffer 53,
An output signal processing circuit section having a coupling capacitor 54 connected between the CD image sensor 51 and the output buffer 53 to enable optical position adjustment such as sensor tilt, skew, and MTF; Reference numeral 60 denotes a configuration in which the substrate is separated. The drive signal generation circuit 52 generates various timing signals for driving the CCD image sensor 51 based on the oscillation clock of the oscillator 71. The output signal of the CCD drive unit 50 is transmitted to the output signal processing circuit unit 60 via the transmission line 72.

The output signal processing circuit section 60 includes an input buffer 61, a line clamp circuit 62, a CDS circuit 63,
H circuit 64, AGC circuit 65, AOC circuit 66, A / D
It comprises a conversion circuit 67 and a shading correction circuit 68. The line clamp circuit 62 receives a line clamp pulse generated by a line clamp pulse generation circuit 73. Line clamp pulse generation circuit 7
3 generates a line clamp pulse based on a reference clock provided from the oscillator 71.

CDS circuit 63, S / H circuit 64 and A
The / D conversion circuit 67 has a CDS clamp pulse, a sample pulse, and an A / D
Each pulse is given. The pulse generation circuit 75
Based on a reference clock of an oscillator 71 which is delayed by a predetermined delay time in a delay time switching circuit 76, CD
A reference pulse corresponding to the reset period of the output signal of the CCD image sensor 51 is generated together with the S clamp pulse, the sample pulse, and the A / D pulse. As the pulse generation circuit 75, as in the case of the first embodiment,
The configuration shown in FIG. 5 is used.

The AGC circuit 65 includes a line clamp circuit 62
In addition, it constitutes reset pulse detecting means for detecting a reset pulse from an image signal in a specific operation mode for adjusting the phase of the timing pulse. This AG
The reset pulse detected by the C circuit 65 and the reference pulse generated by the pulse generation circuit 75 become two inputs of the phase difference detection circuit 77. The phase difference detection circuit 77 detects a phase difference between the reset pulse and the reference pulse, and outputs a voltage having a DC component proportional to the phase difference. As the phase difference detecting circuit 77, a circuit having a configuration as shown in FIG. 7 is used as in the case of the first embodiment.

The DC voltage output from the phase difference detection circuit 77 passes through the AOC circuit 66 to the A / D conversion circuit 6.
7 and is quantized by the A / D conversion circuit 67. The quantized phase difference data is supplied to the CPU 78 via the shading correction circuit 68. CP
U78 is a phase difference detection circuit 77 stored in LUP79.
The switching control of the delay time switching circuit 76 is performed with reference to the table of the detected voltage versus the phase difference. Delay time switching circuit 7
6, the same configuration as shown in FIG. 4 is used as in the first embodiment.

The oscillator 71, the line clamp pulse generating circuit 73, the pulse generating circuit 75, the delay time switching circuit 76, the phase difference detecting circuit 77, the CPU 78 and the LUT 79 are on the same substrate as the output signal processing circuit section 60. Shall be mounted on However, regarding the oscillator 71, the CCD driving unit 50 and the output signal processing circuit unit 60
May be independently mounted on both substrates. According to this, the CCD driving unit 50 and the output signal processing circuit unit 60
This eliminates the need for a transmission line for transmitting a clock between the two, and is therefore advantageous for measures against radiation noise.

Next, the procedure for adjusting the phase of the timing pulse in the output signal processing circuit according to the second embodiment having the above configuration will be described with reference to the timing chart of FIG. 12 in accordance with the flowchart of FIG.

The operation for adjusting the phase of the timing pulse is executed in a specific operation mode after power-on. At this time, the light source may be turned on or off, but is turned off in this embodiment (step S1). Then, the clamp potential Vclmp of the line clamp circuit 62 is switched to the ground level (0 V) (step S2). Next, an enable (EN) pulse (see FIG. 5) to be given to the pulse generation circuit 75 is set to "L" level (step S3), and a clamp pulse of the CDS circuit 63 and a sample pulse of the S / H circuit 64 are generated. To stop.

Next, since the feedthrough component of the reset pulse is usually about 500 mV, this is reduced to about 5 V
The gain of the AGC circuit 65 is set to 10
(Step S4). Next, the AOC circuit 66
Is set to the lowest value that is the lower limit of the A / D reference voltage (step S5). Steps S1 to S5 above
After the above operation is completed, an oscillation clock is supplied from the oscillator 71 to the drive signal generation circuit 52 for driving the CCD image sensor 51 (step S6). Hereinafter, actual processing for adjusting the phase of the timing pulse is performed.

When an oscillating clock is supplied from the oscillator 71, the driving signal generating circuit 52 generates a CC for driving the CCD image sensor 51 based on the oscillating clock.
Various timing signals such as D clocks (transfer clocks) φ1 and φ2 are generated. When the CCD image sensor 51 is driven based on these timing signals, an image signal is output from the CCD image sensor 51. This image signal is sent to the output signal processing circuit unit 60 via the coupling capacitor 54, the output buffer 53, and the transmission line 72.

In the output signal processing circuit section 60, the line clamp circuit 62 changes the DC potential in the shielding pixel period (black reference) to a predetermined clamp potential Vclmp for each line output of the image signal supplied from the CCD drive section 50. Is performed. Since the clamp potential Vclmp at this time is fixed to the ground level, the image signal component is cut by the clamp operation,
Only the reset pulse and the feedthrough component are extracted.

Thereafter, when the CDS circuit 63 and the S / H circuit 64 are operated, the reset noise is cancelled. Therefore, the state in which the generation of the clamp pulse of the CDS circuit 63 and the generation of the sample pulse of the S / H circuit 64 are stopped. And pass the signal through without processing. Then, the output of the S / H circuit 64 is amplified to a specified level by the AGC circuit 65 and then input to the phase difference detection circuit 77. The AGC output of the AGC circuit 65 is obtained by amplifying the reset pulse extracted by the clamp operation of the line clamp circuit 62.

FIG. 13 shows enlarged waveforms of two inputs and a detection output of the phase difference detection circuit 77. This phase difference detection circuit 7
7 detects a phase difference between the reset pulse and the reference pulse, and outputs a voltage having a DC component proportional to the phase difference. The output voltage of the phase difference detection circuit 77 according to the phase difference between the reset pulse and the reference pulse is supplied to the A / D conversion circuit 67 via the AOC circuit 66, and is quantized by the A / D conversion circuit 67. Is done. The quantized phase difference data is stored in a memory (shading memory) in the shading correction circuit 68 (step S7).

The CPU 79 determines whether or not the output voltage of the phase difference detection circuit 77 is below the allowable value by referring to the phase difference data stored in the shading memory (step S8). If not, LUP79
The delay time switching circuit 76 is controlled to set an optimal delay time for canceling the phase difference between the reset pulse and the reference pulse by referring to the table of the detected voltage versus the phase difference of the phase difference detection circuit 77 stored in (Step S9).

In the delay time switching circuit 76, in FIG. 4, when an arbitrary switch in the switch group 42 is selected by the CPU 78, the reference line delayed by the delay time corresponding to the selected switch on the delay line 41 is selected. A clock is obtained. In the pulse generation circuit 75 that generates various timing pulses based on the reference clock, the delay time, that is, the phase of the reference clock is controlled, so that the skew variation between the timing pulses is minimized and the image signal and the sampling are performed. The phase with the pulse can be adjusted.

As described above, the CCD image sensor 5
1 by detecting the phase difference between the reset pulse and the reference pulse included in the output signal of No. 1 and controlling the phase of the reference clock so that the phase difference becomes zero based on the detection result. Since the phase relationship between the image signal output from the image sensor 51 and the sample pulses of data such as CDS and sample hold can be kept constant, accurate sampling can be realized, and with the shift to high-speed reading or high-definition reading. Therefore, even if the operating frequency of the signal processing is increased, the required phase accuracy of the sample pulse can be realized with respect to the variation in the delay time caused by the variation in the temperature characteristic and the semiconductor.

In addition, in the present embodiment, in detecting a reset pulse, in a specific operation mode,
The clamp potential Vclmp of the line clamp circuit 62 is switched to the ground level, the supply of the clamp pulse to the CDS circuit 63 and the supply of the sample pulse to the S / H circuit 64 are stopped, and the reset pulse is set to AGC.
The output is derived as the AGC output of the circuit 65, and the AGC circuit 65 is also used for detecting the reset pulse. Thus, as in the first embodiment, a dedicated reset pulse regeneration circuit 34 for detecting the reset pulse is used. , It is not necessary to provide the circuit configuration, so that the circuit configuration can be simplified.

Further, the output voltage of the phase difference detection circuit 77 according to the phase difference between the reset pulse and the reference pulse is
The signal is supplied to the A / D conversion circuit 67 via the C circuit 66, and the A / D conversion circuit 67 is also used for quantization of the output voltage. Thus, as in the first embodiment, Since there is no need to provide a dedicated A / D conversion circuit 38 for quantizing a voltage corresponding to the phase difference between the reset pulse and the reference pulse, the circuit configuration can be further simplified.

FIG. 14 is a block diagram showing a third embodiment of the present invention. In the first and second embodiments described above, C
Based on the phase difference between the reset pulse and the reference pulse included in the image signal output from the CD image sensor,
Pulse generation circuit 3 that generates various timing pulses
By controlling the phase of the reference clock supplied to the reference pulses 7 and 75, the phase relationship between the image signal and the sample pulse is kept constant. On the other hand, in the third embodiment, the positions of the reset pulse and the reference pulse are changed. By controlling the phase of the image signal based on the phase difference, the phase relationship between the image signal and the sample pulse is kept constant.

In FIG. 14, the CCD driving unit 80
It has a CD image sensor 81, a drive signal generating circuit 82 for generating a drive signal for the CD image sensor 81, an output buffer 83, and a coupling capacitor 84 connected between the CCD image sensor 81 and the output buffer 83. The substrate is separated from the output signal processing circuit unit 90 in order to enable optical position adjustment such as tilt, skew, and MTF.

The drive signal generation circuit 82 generates various timing signals for driving the CCD image sensor 81 based on the oscillation clock of the oscillator 101 supplied via the delay time switching circuit 106. As the delay time switching circuit 106, a circuit having a configuration as shown in FIG. 4 is used as in the first and second embodiments. The output signal of the CCD driving unit 80 is transmitted to the output signal processing circuit unit 90 via the transmission line 102.

The output signal processing circuit section 90 includes an input buffer 91, a line clamp circuit 92, a CDS circuit 93,
H circuit 94, AGC circuit 95, AOC circuit 96, A / D
It comprises a conversion circuit 97 and a shading correction circuit 98. The line clamp circuit 92 is supplied with a line clamp pulse generated by the line clamp pulse generation circuit 103. The line clamp pulse generation circuit 103 generates a line clamp pulse based on a reference clock provided from the oscillator 101.

The output signal of the line clamp circuit 92 is supplied to a reset pulse reproducing circuit 104. The reset pulse reproducing circuit 104 detects (reproduces) a reset pulse included in an output signal of the CCD image sensor 81. The CDS circuit 93 and the S / H circuit 94 are supplied with a CDS clamp pulse and a sample pulse generated by the pulse generation circuit 105, respectively. The pulse generation circuit 105 generates a reference pulse corresponding to a reset period of an output signal of the CCD image sensor 81 together with a CDS clamp pulse and a sample pulse based on a reference clock supplied from the oscillator 101. As the pulse generation circuit 105, a configuration as shown in FIG. 5 is used as in the first and second embodiments.

The reset pulse detected by the reset pulse regenerating circuit 104 and the reference pulse generated by the pulse generating circuit 105 become two inputs to the phase difference detecting circuit 107. The phase difference detection circuit 107 detects a phase difference between the reset pulse and the reference pulse, and outputs a voltage having a DC component proportional to the phase difference. As the phase difference detection circuit 107, one having a configuration as shown in FIG. 7 is used as in the first and second embodiments. Phase difference detection circuit 107
The DC voltage output from is supplied to the CPU 109 after being quantized by the A / D conversion circuit 108. CPU109
Controls switching of the delay time switching circuit 106 with reference to the table of the detected voltage versus the phase difference of the phase difference detection circuit 107 stored in the LUP 110.

The above-described oscillator 101, line clamp pulse generating circuit 103, reset pulse reproducing circuit 1
04, pulse generation circuit 105, delay time switching circuit 10
6. Phase difference detection circuit 107, CPU 108 and LUT
Reference numeral 109 is mounted on the same substrate as the output signal processing circuit unit 90. However, the oscillator 101 may be independently mounted on the substrates of both the CCD drive unit 80 and the output signal processing circuit unit 90. According to this, a transmission line for transmitting a clock between the CCD driving unit 80 and the output signal processing circuit unit 90 becomes unnecessary, and
This is advantageous for measures against radiation noise.

In the output signal processing circuit according to the third embodiment having the above structure, a reset pulse included in an image signal output from the CCD image sensor 81 is detected, and the phase of the reset pulse is compared with the phase of the reference pulse. The basic circuit operation until the phase difference is detected is the same as that in the first embodiment. The difference is that the delay time switching circuit 10 is provided between the CCD driving unit 80 and the oscillator 101.
6 is controlled based on the phase difference between the reset pulse and the reference pulse, so that the phase of the reference clock provided from the oscillator 101 to the drive signal generation circuit 82 in the CCD drive unit 80 is controlled. Is a point.

As described above, the phase difference between the reset pulse and the reference pulse included in the image signal output from the CCD image sensor 81 is detected, and the driving is performed such that the phase difference becomes zero based on the detection result. By controlling the phase of the reference clock applied to the signal generating circuit 82, the phase relationship between the image signal and the sample pulses of data such as CDS and sample hold can be kept constant. As in the case above, accurate sampling can be performed, and even if the operating frequency of signal processing increases with the shift to high-speed reading or high-definition reading, even if the operating frequency of signal processing increases, delay time variations due to temperature characteristics and semiconductor variations can be reduced. As a result, the required phase accuracy of the sample pulse can be realized.

FIG. 15 is a block diagram showing a fourth embodiment of the present invention. In FIG. 15, the CCD driving unit 120
Is a CCD image sensor 121, a drive signal generation circuit 122 for generating a drive signal for the CCD image sensor 121, the CCD image sensor 1
And an output buffer 123 for deriving an image signal output from the sensor 21 to the outside.
The substrate is separated from the output signal processing circuit unit 130 in order to enable optical position adjustment such as F. The image signal output from the CCD driving unit 120 is transmitted to the output signal processing circuit unit 130 via the transmission line 141.

In the CCD drive section 120, for example, transfer clocks φ1 and φ2 for driving the charge transfer section and a signal charge photoelectrically converted by the imaging section are shifted from the drive signal generation circuit 122 to the charge transfer section. Shift pulse φSH, a reset pulse φRS for resetting a charge-voltage converter for converting signal charges into a signal voltage, and a final-stage transfer pulse φ for driving a final-stage gate of the charge transfer unit.
Each drive pulse such as 2B is output.

Of these drive pulses, the transfer clock φ
1, φ2 via buffers 124 and 125, shift pulse φSH via buffer 126, reset pulse φRS via buffer 127, and final stage transfer pulse φSH.
2B is a CCD image sensor 1 via a buffer 128
21 to be driven. The final-stage transfer pulse φ2B is further output to the outside via the buffer 129.

The output signal processing circuit section 130 includes an input buffer 131, a CDS circuit 132, an S / H circuit 133, an AG
C circuit 134, AOC 135, A / D conversion circuit 136,
It comprises a shading correction circuit 137, a buffer 138, a pulse generation circuit 139, and an oscillator 140. CDS circuit 132, S / H circuit 133 and A / D
The conversion circuit 136 is supplied with each timing pulse generated by the pulse generation circuit 139.

The pulse generating circuit 139 includes the CCD driving unit 1
20 and transmitted by the transmission line 142 to the buffer 1
The CDS circuit 132, the S / H circuit 133 and the A / D
A timing pulse to be provided to the conversion circuit 136 is generated. The pulse generation circuit 139 includes first to third
As in the case of the embodiment, the one having the configuration as shown in FIG. 5 is used. In FIG. 5, a final-stage transfer pulse φ2B is used as an input clock φ1. However, no reference pulse is generated.

In the output signal processing circuit section 130,
In the signal processing system described above, the processing operation is performed based on the timing pulse generated by the pulse generation circuit 139 based on the last-stage transfer pulse φ2B, whereas in the other signal processing systems, the processing operation is performed based on the oscillation clock of the oscillator 140. The processing operation is performed. The oscillation clock of the oscillator 140 is further transmitted to the CCD drive unit 120 via the transmission line 143, and is also used as a reference clock of the drive signal generation circuit 122.

In this embodiment, the oscillator 140 is mounted on the substrate of the output signal processing circuit unit 130.
It may be mounted on the substrate of the drive unit 120 or on both substrates. This eliminates the need for a transmission line for transmitting a clock between the CCD drive unit 120 and the output signal processing circuit unit 130, which is advantageous in terms of measures against radiation noise.

In the above configuration, the CCD image sensor 121 outputs an image signal proportional to the reflected light from the original in synchronization with the final-stage transfer pulse φ2B. This image signal is output from the output buffer 123 and the transmission line 141.
Is sent to the output signal processing circuit section 130 via the. The final-stage transfer pulse φ2B synchronized with the image signal is further transmitted to the output signal processing circuit unit 13 via the transmission line 142, and is supplied to the pulse generation circuit 139 as its reference pulse.

The pulse generation circuit 139 generates various timing pulses based on the final-stage transfer pulse φ2B. Among various timing pulses output from the pulse generation circuit 139, the clamp pulse is sent to the CDS circuit 132, the S / H pulse is sent to the S / H circuit 133, and the A / D
The pulses are supplied to the AD conversion circuits 136, respectively. C
The image signal transmitted from the CD drive unit 120 is correlated double-sampled by the CDS circuit 132, and the S / H circuit 13
3 and the AGC circuit 134 and A
After passing through the OC circuit 135, it is digitized by the A / D conversion circuit 136 and supplied to the shading correction circuit 137.

In this example, the last-stage transfer pulse φ2B is used as the reference pulse of the pulse generation circuit 139. However, since the last-stage transfer pulse φ2B and the second-phase transfer clock φ2 are usually in-phase pulses, The transfer clock φ2 can be used as a reference pulse of the pulse generation circuit 139. However, the terminal input capacitance to which the transfer clock φ2 is applied has a value that is at least 10 times larger than that of the case of the final stage transfer pulse φ2B.
The distortion of the pulse waveform of No. 2 is larger than that of the pulse waveform of the final-stage transfer pulse φ2B.

Therefore, the transfer clock φ2 is transmitted to the output signal processing circuit 1 via the transmission line having a large capacitance component.
When the transmission pulse φ2B is transmitted to the pulse generation circuit 139, the final stage transfer pulse φ2B is used as a reference pulse of the pulse generation circuit 139 because not only the pulse waveform distortion is further increased but also the power consumption of the buffer 125 is increased and the reliability may be reduced. It is preferable to use them.

As described above, the CC according to the fourth embodiment
In the output signal processing circuit of the D image sensor, the pulse generation circuit 139 outputs the final-stage transfer pulse φ2B synchronized with the image signal output from the CCD image sensor 121.
Is used as a reference pulse, and various timing pulses are generated based on the reference pulse, so that the phase relationship between the image signal and the sample pulse of the data can always be kept constant. As in the case of the above, accurate sampling can be performed, and even if the operating frequency of signal processing increases with the shift to high-speed reading or high-definition reading, variations in the delay time due to temperature characteristics and semiconductor variations will occur. On the other hand, the required phase accuracy of the sample pulse can be realized.

Further, since the last-stage transfer pulse φ2B of the charge transfer section of the CCD image sensor 121 is used as the reference pulse of the pulse generation circuit 139, the oscillator 140
Transmission line 143, C
The delay time of the transfer line 141 between the CD drive unit 120 and the output signal processing circuit unit 130 and the variation thereof can be easily canceled.

In this embodiment, the pulse generation circuit 3
5, various timing pulses are generated based on the final-stage transfer pulse φ2B. However, in addition to the various timing pulses, the pulse generation circuit 35 also generates a reference pulse corresponding to the final-stage transfer pulse φ2B. As in the first to third embodiments, the phase difference between the last-stage transfer pulse φ2B and the reference pulse is detected, and the relative phase between the last-stage transfer pulse φ2B and the reference pulse is detected based on the detection result. May be configured to be controlled.

[0088]

As described above, the CC according to the present invention is used.
In the output signal processing circuit of the D image sensor, CC
The phase difference between the reset pulse and the reference pulse contained in the output signal of the D image sensor is detected, and the control is performed such that the phase difference between the reset pulse and the reference pulse becomes zero based on the detection result. As a result, the phase relationship between the image signal output from the CCD image sensor and the sample pulses of data such as CDS and sample hold can be kept constant, so that accurate sampling can be realized, and the transition to high-speed reading or high-definition reading is achieved. Accordingly, even if the operating frequency of the signal processing increases, it is possible to achieve the required accuracy of the phase of the sample pulse with respect to the variation in the delay time due to the variation in the temperature characteristics and the semiconductor.

In another output signal processing circuit of a CCD image sensor according to the present invention, a timing pulse for sampling an output signal of the CCD image sensor is generated based on a driving pulse for driving the CCD image sensor, and the timing pulse is generated. The signal processing for the output signal of the CCD image sensor is performed based on the above, so that the phase relationship between the image signal output from the CCD image sensor and the sample pulse of data can always be kept constant, so that accurate sampling can be performed. Achieves the required accuracy of sample pulse phase with respect to variations in delay time caused by temperature characteristics and semiconductor variations, even if the operating frequency of signal processing increases with the shift to high-speed reading or high-definition reading. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a clamp type CDS circuit.

FIG. 3 is a timing chart of a clamp type CDS circuit.

FIG. 4 is a block diagram illustrating an example of a delay time switching circuit.

FIG. 5 is a block diagram illustrating an example of a pulse generation circuit.

FIG. 6 is a timing chart of the pulse generation circuit.

FIG. 7 is a circuit diagram illustrating an example of a phase difference detection circuit.

FIG. 8 is a timing chart for explaining the operation of the first embodiment.

FIG. 9 is a timing chart when a phase difference is detected in the first embodiment.

FIG. 10 is a block diagram showing a second embodiment of the present invention.

FIG. 11 is a flowchart illustrating a processing procedure according to the second embodiment.

FIG. 12 is a timing chart for explaining the operation of the second embodiment.

FIG. 13 is a timing chart when detecting a phase difference in the second embodiment.

FIG. 14 is a block diagram showing a third embodiment of the present invention.

FIG. 15 is a block diagram showing a fourth embodiment of the present invention.

FIG. 16 is a block diagram illustrating a configuration of an image signal processing device.

FIG. 17 is a block diagram showing a conventional example.

[Explanation of symbols]

 10, 50, 80, 120 CCD drive unit 11, 51, 81, 121 CCD image sensor 12, 52, 82, 122 Drive signal generation circuit 20, 60, 90, 130 Output signal processing circuit unit 22, 62, 92 Line clamp Circuits 23, 63, 93, 132 CDS circuits 24, 64, 94, 133 S / H circuits 25, 65, 95, 134 AGC circuits 31, 71, 101, 140 Oscillators 33, 73, 103 Line clamp pulse generation circuits 34, 104 reset pulse regeneration circuit 35, 75, 105, 139 pulse generation circuit 36, 76, 106 delay time switching circuit 37, 77, 107 phase difference detection circuit

Claims (6)

[Claims] 1. An output signal processing circuit of a CCD image sensor for sampling an output signal of a CCD image sensor for photoelectrically converting an image at least once at a predetermined timing and extracting an image signal, the output signal of the CCD image sensor. Reset pulse detecting means for detecting a reset pulse contained therein; a timing pulse for sampling an output signal of the CCD image sensor; and a timing pulse for generating a reference pulse corresponding to a reset period of the output signal of the CCD image sensor. Generating means, phase comparing means for comparing the phase of the reset pulse and the reference pulse and detecting the phase difference, and calculating the phase difference between the reset pulse and the reference pulse based on the comparison result of the phase comparing means. Phase adjustment means for adjusting Output signal processing circuit of the CCD image sensor to. 2. The output signal processing circuit according to claim 1, wherein the phase adjustment unit controls the phase of the reference pulse based on a comparison result of the phase comparison unit. 3. The output signal processing of a CCD image sensor according to claim 1, wherein said phase adjusting means controls a phase of an output signal of said CCD image sensor based on a comparison result of said phase comparing means. circuit. 4. The line clamp means for line-clamping an output signal of the CCD image sensor in a state where the generation of the timing pulse from the timing pulse generation circuit is stopped, and the line clamp means. 2. An output signal processing circuit for a CCD image sensor according to claim 1, further comprising amplification means for amplifying the output of said CCD image sensor. 5. An output signal processing circuit of a CCD image sensor for sampling an output signal of a CCD image sensor for photoelectrically converting an image at least once at a predetermined timing and extracting an image signal, and driving the CCD image sensor. An output signal processing circuit for a CCD image sensor, comprising: a timing pulse generator that receives a driving pulse as input and generates a timing pulse for sampling an output signal of the CCD image sensor based on the driving pulse. 6. The output signal processing circuit for a CCD image sensor according to claim 5, wherein said drive pulse is a pulse for driving a final stage gate of a charge transfer section in said CCD image sensor.