JP2000287137A - Solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance image quality by avoiding the occurrence of a difference in DC levels among signals for reading a plurality of pixels. SOLUTION: In this solid-state image pickup element having a plurality of A/D converters to sequentially select outputs of the A/D converters and to obtain a digital video output, a noise cancel (comparison) section NR1 consists of a plurality of stages of amplifiers 501, 502 and a clamp circuit is provided to 2nd and succeeding stages of amplifiers 502.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device in which a video signal is obtained as a digital signal, and more particularly to a solid-state imaging device having a plurality of A / D converters, which causes conversion characteristics between A / D converters. Variations can be reduced.

[0002]

2. Description of the Related Art As an analog-to-digital converter effective for a solid-state imaging device, there is a technique described in, for example, Japanese Patent Application Laid-Open No. 9-238286. However, the present inventor has noticed that the analog-to-digital conversion characteristics require further improvement.

[0003]

The above-described analog-to-digital converter first starts a counter at a predetermined timing, and generates a reference voltage that changes according to the count value of the counter. Next, the comparator compares the signal voltage extracted from each pixel with the reference voltage, and obtains a latch pulse when the level of the reference voltage that changes with a slope matches the level of the signal voltage. Then, by the latch pulse, the digital count value at the time of generation of the pulse is latched by a latch circuit, and is converted into a digital conversion output. The digital values thus obtained from the respective comparators are sequentially read out during the horizontal period under the control of the horizontal scanning circuit.

Here, usually, in order to make the signal voltage accurate, each comparator performs a process for making the input and output DC levels of the comparator the same before performing the comparison. That is, a switch provided in parallel between the input / output terminals of the comparators is closed once, so-called clamp processing is performed, and input offset variations among the comparators are reduced.

However, due to the parasitic capacitance existing between the control terminal and the input / output terminal of the switch provided in parallel with the comparator during the clamping process, a difference occurs between the threshold voltage of the comparator and the clamp voltage.

[0006] This difference is affected by the switch manufacturing variation, and as a result, a variation occurs between the output of each comparator and the DC level. This variation eventually appears as channel-to-channel variation in digital values obtained in each analog-to-digital converter provided at the subsequent stage.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a solid-state imaging device capable of preventing variation in a DC level between read signals of a plurality of pixels in the same horizontal line direction and improving image quality. And

[0008]

In order to achieve the above object, the present invention has a plurality of analog-to-digital converters, and sequentially selects the outputs of the analog-to-digital converters.
In a solid-state imaging device for obtaining a digital video output, a voltage comparison unit used in the analog-to-digital converter is composed of a plurality of stages of amplifiers, and the second and subsequent stages of the amplifier function as a clamp circuit, and the DC reproduction characteristics of the clamp circuit vary. To reduce the effect of the above.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 mainly shows an analog-to-digital converter of a solid-state imaging device. The configuration of one pixel block PB11 of the imaging unit will be described as a representative. The pixel block unit PB11 includes a switch 402 and a light receiving element 401 connected in series between a power supply 400 and a ground, and a connection point between the switch 402 and the light receiving element 401 is connected to an input terminal of an amplifier 403. Output terminal is switch 40
4 is connected to a signal derivation line (vertical line) VL1.

Although the pixel block PB11 has been described as a representative,
Other pixel blocks PB12 to PBnm (m horizontal pixel number, n
The vertical pixel numbers have the same configuration.

Pixel blocks PB11, PB12,..., PB1m
Denotes a pixel column in a first horizontal line direction, and a pixel block
PB21, PB22,..., PB2m indicate pixel columns in the second horizontal line direction. Since each pixel block has the same configuration, the same reference numeral is assigned. The columns in the vertical direction of each pixel block correspond to the corresponding signal derivation lines (vertical lines) V
L1 to VLm.

The vertical lines VL1 to VLm are noise cancellations (comparisons) each forming a part of an analog-to-digital converter.
Led to the department. Since the configuration of each noise canceling (comparing) unit is the same, the configuration of one noise canceling (comparing) unit N1 will be described as a representative. The vertical line VL1 is connected to one input terminal of the voltage comparator 501 via the capacitor C1. A switch CP1 is connected between the one input terminal and the output terminal of the voltage comparator 501. The other input terminal of the voltage comparator 501 is supplied with the reference voltage from the reference voltage generator 311. An output terminal of the voltage comparator 501 is connected to an input terminal of an inverter (amplifier) 502 via a capacitor C2. A switch C is provided between the input terminal and the output terminal of the inverter 502.
P2 is connected. The output terminal of the amplifier 502 is connected to the drive pulse input terminal G of the corresponding latch circuit 11-1.

The output reference voltage of the reference voltage generator 311 is commonly supplied to each voltage comparator / comparator 501. A latch circuit 11-2 is provided corresponding to the noise canceling (comparing) unit NR2. The output of the amplifier 502 of the noise canceling (comparing) unit NR2 is supplied to the drive pulse input terminal G of the latch circuit 11-2. Thus, the noise canceling (comparing) unit NR1
To NRm, latch circuits 11-1 to 11-m are provided, and these latch circuits 11-1 to 11-m are provided.
At the time when the output of the inverter of the corresponding noise canceling (comparing) unit is inverted, the common counter 31
The count value of 2 can be latched. The output of the counter 312 is also input to the reference voltage generator 311.

A plurality of noise canceling (comparing) units NR1
The reference voltage generator 311 is shared for 〜NRm. The counter 312 is reset at the beginning of the horizontal drive signal HD and counts the clock CLOCK.
The horizontal drive signal HD and the clock CLOCK are
It is also supplied to the timing generator 313, and generates timing signals for various switch controls and the like.

The latch circuits 12-1 to 12-m are provided corresponding to the latch circuits 11-1 to 11-m. These latch the digital values latched by the corresponding latch circuits 11-1 to 11-m all at once with the timing of the horizontal drive signal HD. Latch circuits 12-1 to 1
2-m output terminals are scanning switches 13-1 to 13-m
Connected to each other. These scanning switches 13
-1 to 13-m turn on one after another in one horizontal period, and derive the digital value of the image signal for one scan to the output line 70.

FIG. 2 is a waveform diagram showing the operation timing of the main part of the solid-state imaging device of FIG. FIG. 2A shows the operation waveform of the output switch 404 on the first horizontal line, and FIG. 2B shows the operation waveform of the output switch 404 on the second horizontal line. FIG. 2C shows an operation waveform of the reset switch 402 in the first horizontal line,
FIG. 2D shows operation waveforms of the reset switch 402 in the second horizontal line.

FIG. 2E shows noise cancellation (comparison).
FIG. 2 (f) is an operation waveform diagram of the switch CP1 of FIG.

FIGS. 2 (g) and 2 (h) show signals at the input section of each comparator 501 of the noise canceling (comparing) sections NR1 and NR2, respectively. In the example of the drawing, an example is shown in which an output sig1 exists from the pixel block PB11 on the first horizontal line, and an output sig2 (zero output) exists from the pixel block PB12.

The comparator 501 and the amplifier 502 perform a clamping process.

For the clamping process, for example, as shown in the timing charts of FIGS.
1. After CP2 is once turned on, it is turned off. Here, the off-timing of the subsequent switch CP2 is determined by the switch CP2.
Delay from off timing of 1.

In the drawing, the timings at which the switches CP1 and CP2 are turned on coincide, but the point is that the off-timing of the switch CP2 at the subsequent stage should be later than the off-timing of the switch CP1. Therefore, the on timing of the switch CP2 in the subsequent stage may be delayed from the off timing of the switch CP1.

As described above, when the voltage comparison section is constituted by a plurality of amplifiers and a clamp circuit is provided in the subsequent amplifier, the variation in A / D conversion characteristics between channels due to the variation in the switch CP1 can be reduced by the clamp operation of the switch CP2. Canceled. Due to the variation of the switch CP2,
Although the A / D conversion characteristics between channels vary between channels, the input signal level is (1 / A1) (A
1 is a variation multiplied by the amplification factor of the comparator 501) times, and when viewed from the signal, this variation is substantially eliminated.

In the noise canceling unit according to the present invention,
As described above, the DC variation between channels can be effectively suppressed on the signal output side, and conversely, it can be said that the allowable range of the variation on the imaging region side may be increased. This is advantageous in terms of manufacturing and also in terms of increasing the yield.

The present invention is not limited to the above-described embodiment, and various embodiments are possible. FIG. 3 shows various modifications.

FIG. 3A shows a comparator 501 and a capacitor.
This is an example in which an amplifier 511 is further provided between C2 and C2. FIG.
(B) is an example in which the switch CP1 and the amplifier 511 are omitted as compared with the above embodiment. Further, in the example shown in FIG. 3C, an amplifier 512 is provided at the subsequent stage of the amplifier 502 as compared with the embodiment of FIG. 3B.

The present invention is not limited to the above embodiment.

FIG. 4 shows a basic configuration according to another embodiment of the present invention. That is, in FIG. 4, a portion PB surrounded by a broken line is a pixel portion of the solid-state imaging device, and a cathode of the photoelectric conversion device PD is connected in series to the DC power supply 100 via the reset switch RD and the readout switch device RS. I have. The connection point between the switch elements RD and RS is
Connected to the gate of Q1. One electrode of the switch element Q1 is connected to the DC power supply 100, and the other electrode is grounded via the constant current source 11.

The other electrode is led out as a signal output node, and is led to a noise canceling (comparing) unit 13. In the noise cancellation (comparison) unit 13, the switch S1 is provided at the input node. The output node of the switch S1 is connected to one electrode of each of the capacitors C11 and C12. The other electrode of the capacitor C12 is configured to be supplied with the reference voltage from the reference voltage generation circuit 14 via the switch S2. Capacitor C1
The other electrode of 2 is connected to a parallel circuit of the comparator A1 and the switch S3. Further, the output of the comparator A1 is connected to one electrode of the capacitor C13. The other electrode of the capacitor C13 is connected to the inverter A2 and the switch S
4 is connected to the latch pulse input terminal of the latch circuit 15 via the four parallel circuits.

The count data from the counter 16 is supplied to the latch circuit 15. The count data is also supplied to the reference voltage generation circuit 14.
The reference voltage generation circuit 14 outputs a voltage Vsaw having an amplitude corresponding to the value of the count data. Timing circuit 17
Is a circuit that outputs a timing pulse for turning on and off each switch element, a reset pulse of the counter 16, and a clock.

FIG. 5 shows waveforms for explaining the operation of the above circuit.

When the switch element RS is turned on by the reset pulse (FIG. 5A), the gate of the amplifier element Q1 is set to a high potential. Then, the output voltage Vsig of the amplifier element Q1 becomes high potential, the switch RS is turned off, the switch element S1 is turned on, the switch S3 is turned on, and then the switch S3 is turned off. When the switch S3 is turned on, the potential Va of the output voltage Vsig
And Vth, that is, (Va−Vth) is stored in the capacitor C11. Vth is a threshold voltage of the comparator A1.

Next, the switch S4 is turned on and off. As a result, the DC component remaining as an error is
Is clamped by

Next, the on state of the switch S1 is maintained,
The switch RD is turned on. That is, the signal charge stored in the photoelectric conversion element (photodiode) PD is amplified by the amplification element Q.
Transfer to 1 gate. Then, the output voltage Vsig of the amplification element Q1 becomes a voltage corresponding to the signal charge (the amount of photoelectric conversion). Here, the switch S2 is turned on. Then, the difference voltage between the output voltage Vb and the reference voltage Vsaw at this time, that is, (Vb
−V0) is stored in the capacitor C12.

Next, the switch S1 is turned off, and the switch S1 is turned off.
2 is maintained, and the reference voltage Vsaw is
Is varied based on the count value of. As a result, the reference voltage Vsaw increases or decreases sequentially. After the switch S1 is turned off, only the switch S2 is kept on.

Here, looking at the input voltage Vin of the comparator A1, Vin = Vsaw + (Vb-V0)-(Va-Vth).
By transforming this equation, Vin = Vth + (Vb−Va) + (Vsaw
−V0). That is, the input voltage Vin of the comparator A1 includes a threshold voltage Vth, a potential difference (Va−Vb) between voltages obtained by sampling the input voltage at two points in time, and a change width of the reference voltage (Vsaw−V
0). Here, the reference voltage change width (Vsaw−V
0) and the potential difference (Va−Vb) become zero, Vin = Vth (threshold voltage), and the output of the comparator A1 can be inverted.

The fact that the sum of the reference voltage change width (Vsaw−V0) and the potential difference (Va−Vb) becomes zero means that (Vsaw−Vsaw−Vb).
0) + (Va−Vb) = 0, and (Va−Vb) = − (Vsaw−
V0). FIG. 5H shows how the reference voltage Vsaw changes, and shows a case where Vsaw−V0 = V1 becomes equal to the threshold value Vth. At this time, the output voltage Vout of the comparator A1 changes from the high level VH to the low level VL,
The output of the amplifier A2 is supplied to the latch circuit 15 as a clock for latching.

At this time, the latch circuit 15 latches the count value of the counter 16. The digital output of the latch circuit 15 is an analog-to-digital conversion output.

The analog-to-digital converter is an amplifying element
DC component (noise component) superimposed on the signal line on the output side of Q1
Has no sensitivity to the signal and functions as a noise reduction circuit. In this embodiment, the same effects as those of the embodiment shown in FIG. 1 can be obtained.

[0040]

As explained above, according to the present invention,
It is possible to reduce the influence of variations in AD conversion characteristics among readout signals from a plurality of pixels, thereby improving image quality.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a diagram showing a main part according to another embodiment of the present invention.

FIG. 4 is a diagram showing still another embodiment of the present invention.

FIG. 5 is a timing chart shown for explaining the operation of the circuit of FIG. 4;

[Explanation of symbols]

400 power supply, 401 light receiving element, 402 switch
403 amplifier, 404 switch, PB11 to PBnm pixel block, 501 comparator, 502 amplifier, CP1, CP
2 ... Switch, C1, C2 ... Capacitor.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA06 AA10 AB01 BA14 CA02 DD09 FA06 FA50 5B047 BB02 BC01 CA06 CB17 DB01 5C024 AA01 CA13 CA14 FA01 GA11 HA14 HA18 5C051 AA01 BA03 DA03 DB01 DB08 DB15 DC03 DC07 DE02 DE13 DE17 DE16

Claims (3)

[Claims] A plurality of analog-to-digital converters;
In the solid-state imaging device that sequentially selects the output of the analog-to-digital converter and obtains a digital video output, the voltage comparison unit used in the analog-to-digital converter includes a plurality of amplifiers, and the second and subsequent amplifiers A solid-state imaging device comprising a clamp circuit. 2. The solid-state imaging device according to claim 1, wherein a clamp circuit is provided in a plurality of stages of the plurality of amplifiers, and a timing of turning off the clamp circuit is later in a clamp circuit in a subsequent stage. element. 3. The solid-state imaging device according to claim 1, wherein the voltage comparison unit is supplied with a common reference voltage.